JP2001195034A - Array substrate and its inspection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an array substrate whose cost is capable of being reduced without lowering the measuring accuracy of a circuit for inspection and an inspection method which is an inspection method inspecting short circuits and disconnection of a display device capable of making pixels to be highly accurate and is capable of being applied to the array substrate. SOLUTION: A first signal line X1 and a second signal line X2 which are adjacent with each other are made to be a pair and the first probe PR1 of a circuit for inspection 900 is connected to a connection pad PD1A and, also, a second probe PR2 is connected to a pad for inspection PD1B which is provided on the signal line X2. Then, the short circuit between the signal lines of the pair is detected by writing an anolog signal to the first signal line X1 in a state in which the connection pad PD1A connected to the first probe PR1 is connected electrically to the first signal line X1 by the control of a switch SW1 which is included in a selection circuit 170 and by reading out an output signal from the second signal line X2 connected electrically to the pad for inspection PD1B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate and a method of inspecting the same, and more particularly, to a method of inspecting a display device capable of reducing the number of connections to an external circuit.

[0002]

2. Description of the Related Art Display devices such as polycrystalline silicon TF
In a liquid crystal display device using T, a part of a signal line driving circuit as a driving circuit and a gate line driving circuit can be integrally formed over an array substrate. In this case, a part of the signal line driving circuit, for example, a digital-to-analog conversion circuit (DAC) is also provided outside the substrate. However, as compared with a liquid crystal display device using amorphous silicon TFTs, the connection between the array substrate and the external circuit is reduced. The number of connection wirings can be greatly reduced.

In the above-described display device, for example, when inspecting a short circuit between adjacent signal lines, an inspection pad is provided for each signal line, and a probe of an inspection circuit is connected to both pads. The short circuit between the signal lines is detected by measuring the resistance value.

[0004]

However, in order to inspect for short-circuits between signal lines, not only the number of test pads as many as the number of signal lines are required, but also the number of test pads corresponding to the number of pads is required. Probes are also required. For this reason,
It is necessary to secure the arrangement space for the inspection pads and to perform high-precision alignment, and it is necessary to prepare expensive probes.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has as its object to provide an inspection method for inspecting a short circuit of a display device capable of increasing the definition of pixels, and a method of measuring an inspection circuit. An object of the present invention is to provide an array substrate capable of reducing costs without reducing accuracy and an inspection method applied to the array substrate.

[0006]

In order to solve the above-mentioned problems and achieve the object, an array substrate according to the first aspect of the present invention comprises a plurality of gate lines and a plurality of signal lines arranged orthogonally to each other on the substrate. A transistor disposed at each intersection of the gate line and the signal line; a pixel electrode connected to each transistor; an input terminal to which an analog signal output from the driver IC is input; A selection unit for sequentially selecting and distributing an input analog signal from a plurality of adjacent signal lines, and a test pad arranged between the selection unit and the transistor and electrically connected to the signal line; It is characterized by having.

According to a fifth aspect of the present invention, there is provided a method for inspecting an array substrate, wherein a plurality of gate lines and a plurality of signal lines are arranged on the substrate at right angles to each other, and are arranged at respective intersections of the gate lines and the signal lines. Transistor, a pixel electrode connected to each transistor, an input terminal to which an analog signal output from the driving IC is input, and an analog signal input from the input terminal sequentially selected from a plurality of adjacent signal lines. And a test pad disposed between the select means and the transistor and electrically connected to the signal line. A probe of a test circuit is connected to the test pads arranged on each of the signal line and the second signal line, and the first signal is supplied from the first test pad on the first signal line. An analog signal, reads an output signal output from the second signal line via a second inspection pad on the second signal line, and, based on the output signal read from the second inspection pad, A short circuit between the first signal line and the second signal line is inspected.

According to a sixth aspect of the present invention, there is provided a method for inspecting an array substrate, wherein a plurality of gate lines and a plurality of signal lines are arranged on the substrate at right angles to each other, and are disposed at intersections of the gate lines and the signal lines. Transistor, a pixel electrode connected to each transistor, an input terminal to which an analog signal output from the driving IC is input, and an analog signal input from the input terminal sequentially selected from a plurality of adjacent signal lines. And an inspection pad disposed between the selection unit and the transistor and electrically connected to the signal line, wherein the inspection method of the array substrate comprises: Selecting one signal line, connecting a probe of a test circuit to the input terminal and a test pad arranged on a second signal line adjacent to the first signal line, Write an analog signal from the child to the first signal line, reads the output signal output via the test pads from the second signal line, based on the analog signals read from the test pads, the first
A short circuit between the signal line and the second signal line is inspected.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a display device provided with an array substrate according to the present invention, for example, a polycrystalline silicon TFT will be referred to as a pixel TF.
An embodiment of a light-transmitting liquid crystal display device having a diagonal size of 15 inches as an effective display area and an inspection method applied to the array substrate will be described with reference to the drawings.

As shown in FIG. 1, this liquid crystal display 1
Is a counter substrate 200 disposed opposite to the array substrate 100 at a predetermined distance from the array substrate 100.
And a liquid crystal layer 300 sandwiched between the array substrate 100 and the counter substrate 200 and disposed via an alignment film (not shown). Array substrate 100 and counter substrate 2
00 is attached by a seal member 400 disposed around the periphery.

The array substrate 100 includes a plurality of gate lines Y extending in a row direction, a plurality of signal lines X extending in a column direction, and a plurality of gate lines Y and signal lines X. It includes a pixel thin film transistor or a pixel TFT 110 as a switching element provided at the intersection, and a pixel electrode 120 provided corresponding to each pixel surrounded by the gate line Y and the signal line X.

The pixel TFT 110 is a polycrystalline silicon TFT using a polycrystalline silicon film as a semiconductor layer. Pixel TF
The gate electrode of T110 is connected to the gate line Y, and the source electrode is connected to the signal line X.
The drain electrode of the pixel TFT 110 is the pixel electrode 1
20 and the auxiliary capacitance element 13 in parallel with the pixel electrode 120.
0 is connected to one of the electrodes.

A gate line driving circuit 150 functioning as a gate line driving means for outputting a driving signal for driving the gate line Y is integrally formed on the array substrate 100 in the same process as the pixel TFT 110.

The signal line driving circuit section 160 for outputting a driving signal for driving the signal line X has a signal line driving IC 511 mounted on a flexible wiring board, and the array substrate 1
TCP 500-1, 500- electrically connected to
2,..., 500-6, and a pixel TFT on the array substrate 100
110 and a selection circuit 170 formed by the same process and functioning as selection means.

The TCPs 500-1 to 500-6 correspond to the array substrate 10
0, and are connected to a PCB board 600 as an external circuit board. On this PCB board 600,
Based on a reference clock signal and a digital data signal input from the outside, a control IC for outputting various control signals and a data signal synchronized with the control signal, a power supply circuit, and the like are mounted.

The TCP 500-N is, as shown in FIG.
A PCB-side pad 513 connected to a connection terminal on a connection wiring formed on the PCB substrate 600;
An array-side pad 515 connected to a connection terminal on a connection wiring formed in the array, and various wirings connecting these pads are provided. These PCB side pads 513 and array side pads 515 are made of an anisotropic conductive film (AC
F), and are electrically connected to the PCB substrate 600 and the array substrate 100, respectively.

The signal line driving circuit 160 of the signal line driving circuit unit 160
The C511 outputs a data signal as an analog video signal based on an input signal from the PCB 600.

That is, as shown in FIG. 3, the signal line driving IC 511 includes a shift register 521, a data register 523, a D / A converter 525, and the like. A clock signal and a control signal are input to the shift register 521 from the PCB substrate 600 side. A data signal is input to the data register 523 from the PCB board 600 side. Also, the D / A converter 525 has P
A reference signal is input from the CB substrate 600, and the input data signal is converted into an analog video signal.

Each analog video signal output from the TCP-N signal line driving IC 511 includes an analog video signal corresponding to two signal lines in each horizontal scanning period, and outputs these in a time series. The signal is input to the selection circuit 170 of the signal line drive circuit section 160 formed on the array substrate 100.

The selection circuit 170 includes a signal line driving IC 51
Output terminal O, which is connected to the wiring from the terminal 1 and outputs each serial analog video signal from the signal line driving IC 511.
, And switches SW1 and SW2 for selectively connecting input terminals 1A and 1B, 2A and 2B provided at one end of signal lines X1, X2,. Signal line driving IC 51 in the period
Each serial analog video signal corresponding to two adjacent signal lines from 1 is sequentially distributed to two adjacent signal lines as described later.

In this embodiment, the number of output terminals OUT is half of the number of signal lines X, and drive signals are sequentially output from one output terminal to two signal lines. To further reduce the number of connections, the number of output terminals OUT can be reduced to 1/3 or 1/4 of the number of signal lines X.

For example, the switch SW1 outputs the output terminal O within one horizontal scanning period based on the switch signal.
UT1 and input terminals 1A and 1B of signal lines X1 and X2
Are sequentially connected at predetermined timings. The switch SW1 connects the output terminal OUT1 and the input terminal 1A when the switch signal is ON, and outputs the output terminal OUT1 and the input terminal 1B when the switch signal is OFF.
And connect.

Similarly, the switch SW2 connects the output terminal OUT2 to the input terminals 2A and 2B of the signal lines X3 and X4 at a predetermined timing within one horizontal scanning period. The switch SW2 connects the output terminal OUT2 to the input terminal 2B when the switch signal is ON, and connects the output terminal OUT2 to the input terminal 2B when the switch signal is OFF.

As described above, the gate line driving circuit is formed integrally on the substrate, the signal line driving circuit is formed integrally on the substrate, and the signal line driving I / O mounted on the TCP is formed.
And the number of connection wirings formed on the array substrate even when the pixels are made high definition by the switch of the selection circuit sequentially outputting drive signals to a plurality of signal lines within one horizontal scanning period. Need not be formed corresponding to the number of signal lines, and a sufficient pitch between connection wirings can be secured.

Further, compared with the case where the gate line driving circuit and the signal line driving circuit are all formed on the substrate, it is possible to prevent the wiring length from becoming longer, and to prevent the data signal or the video signal from deteriorating. In addition, the manufacturing cost can be prevented from increasing.

Next, an example of a method of driving each signal line X, that is, an example of a method of writing an analog video signal from each signal line to each pixel will be described.

Here, for example, a case where a video signal is written to the signal lines X1 and X2 connected to the input terminal 1A in the first half of one horizontal scanning period and to the input terminal 1B in the second half will be described.

First, in the first half of one horizontal scanning period, the switch SW1 is connected to the input terminal 1A, and an analog video signal is written to the signal line X1. In a state where the analog video signal is held on the signal line X1, the switch SW1 is connected to the input terminal 1B in the latter half of one horizontal cycle, and the analog video signal is written on the signal line X2.

At this time, the potential of the signal line X1 changes due to the coupling capacitance between the signal lines with the change in the potential of the signal line X2. As a result, the signal line X1 originally has
The potential fluctuates to a potential different from the potential based on the analog video signal to be written, which may cause a display problem.

For example, in the case of V-line inversion driving in which the polarity of a video signal written to a signal line, that is, positive or negative, is switched every one vertical scanning period, and a video signal whose polarity is inverted is written to an adjacent signal line, a uniform screen is used. To be displayed,
For example, when black display is performed by applying a voltage, if the common potential is 5 V, a voltage of 9 V is applied to the positive side and a voltage of 1 V is applied to the negative side.

When the above problem occurs, the signal line X1 is set to 9 V
Is written to the adjacent signal line X2, the potential of the signal line X1 changes in a direction in which the potential of 9V approaches 5V due to the fluctuation of the potential of the signal line X2. In other words, if the black level changes and the fluctuation is large, this leads to the appearance of stripes having different gradations in the vertical direction, which seriously impairs the function of the display device.

Therefore, in this embodiment, by changing the order of writing to the signal lines at least in each of the predetermined vertical scanning period and horizontal scanning period, the pixels having the potential fluctuation can be temporally or spatially dispersed. This makes it difficult to visually recognize the gradation change of the display screen.

That is, as shown in FIG. 4, in the n-th frame, a switch signal which is turned on in the first half of one horizontal scanning period and turned off in the latter half of one horizontal scanning period is input. Thus, the output terminal OUT1 is connected to the input terminal 1A in the first half of one horizontal scanning period, and is connected to the input terminal 1B in the second half. A switch signal that is turned off in the first half of one horizontal scanning period and turned on in the second half is input to the switch SW2. Thereby, the output terminal OUT2
Is connected to the input terminal 2B in the first half of one horizontal scanning period,
The latter half is connected to the input terminal 2A.

The output signal output from the output terminal OUT1 is inverted in the first half and the second half of one horizontal scanning period. In the first half, a positive video signal is written to the signal line X1 via the connected input terminal 1A. In the latter half, connected input terminal 1
A negative video signal is written to the signal line X2 via B.

The output signal output from the output terminal OUT2 is inverted in the first half and the second half of one horizontal scanning period. In the first half, a negative video signal is written to the signal line X4 via the connected input terminal 2B. In the latter half, connected input terminal 2
A positive video signal is written to the signal line X3 via A.

As a result, a positive video signal is written to the pixel 1 from the first half of one horizontal scanning period, and a negative video signal is written to the pixel 2 from the latter half. Also,
A positive video signal is written to the pixel 3 from the second half of one horizontal scanning period, and a negative video signal is written to the pixel 4 from the first half.

At this time, the potential written in the first half of one horizontal scanning period fluctuates due to the influence of the writing potential of the adjacent pixel. That is, in the pixel 1, the potential is slightly lowered from 9 V at the time of writing due to the effect of writing the potential to the pixel 2, and in the pixel 4, the potential is slightly lowered from 1 V at the time of writing due to the effect of writing the potential to the pixel 3. To rise.

Subsequently, as shown in FIG. 5, in the (n + 1) frame, a switch signal which is turned off in the first half of one horizontal scanning period and turned on in the second half is input to the switch SW1. Thus, the output terminal OUT1 is connected to the input terminal 1B in the first half of one horizontal scanning period, and is connected to the input terminal 1A in the second half. Also, the switch SW2 includes:
A switch signal that is turned on in the first half of one horizontal scanning period and turned off in the second half is input. Thereby, the output terminal O
The UT 2 is connected to the input terminal 2A in the first half of one horizontal scanning period, and is connected to the input terminal 2B in the second half.

The output signal output from the output terminal OUT1 is inverted in the first half and the second half of one horizontal scanning period. In the first half, a positive video signal is written to the signal line X2 via the connected input terminal 1B. In the latter half, connected input terminal 1
A negative video signal is written to the signal line X1 via A.

The output signal output from the output terminal OUT2 is inverted in the first half and the second half of one horizontal scanning period. In the first half, a negative video signal is written to the signal line X3 through the connected input terminal 2A. In the latter half, connected input terminal 2
A positive video signal is written to the signal line X4 via B.

As a result, a negative video signal is written to the pixel 1 from the latter half of one horizontal scanning period, and a positive video signal is written to the pixel 2 from the former half. Also,
A negative video signal is written to the pixel 3 from the first half of one horizontal scanning period, and a positive video signal is written to the pixel 4 from the second half.

At this time, in the pixel 2, the potential is slightly lowered from 9 V at the time of writing due to the effect of writing the potential to the pixel 1. Slightly rises from 1V.

As described above, in the n-th frame, the pixel 1
And the potential of the pixel 4 is shifted in a direction closer to the common potential, and the black level becomes thinner than the pixels 2 and 3. Further, in the (n + 1) frame, the potentials of the pixels 2 and 3 are shifted in a direction closer to the common potential, and the black level is lower than that of the pixels 1 and 4.

Since other parts on the display screen operate similarly, in this case, the pixel column connected to the signal line X1 and the pixel column connected to the signal line X2, or the pixel column connected to the signal line X3. The black level of the pixel column and the pixel column connected to the signal line X4 are alternately reduced. As a result, the portion where the display becomes thinner is averaged over the entire display screen, and it is possible to make it difficult to visually recognize the change in the display due to the influence of the potential change.

Therefore, since the number of output terminals of the signal line driving IC is smaller than the number of signal lines, the number of signal line driving ICs can be reduced, and the cost can be reduced. Even if the number is reduced, display can be performed without deteriorating the display quality of the screen.

In the above-described embodiment, the signal line selection cycle is set for each one vertical scanning period. However, the same operation occurs every one horizontal scanning period, and pixels having a fluctuating potential can be dispersed in a checkered pattern. it can. Further, the signal line selection cycle may be changed every one horizontal scanning period and every one vertical scanning period. In this case, the checkerboard arrangement is switched every vertical scanning period, and the pixels having further potential fluctuations can be averaged.

Similarly, the signal line selection cycle is not limited to one horizontal scanning period or one vertical scanning period, and may be executed in a plurality of periods. For example, the signal line selection cycle may be changed every one horizontal scanning period and every two vertical scanning periods. That is, in the above-described embodiment, when attention is paid to a certain pixel, there is a bias that a potential change occurs when a video signal of a specific polarity is written. Can be suppressed.

In the above-described embodiment, the T shown in FIG.
The CPs 500-1 to 500-6 are all the same, and are configured as shown in FIG. That is, each TCP500-
The number of connection wires and the pitch between the connection wires on the PCB substrate 600 and the array substrate 100 corresponding to the N PCB pads 513 and the array pads 515 are the same.

The TCP 500-N has a signal line driving I
An input signal wiring group 531 provided on the C511 corresponding to an input signal from the PCB substrate 600, a signal line driving IC
Output signal wiring group 533 provided corresponding to the output signal from 511, power supply wiring for liquid crystal display device, selection circuit 1
Various wiring groups 535 and 537 such as a power supply wiring for a switch SW and a wiring for a switch signal (control signal) are provided.

As shown in FIG. 2, the signal line driving IC 51
1 wiring group 531 for input signal and wiring group 5 for output signal
33 is disposed between various wiring groups 535 and 537 distributed in substantially equal numbers.

The TCs arranged at both ends of the array substrate 100
P500-1 and P500-6 correspond to the gate line driving circuits 150 provided at both ends of the array substrate 100, and correspond to the various wiring groups 535 and 537.
Power supply wiring and control signal wiring. Of course, when the gate line driving circuit 150 is provided only at one end of the array substrate, one TCP 50
0-1 or 500-6 only, the gate line driving circuit 15
A power supply wiring for 0 and a wiring for control signal may be provided.

As described above, the power supply wiring and control signal wiring for the gate line driving circuit, the power supply wiring and switch signal wiring for the switch of the selection circuit, and the power supply wiring for the liquid crystal display device are formed on the TCP. By forming the wiring drive IC together with the input / output signal wiring, it is not necessary to prepare a separate wiring member, and the cost can be reduced.

In the above-described embodiment, the TCP5
Although 00-1 to 6 were all the same, TCP500-1
And 500-6 and the TCPs 500-2 to 500-5 may have different configurations. That is, TCP500-2
The number of connection wirings on the array substrate 100 corresponding to the array pads 515 to 500-5 is TCP 500-1 and TCP 500
Less than 0-6. Therefore, TCP500-2 ~
In the case of 500-5, the pitch between the connection wirings can be further increased.

More specifically, TCP 500-1 and TCP 500-5
Reference numeral 00-6 denotes a structure as shown in FIG. 2, wherein an input signal wiring group 531 provided on the signal line driving IC 511 in correspondence with an input signal from the PCB substrate 600 and a signal line driving IC 511 The output signal wiring group 533 provided corresponding to the output signal, the power supply wiring for the liquid crystal display device, the power supply wiring for the switch SW of the selection circuit 170 and the wiring for the switch signal (control signal), and the gate line driving circuit 150 And various wiring groups 535 and 537 such as power supply wiring and control signal wiring.

As shown in FIG. 2, the signal line driving IC 51
1 wiring group 531 for input signal and wiring group 5 for output signal
33 is disposed between various wiring groups 535 and 537 distributed in substantially equal numbers.

The TCPs 500-2 to 500-5 have a structure as shown in FIG.
An input signal wiring group 531 provided corresponding to an input signal from the CB substrate 600, and an output signal wiring group 53 provided corresponding to an output signal from the signal line driving IC 511.
3. Various wiring groups 541 and 543 such as a power supply wiring for a liquid crystal display device, a power supply wiring for a switch SW of the selection circuit 170, and a wiring for a switch signal (control signal).

As shown in FIG. 6, the signal line driving IC 51
1 wiring group 531 for input signal and wiring group 5 for output signal
33 is arranged between various wiring groups 541 and 543 distributed in substantially equal numbers.

Various wiring groups 5 in the TCP shown in FIG.
Although the number of lines 35 and 537 is about 20 to 40, various wiring groups 541 in the TCP shown in FIG.
And 543 are about 5 to 20.

As shown in FIG. 7, a TCP 500-1 is connected to one end of the array substrate 100. Array substrate 1
00 includes a connection pad group PD to which the array pad 515 of the TCP 500-1 is connected along one side thereof. In the center of the connection pad group PD, a pad for inputting an output signal from the signal line driving IC 511, a switch signal, and a switch power supply to the selection circuit 170 is provided.

At one end of the connection pad group PD, pads for mainly inputting power and control signals to the gate line drive circuit 150 are provided. Control signals supplied from these pads include, for example, the gate line driving circuit 15
When 0 is constituted by a shift register, it is a clock signal, a start signal, a reset signal, or the like. Power from the liquid crystal display device may be supplied from these pads as needed.

As shown in FIG. 8, TCPs 500-2 to 500-5 are provided at a central portion along one side of the array substrate 100.
Is connected. The array substrate 100 is arranged along one side thereof with array pads 51 of TCPs 500-2 to 500-5.
5 is provided with a connection pad group PD to be connected. The connection pad group PD is provided with pads for inputting an output signal from the signal line driving IC 511, a switch signal, and a switch power supply to the selection circuit 170.

As shown in FIG. 9, a TCP 500-6 is connected to the other end of the array substrate 100. Array substrate 1
00 includes a connection pad group PD to which the array pad 515 of the TCP 500-6 is connected along one side thereof. In the center of the connection pad group PD, a pad for inputting an output signal from the signal line driving IC 511, a switch signal, and a switch power supply to the selection circuit 170 is provided.

At the other end of the connection pad group PD, pads for mainly inputting power and control signals to the gate line drive circuit 150 are provided. Power from the liquid crystal display device may be supplied from these pads as needed.

With the above configuration, TCP 500-2 to TCP 500-5
Reference numeral 00-5 denotes a wiring for inputting an output signal from the signal line driving IC, a power supply for the switch SW of the selection circuit 170 and a wiring for inputting a switch signal.
The number of wirings to be connected can be reduced as compared with P500-1 and P-6. Therefore, the pitch of the pads provided at one end of each wiring can be increased. Thus, high definition can be achieved without impairing reliability.

Next, in the display device as described above,
A first inspection method for inspecting a short circuit of the signal line X (1, 2, 3,...) Of the array substrate 100 will be described.

As shown in FIG. 10, first, the array substrate 1
00 is connected to the inspection circuit 900. This inspection circuit 9
00 is a CPU 90 for controlling internal circuits and switches.
1 and a writing circuit 902 for writing an analog signal to a signal line
And a reading circuit 90 for reading a signal output from a signal line
3 and probes PR (1, 2) connected to the connection pads PD (1, 2, 3,...), Respectively.

The CPU 901 of the test circuit 900 outputs control signals to the write circuit 902, the read circuit 903, and the selection circuit 170 of the array substrate 100 at predetermined timings.

On the other hand, on the array substrate 100 side, the switch SW (1, 2,...)
And the pixel transistor 110N closest to this switch
And inspection pads PD1B (2B, 3B)
B,...). That is, the inspection pad P
D1B is electrically connected to the signal line X2 and is arranged between the input terminal 1B of the switch SW1 included in the selection circuit 170 and the pixel transistor 110N.

Similarly, the other inspection pads PD2B.
For example, it is arranged between the switch of the selection circuit 170 on the even-numbered signal line X2n (n = 1, 2,...) And the pixel transistor closest to this switch.

First, an inspection method for inspecting a short circuit between the first signal line X1 and the second signal line X2 adjacent to each other will be described. These first signal line X1 and second signal line X2 are selected by the same switch SW1 of the selection circuit 170,
Writing and reading of analog signals are performed via the same connection pad PD1.

That is, as shown in FIG. 10, the first probe PR1 is connected to the connection pad PD1A, and the second probe PR2 is connected to the inspection pad PD1B.

The CPU 901 of the inspection circuit 900
Outputs a control signal to the selection circuit 170 such that the output terminal OUT1 of the switch SW1 is connected to the input terminal 1A of the first signal line X1.

Then, the CPU 901 sets the write circuit 902
To control the first signal line X through the first probe PR1.
1 is written with a predetermined analog signal.

Subsequently, the CPU 901 reads the reading circuit 903
To control the second signal line X via the second probe PR2.
Read the output signal from 2.

When a predetermined analog signal is detected from the second signal line X2, the CPU 901 determines that the first signal line X1 and the second signal line X2 are short-circuited, and
If no signal is detected from the second signal line 2, it is determined that no short circuit has occurred between the first signal line X1 and the second signal line X2.

Next, an inspection method for inspecting a short circuit between the second signal line X2 and the third signal line X3 adjacent to each other will be described. The second signal line X2 and the third signal line X3 are respectively selected by different switches of the selection circuit 170, that is, switches SW1 and SW2, and the connection pad PD1 connected to the respective switches SW1 and SW2.
A and the analog signal are written and read via the PD 2A.

At this time, the first probe PR1 is connected to the connection pad PD2A.

That is, the CPU 901 controls the selection circuit 17
0, the output terminal OUT2 of the switch SW2 is set to the third
The control signal is output such that it is connected to the input terminal 2A of the signal line X3.

Then, the CPU 901 controls the writing circuit 902
To control the third signal line X via the first probe PR1.
3, a predetermined analog signal is written.

Subsequently, the CPU 901 reads the reading circuit 903
To control the second signal line X via the second probe PR2.
Read the output signal from 2.

When a predetermined analog signal is detected from the second signal line X2, the CPU 901 determines that the second signal line X2 and the third signal line X3 are short-circuited, and
If no signal is detected from the second signal line 2, it is determined that no short circuit has occurred between the second signal line X2 and the third signal line X3.

Similarly, two signal lines adjacent to each other are paired, and one probe of the test circuit is connected to the connection pad, and the other probe is connected to the test pad provided on the signal line. Then, in a state where the connection pad connected to the one probe and one signal line are electrically connected, an analog signal is written to the one signal line, and the other signal electrically connected to the test pad. By reading the output signal from the signal line, it is possible to detect a short circuit between the pair of signal lines.

As described above, by using a part or all of the connection pads as test pads, it is possible to suppress an increase in the number of test pads, and even when pixels are made finer. The space for arranging the pads can be easily secured, and the advantage of using the polycrystalline silicon TFT can be effectively utilized.

Further, the increase in the number of probes can be suppressed, or the interval between the probes can be made sufficiently large, so that it is possible to provide an inspection circuit which can be easily maintained without increasing the cost. .

Next, in the display device as described above,
A second inspection method for inspecting the signal lines X (1, 2, 3,...) Of the array substrate 100 for a short circuit will be described.

As shown in FIG. 11, first, the array substrate 1
00 is connected to the inspection circuit 900. This inspection circuit 9
00 is a CPU 90 for controlling internal circuits and switches.
1 and a writing circuit 902 for writing an analog signal to a signal line
And a reading circuit 90 for reading a signal output from a signal line
3, the probes PR (1, 2, 3) connected to the connection pads PD (1, 2, 3,...), Respectively, and the second probe P
Switching circuit 9 for switching between R2 and third probe PR3
04.

The CPU 901 of the inspection circuit 900 outputs a control signal to the write circuit 902, the read circuit 903, the switching circuit 904, and the selection circuit 170 of the array substrate 100 at a predetermined timing.

On the other hand, on the array substrate 100 side, the switches SW (1, 2,...) Of the selection circuit 170 connect three signal lines X1, X2,
The input terminals 1A, 1B, and 1C respectively corresponding to X3 are formed so as to be selectable. In addition, the array substrate 100
On the signal line, the switch SW of the selection circuit 170
The test pad PD1 arranged between (1, 2,...) And the pixel transistor 110N closest to this switch.
B, PD1C (PD2B, PD2C,...).

First, an inspection method for inspecting a short circuit between the first signal line X1 and the second signal line X2 adjacent to each other will be described. These first signal line X1 and second signal line X2 are selected by the same switch SW1 of the selection circuit 170,
Writing and reading of analog signals are performed via the same connection pad PD1A.

That is, as shown in FIG. 11, the first probe PR1 is connected to the connection pad PD1A, and the second probe PR2 is connected to the inspection pad PD1C. Further, the third probe PR3 is connected to the connection pad PD1B.

The CPU 901 of the inspection circuit 900
Outputs a control signal to the selection circuit 170 such that the output terminal OUT1 of the switch SW1 is connected to the input terminal 1A of the first signal line X1. Further, the CPU 901 outputs a control signal to the switching circuit 904 to select the third probe PR3.

Then, the CPU 901 sets the write circuit 902
To control the first signal line X through the first probe PR1.
1 is written with a predetermined analog signal.

Subsequently, the CPU 901 reads the reading circuit 903
To control the second signal line X via the third probe PR3.
Read the output signal from 2.

When a predetermined analog signal is detected from the second signal line X2, the CPU 901 determines that the first signal line X1 and the second signal line X2 are short-circuited, and
If no signal is detected from the second signal line 2, it is determined that no short circuit has occurred between the first signal line X1 and the second signal line X2.

Next, an inspection method for inspecting a short circuit between the second signal line X2 and the third signal line X3 adjacent to each other will be described. The second signal line X2 and the third signal line X3 are selected by the same switch SW1 of the selection circuit 170,
Writing and reading of analog signals are performed via the same connection pad PD1A.

That is, the CPU 901 controls the selection circuit 17
0, the output terminal OUT1 of the switch SW1 is connected to the second
It outputs a control signal such as to connect to the input terminal 1B of the signal line X2. Further, the CPU 901 outputs a control signal to the switching circuit 904 to select the second probe PR2.

Then, the CPU 901 controls the writing circuit 902
To control the second signal line X via the first probe PR1.
2, a predetermined analog signal is written.

Subsequently, the CPU 901 executes the reading circuit 903
To control the third signal line X via the second probe PR2.
Read the output signal from 3.

When a predetermined analog signal is detected from the third signal line X3, the CPU 901 determines that the second signal line X2 and the third signal line X3 are short-circuited, and
If no signal is detected from No. 3, it is determined that no short circuit has occurred between the second signal line X2 and the third signal line X3.

Next, an inspection method for inspecting a short circuit between the third signal line X3 and the fourth signal line X4 adjacent to each other will be described. The third signal line X3 and the fourth signal line X4 are respectively selected by different switches of the selection circuit 170, that is, the switches SW1 and SW2, and the connection pad PD1 connected to the respective switches SW1 and SW2.
A and the analog signal are written and read via the PD 2A.

At this time, the first probe PR1 is connected to the connection pad PD2A.

That is, the CPU 901 controls the selection circuit 17
0, the output terminal OUT2 of the switch SW2 is connected to the fourth terminal.
The control signal is output such that it is connected to the input terminal 2A of the signal line X4. Further, the CPU 901 outputs a control signal to the switching circuit 904 to select the second probe PR2.

Then, the CPU 901 controls the writing circuit 902
To control the fourth signal line X via the first probe PR1.
4, a predetermined analog signal is written.

Subsequently, the CPU 901 executes the reading circuit 903
To control the third signal line X via the second probe PR2.
Read the output signal from 3.

When a predetermined analog signal is detected from the third signal line X3, the CPU 901 determines that the third signal line X3 and the fourth signal line X4 are short-circuited, and
When no signal is detected from No. 3, it is determined that no short circuit has occurred between the third signal line X3 and the fourth signal line X4.

Similarly, two signal lines adjacent to each other are paired, and one probe of the test circuit is connected to the connection pad, and the other probe is connected to the test pad provided on the signal line. Then, in a state where the connection pad connected to the one probe and one signal line are electrically connected, an analog signal is written to the one signal line, and the other signal electrically connected to the test pad. By reading the output signal from the signal line, it is possible to detect a short circuit between the pair of signal lines.

Thus, it is possible to obtain the same operation and effect as those of the first inspection method described above.

Next, in the display device as described above,
A third inspection method for inspecting the signal lines X (1, 2, 3,...) Of the array substrate 100 for a short circuit will be described. In the third inspection method, an inspection pad is provided on each signal line to inspect a short circuit between adjacent signal lines, and to simultaneously inspect the operation of a switch included in the selection circuit.

As shown in FIG. 12, first, the array substrate 1
00 is connected to the inspection circuit 900. This inspection circuit 9
00 is a CPU 90 for controlling internal circuits and switches.
1 and a writing circuit 902 for writing an analog signal to a signal line
And a reading circuit 90 for reading a signal output from a signal line
3, the probes PR (1, 2, 3) connected to the connection pads PD (1, 2, 3,...), Respectively, and the second probe P
Switching circuit 9 for switching between R2 and third probe PR3
04.

The CPU 901 of the inspection circuit 900 outputs a control signal to the write circuit 902, the read circuit 903, the switching circuit 904, and the selection circuit 170 of the array substrate 100 at a predetermined timing.

On the other hand, on the array substrate 100 side, the switches SW (1, 2,...) Of the selection circuit 170 are connected to one output terminal OUT1 with respect to the input terminals corresponding to the two signal lines X1 and X2, respectively. 1A and 1B are formed to be selectable. In addition, the array substrate 100 includes a switch SW (1, 2,...) Of the selection circuit 170 on the signal line.
And the pixel transistor 110N closest to this switch
Inspection pads PD1B, PD1C arranged between
(PD2B, PD2C,...). The inspection pads PD1B and PD1C are electrically connected to the respective signal lines.

First, an inspection method for inspecting the operation of the switch SW1 that can select the first signal line X1 and the second signal line X2 adjacent to each other will be described. These first signal lines X
The first and second signal lines X2 are selected by the same switch SW1 of the selection circuit 170 and have the same connection pad PD1A.
To write and read analog signals.

That is, as shown in FIG. 12, the first probe PR1 is connected to the connection pad PD1A, and the second probe PR2 is connected to the inspection pad PD1C. Further, the third probe PR3 is connected to the connection pad PD1B.

The CPU 901 of the inspection circuit 900
Outputs a control signal to the selection circuit 170 such that the output terminal OUT1 of the switch SW1 is connected to the input terminal 1A of the first signal line X1. Further, the CPU 901 outputs a control signal to the switching circuit 904 to select the third probe PR3.

Then, the CPU 901 sets the write circuit 902
To control the first signal line X through the first probe PR1.
A predetermined analog signal is written from the connection pad PD1A connected to No. 1.

Subsequently, the CPU 901 executes the reading circuit 903
To control the first signal line X via the third probe PR3.
An output signal from the inspection pad PD1B on the first device is read.

When the CPU 901 detects a predetermined analog signal from the inspection pad PD1B, the selection circuit 17
When it is determined that the switch SW1 at 0 is operating normally and no signal is detected from the inspection pad PD1B, it is determined that the switch SW1 is abnormal.

Next, an inspection method for inspecting a short circuit between the first signal line X1 and the second signal line X2 adjacent to each other will be described.

That is, the CPU 90 of the inspection circuit 900
1 outputs a control signal to the selection circuit 170 such that the output terminal OUT1 of the switch SW1 is connected to the input terminal 1A of the first signal line X1. Further, the CPU 901 includes:
A control signal for selecting the second probe PR2 is output to the switching circuit 904.

Then, the CPU 901 controls the writing circuit 902
To control the first signal line X through the first probe PR1.
1 is written with a predetermined analog signal.

Subsequently, the CPU 901 executes the reading circuit 903
To control the second signal line X via the second probe PR2.
Read the output signal from 2.

When a predetermined analog signal is detected from the second signal line X2, the CPU 901 determines that the first signal line X1 and the second signal line X2 are short-circuited, and
If no signal is detected from the second signal line 2, it is determined that no short circuit has occurred between the first signal line X1 and the second signal line X2.

Next, an inspection method for inspecting a short circuit between the second signal line X2 and the third signal line X3 adjacent to each other will be described. The second signal line X2 and the third signal line X3 are respectively selected by different switches of the selection circuit 170, that is, switches SW1 and SW2, and the connection pad PD1 connected to the respective switches SW1 and SW2.
A and the analog signal are written and read via the PD 2A.

At this time, the first probe PR1 is connected to the connection pad PD2A.

That is, the CPU 901 controls the selection circuit 17
0, the output terminal OUT2 of the switch SW2 is set to the third
The control signal is output such that it is connected to the input terminal 2A of the signal line X3. Further, the CPU 901 outputs a control signal to the switching circuit 904 to select the second probe PR2.

Then, the CPU 901 controls the writing circuit 902
To control the third signal line X via the first probe PR1.
3, a predetermined analog signal is written.

Subsequently, the CPU 901 executes the reading circuit 903
To control the second signal line X via the second probe PR2.
Read the output signal from 2.

When a predetermined analog signal is detected from the second signal line X2, the CPU 901 determines that the second signal line X2 and the third signal line X3 are short-circuited, and
If no signal is detected from the second signal line 2, it is determined that no short circuit has occurred between the second signal line X2 and the third signal line X3.

In the same manner, two signal lines adjacent to each other are paired, and one probe of the test circuit is connected to the connection pad, and the other probe is connected to the test pad provided on the signal line. Then, in a state where the connection pad connected to the one probe and one signal line are electrically connected, an analog signal is written to the one signal line, and the other signal electrically connected to the test pad. By reading the output signal from the signal line, it is possible to detect a short circuit between the pair of signal lines.

Similarly, a switch included in the selection circuit is operated, and signals are written and read between the connection pad and the inspection pad sandwiching the switch, thereby preparing a new pad. Without this, the operation of the switch can be inspected.

[0131]

As described above, according to the present invention, there is provided an inspection method for inspecting a short circuit of a display device capable of increasing the definition of pixels, and the cost can be reduced without reducing the measurement accuracy of an inspection circuit. And an inspection method applied to the array substrate can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing a configuration of a liquid crystal display device according to an embodiment of a display device provided with an array substrate of the present invention.

FIG. 2 is a diagram schematically showing a configuration of a TCP provided on one side of the liquid crystal display device shown in FIG.

FIG. 3 is a diagram schematically showing a configuration of a signal line driving circuit of the liquid crystal display device shown in FIG. 1;

FIG. 4 is a diagram showing a timing chart when a data signal is written to each pixel of the liquid crystal display device shown in FIG. 1;

FIG. 5 is a diagram showing a timing chart when writing a data signal to each pixel of the liquid crystal display device shown in FIG. 1;

FIG. 6 is a diagram schematically showing a configuration of a TCP provided on one side of the liquid crystal display device shown in FIG. 1;

FIG. 7 is a diagram schematically showing a configuration of a wiring pad provided on one end side of an array substrate of the liquid crystal display device shown in FIG. 1;

FIG. 8 is a diagram schematically showing a configuration of a wiring pad provided at a central portion of an array substrate of the liquid crystal display device shown in FIG. 1;

FIG. 9 is a diagram schematically illustrating a configuration of a wiring pad provided on the other end side of the array substrate of the liquid crystal display device illustrated in FIG. 1;

FIG. 10 is a diagram schematically showing a circuit configuration for explaining a first inspection method for inspecting a short circuit between two signal lines in the inspection method of the array substrate according to the present invention;

FIG. 11 is a diagram schematically showing a circuit configuration for explaining a second inspection method for inspecting a short circuit between two signal lines in the inspection method of the array substrate according to the present invention;

FIG. 12 is a diagram schematically showing a circuit configuration for explaining a third inspection method for inspecting a short circuit between two signal lines in the inspection method of the array substrate according to the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device 100 ... Array substrate 110 ... Polycrystalline silicon thin film transistor 150 ... Gate line drive circuit 160 ... Signal line drive circuit 170 ... Selection circuit 200 ... Counter substrate 300 ... Liquid crystal layer 511 ... Signal line drive IC 900 ... For inspection Circuit 901 CPU 902 Write circuit 903 Read circuit 904 Switching circuit X (1, 2,...) Signal line PD (1A, 2A,...) Connection pad PD (1B, 2B,...) Pad PD (1C, 2C, ...) ... Inspection pad PR (1, 2, 3, ...) ... Probe SW (1, 2, ...) ... Switch

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09F 9/00 352 G09G 3/36 G09G 3/36 G02F 1/136 500

Claims (7)

[Claims] A plurality of gate lines and a plurality of signal lines arranged orthogonally to each other on a substrate; a transistor disposed at each intersection of the gate line and the signal line; and a transistor connected to each transistor. A pixel electrode; an input terminal to which an analog signal output from the driving IC is input; a selection unit for sequentially selecting and distributing the analog signal input from the input terminal from a plurality of adjacent signal lines; An inspection pad disposed between the transistor and the transistor and electrically connected to the signal line. 2. The apparatus according to claim 1, wherein when the number of said signal lines selected by one said selecting means is N, the number of said test pads is (N-1). Array substrate. 3. The signal processing apparatus according to claim 1, wherein the selecting unit divides the signal line into a plurality of signal line groups each including a predetermined number of signal lines, inputs an analog signal corresponding to each of the signal line groups, and The array substrate according to claim 1, wherein the array substrate is sequentially allocated to signal lines corresponding to the signal line group. 4. The array substrate according to claim 1, wherein said array substrate integrally includes gate line driving means for supplying a drive signal to said gate lines. 5. A plurality of gate lines and a plurality of signal lines arranged orthogonally to each other on a substrate, transistors arranged at respective intersections of the gate lines and the signal lines, and connected to the respective transistors. A pixel electrode; an input terminal to which an analog signal output from the driving IC is input; a selection unit for sequentially selecting and distributing the analog signal input from the input terminal from a plurality of adjacent signal lines; A test pad disposed between the transistor and the signal line, the test pad electrically connected to the signal line; and a test method for an array substrate, comprising: a test pad disposed on each of the first signal line and the second signal line adjacent to each other. Connecting a probe of a test circuit to the test pad, writing an analog signal from the first test pad on the first signal line to the first signal line, An output signal output from a signal line via a second inspection pad on the second signal line is read, and the first signal line and the second signal are read based on the output signal read from the second inspection pad. Inspection method for inspecting a short circuit between a wire and a wire. 6. A plurality of gate lines and a plurality of signal lines arranged orthogonally to each other on a substrate, transistors arranged at respective intersections of the gate lines and the signal lines, and connected to each transistor. A pixel electrode; an input terminal to which an analog signal output from the driving IC is input; a selection unit for sequentially selecting and distributing the analog signal input from the input terminal from a plurality of adjacent signal lines; A test pad disposed between the transistor and the signal line, the test pad being electrically connected to the signal line; a test method for an array substrate, comprising: a first signal line selected by the selecting means; And connecting a probe of an inspection circuit to an inspection pad arranged on a second signal line adjacent to the first signal line, and connecting an analog signal from the input terminal to the first signal line. And an output signal output from the second signal line via the inspection pad is read. Based on the analog signal read from the inspection pad, the first signal line and the second signal line are connected to each other. An inspection method for inspecting a short circuit between the two. 7. The method according to claim 6, wherein the inspection circuit outputs a selection signal for selecting the first signal line to the selection unit.