JP2001185573A - Method for manufacturing electronic component - Google Patents

Method for manufacturing electronic component

Info

Publication number
JP2001185573A
JP2001185573A JP2000397702A JP2000397702A JP2001185573A JP 2001185573 A JP2001185573 A JP 2001185573A JP 2000397702 A JP2000397702 A JP 2000397702A JP 2000397702 A JP2000397702 A JP 2000397702A JP 2001185573 A JP2001185573 A JP 2001185573A
Authority
JP
Japan
Prior art keywords
package
internal connection
electrode
shield electrode
connection electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000397702A
Other languages
Japanese (ja)
Other versions
JP3438721B2 (en
Inventor
Kozo Murakami
弘三 村上
Kunihiro Fujii
邦博 藤井
Satoshi Matsuo
聡 松尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2000397702A priority Critical patent/JP3438721B2/en
Publication of JP2001185573A publication Critical patent/JP2001185573A/en
Application granted granted Critical
Publication of JP3438721B2 publication Critical patent/JP3438721B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing electronic components which can alternately decide the position of connection between the internally connected electrode of a package and a wire. SOLUTION: A plurality of internally connected electrodes 14 are made, such that they lead to the end of inside periphery on the top end face of the step 22, at the inwall face of a package, and a shield electrode 15 is made at the inside bottom face, and a plurality of shield electrode nonformation parts 18a and 18b are provided such that they lead to the end of the inside periphery of the package 13, and the angle between one side each of the shield electrode nonforming parts 18a and 18b and one side of the internally connected electrode 14 is arranged to be right-angled, and the intersecting points between one side each of contacting with the side end of the internally connected electrode 14 of the shield electrode nonforming parts 18a and 18b and one side of contacting with the end on inside periphery side of the package 13 of the internally connected electrode 14 are detected severally, whereby the boundary between the inside periphery end and the inside bottom face of the package 13 in the plan view is recognized, and the mounting position into the package 13 of a SAW element 17 is determined.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は例えばＳＡＷデバイ
スなどパッケージ内に素子を収納する電子部品の製造方
法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an electronic component such as a SAW device in which a device is housed in a package.

【０００２】[0002]

【従来の技術】図５は従来のＳＡＷデバイスの上面図、
図６は同断面図である。2. Description of the Related Art FIG. 5 is a top view of a conventional SAW device.
FIG. 6 is a sectional view of the same.

【０００３】内側壁の段差の上面に複数の内部接続電極
１０２を形成したパッケージ１００の内部底面の全体に
シールド電極１０１上に接着層１０５によりＳＡＷ素子
１０３を固定し、ＳＡＷ素子１０３の電極と内部接続電
極１０２とをワイヤ１０４で電気的に接続し、パッケー
ジ１００の上端面に設けたシームリング１０７にリッド
１０６を溶接して構成されていた。[0003] A SAW element 103 is fixed on a shield electrode 101 by an adhesive layer 105 over the entire inner bottom surface of a package 100 in which a plurality of internal connection electrodes 102 are formed on the upper surface of the step on the inner wall. The connection electrode 102 is electrically connected with a wire 104, and a lid 106 is welded to a seam ring 107 provided on an upper end surface of the package 100.

【０００４】[0004]

【発明が解決しようとする課題】この構成によると、シ
ールド電極１０１と内部接続電極１０２とが同じ金属で
形成されているため、パッケージ１００を上面から見た
ときにシールド電極１０１と内部接続電極１０２との境
界の認識が難しく、内部接続電極１０２のワイヤ１０４
との接続位置を精度良く決定するのが困難であった。According to this structure, since the shield electrode 101 and the internal connection electrode 102 are formed of the same metal, when the package 100 is viewed from the top, the shield electrode 101 and the internal connection electrode 102 are formed. It is difficult to recognize the boundary with the wire 104 of the internal connection electrode 102.
It was difficult to accurately determine the connection position with the connection.

【０００５】そこで本発明は、内部接続電極のワイヤと
の接続位置を精度よく決定することのできる電子部品の
製造方法を提供することを目的とするものである。SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for manufacturing an electronic component capable of accurately determining a connection position between an internal connection electrode and a wire.

【０００６】[0006]

【課題を解決するための手段】この目的を達成するため
に本発明は、相対向する壁側に段差を有し、この段差の
上端面に複数の内部接続電極を有し、内部底面にシール
ド電極と、上面から見た時前記内部接続電極の一辺ある
いはその延長線とその一辺が直交するようなシールド電
極非形成部を有するパッケージに素子を実装する第１の
工程と、次に前記内部接続電極の一辺あるいはその延長
線と前記シールド電極非形成部の一辺の交点を少なくと
も二点検出し、前記素子と前記内部接続電極とを接続す
るワイヤの接続位置を決定する第２の工程と、次いで前
記素子と前記内部接続電極とをワイヤで接続する第３の
工程と、その後前記パッケージをリッドで封止する第４
の工程とを備えたものであり、ワイヤの接続位置を精度
良く決定することができる。In order to achieve this object, the present invention has a step on the opposite wall side, a plurality of internal connection electrodes on the upper end face of the step, and a shield on the inner bottom face. A first step of mounting an element on a package having an electrode and a shield electrode non-formed portion in which one side or an extension of the internal connection electrode is orthogonal to one side when viewed from above, and then the internal connection A second step of detecting at least two intersections between one side of the electrode or an extension thereof and one side of the shield electrode non-formed portion, and determining a connection position of a wire connecting the element and the internal connection electrode; and A third step of connecting a device to the internal connection electrode with a wire, and a fourth step of sealing the package with a lid thereafter.
And the connection position of the wire can be accurately determined.

【０００７】[0007]

【発明の実施の形態】本発明の請求項１に記載の発明
は、相対向する壁側に段差を有し、この段差の上端面に
複数の内部接続電極を有し、内部底面にシールド電極
と、上面から見た時前記内部接続電極の一辺あるいはそ
の延長線とその一辺が直交するようなシールド電極非形
成部を有するパッケージに素子を実装する第１の工程
と、次に前記内部接続電極の一辺あるいはその延長線と
前記シールド電極非形成部の一辺の交点を少なくとも二
点検出し、前記素子と前記内部接続電極とを接続するワ
イヤの接続位置を決定する第２の工程と、次いで前記素
子と前記内部接続電極とをワイヤで接続する第３の工程
と、その後前記パッケージをリッドで封止する第４の工
程とを備えた電子部品の製造方法であり、ワイヤの接続
位置を精度良く決定することができる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention has a step on the opposite wall side, a plurality of internal connection electrodes on the upper end face of the step, and a shield electrode on the inner bottom face. And a first step of mounting an element in a package having a shield electrode non-formed portion in which one side of the internal connection electrode or an extension thereof is orthogonal to one side when viewed from above, and then the internal connection electrode A second step of detecting at least two intersections between one side or an extension of the one side and the one side of the shield electrode non-formed portion, and determining a connection position of a wire connecting the element and the internal connection electrode, and then the element And a fourth step of sealing the package with a lid, wherein the third step of connecting the internal connection electrodes with wires is performed, and the fourth step of sealing the package with a lid. Do Door can be.

【０００８】本発明の請求項２に記載の発明は、相対向
する壁側に段差を有し、この段差の上端面に複数の内部
接続電極を有し、内部底面にシールド電極と、上面から
見た時前記内部接続電極の一辺あるいはその延長線とそ
の一辺が直交するようなシールド電極非形成部を有する
パッケージに素子を実装する第１の工程と、次いで前記
素子と前記内部接続電極とをワイヤで接続する第２の工
程と、その後前記パッケージをリッドで封止する第３の
工程とを備え、前記第１の工程において、前記内部接続
電極の一辺あるいはその延長線と前記シールド電極非形
成部の一辺の交点を少なくとも二点検出し、前記素子の
実装位置を決定する電子部品の製造方法であり、素子の
実装位置を高精度に決定することができる。According to a second aspect of the present invention, a step is provided on a wall facing each other, a plurality of internal connection electrodes are provided on an upper end face of the step, a shield electrode is provided on an inner bottom face, and a plurality of internal connection electrodes are provided. A first step of mounting an element in a package having a shield electrode non-formed portion such that one side or an extension of the internal connection electrode and one side thereof are orthogonal to each other when viewed, and then the element and the internal connection electrode A second step of connecting with a wire, and a third step of sealing the package with a lid thereafter, and in the first step, one side of the internal connection electrode or an extension thereof and the formation of the shield electrode are omitted. This is a method for manufacturing an electronic component in which at least two intersections of one side of a portion are checked and the mounting position of the element is determined, and the mounting position of the element can be determined with high accuracy.

【０００９】本発明の請求項３に記載の発明は、相対向
する壁側に段差を有し、この段差の上端面に複数の内部
接続電極を有し、内部底面にシールド電極と、上面から
見た時前記内部接続電極の一辺あるいはその延長線とそ
の一辺が直交するようなシールド電極非形成部を有する
パッケージに素子を実装する第１の工程と、次に前記素
子と前記内部接続電極とをワイヤで接続する第２の工程
と、その後前記パッケージをリッドで封止する第３の工
程とを備え、前記第１及び第２の工程において、前記内
部接続電極の一辺あるいはその延長線と前記シールド電
極非形成部の一辺の交点を少なくとも二点検出し、前記
素子の実装位置及び前記ワイヤの接続位置を決定する電
子部品の製造方法であり、素子の実装位置及びワイヤの
接続位置を精度良く決定することができる。According to a third aspect of the present invention, a step is provided on a wall side opposite to the step, a plurality of internal connection electrodes are provided on an upper end surface of the step, a shield electrode is provided on an inner bottom surface, and a plurality of internal connection electrodes are provided. A first step of mounting an element in a package having a shield electrode non-forming portion such that one side or an extension of the internal connection electrode and one side thereof are orthogonal to each other when viewed, and And a third step of sealing the package with a lid, and in the first and second steps, one side of the internal connection electrode or an extension thereof and the This is a method for manufacturing an electronic component in which at least two intersections of one side of a shield electrode non-formed portion are checked and the mounting position of the element and the connection position of the wire are determined, and the mounting position of the element and the connection position of the wire are accurately determined. It can be determined.

【００１０】以下、本発明の一実施の形態について図面
を参照しながらＳＡＷデバイスを例に説明する。Hereinafter, an embodiment of the present invention will be described with reference to the drawings, taking a SAW device as an example.

【００１１】（実施の形態１）図１は本発明の実施の形
態１，２のＳＡＷデバイスの上面図、図２は図１のＡ−
Ｂ断面図である。(Embodiment 1) FIG. 1 is a top view of a SAW device according to Embodiments 1 and 2 of the present invention, and FIG.
It is B sectional drawing.

【００１２】１０はセラミック基板、１１は第１のセラ
ミック枠体、１２は第２のセラミック枠体でこのセラミ
ック基板１０と第１のセラミック枠体１１と第２のセラ
ミック枠体１２で内側壁に段差２２を有したパッケージ
１３を構成している。また１４は第１のセラミック枠体
１１の上面および第１のセラミック枠体１１とセラミッ
ク基板１０の外側面、さらにセラミック基板１０の底面
の一部に形成した内部接続電極、１５はパッケージ１３
の内底面に形成したシールド電極、１６はシールド電極
１５上に設けた接着層、１７はＳＡＷ素子、１８ａ，１
８ｂはシールド電極非形成部、１９はワイヤ、２０はシ
ームリング、２１はリッドである。Reference numeral 10 denotes a ceramic substrate, 11 denotes a first ceramic frame, and 12 denotes a second ceramic frame. The ceramic substrate 10, the first ceramic frame 11, and the second ceramic frame 12 are provided on the inner wall. A package 13 having a step 22 is formed. Reference numeral 14 denotes an internal connection electrode formed on the upper surface of the first ceramic frame 11, the outer surfaces of the first ceramic frame 11 and the ceramic substrate 10, and a part of the bottom surface of the ceramic substrate 10.
, A shield electrode 16 provided on the shield electrode 15, 17 a SAW element, 18a, 1
8b is a shield electrode non-formed portion, 19 is a wire, 20 is a seam ring, and 21 is a lid.

【００１３】まず、セラミック基板１０の表面、裏面お
よび側面に形成しようとするシールド電極１５及び内部
接続電極１４と同じ形状のメッキ下地層を形成する。First, a plating base layer having the same shape as the shield electrode 15 and the internal connection electrode 14 to be formed on the front, back and side surfaces of the ceramic substrate 10 is formed.

【００１４】次に、このセラミック基板１０上に第１の
セラミック枠体１１を配置する。この第１のセラミック
枠体１１の表面及び外側面にも形成しようとする内部接
続電極１４と同じ形状のメッキ下地層を形成する。Next, a first ceramic frame 11 is disposed on the ceramic substrate 10. A plating base layer having the same shape as the internal connection electrode 14 to be formed on the surface and the outer surface of the first ceramic frame 11 is formed.

【００１５】次いで、この第１のセラミック枠体１１と
外周形状が同じで幅が第１のセラミック枠体１１よりも
小さい第２のセラミック枠体１２を第１のセラミック枠
体１１の上に配置して内側壁に段差２２を有する構成と
して焼成し、セラミック基板１０と第１及び第２のセラ
ミック枠体１１，１２を一体化させてパッケージ１３を
作製する。この第２のセラミック枠体１２の上面にもメ
ッキ下地層を形成している。Next, a second ceramic frame 12 having the same outer peripheral shape as that of the first ceramic frame 11 and having a smaller width than that of the first ceramic frame 11 is disposed on the first ceramic frame 11. Then, firing is performed so as to have a step 22 on the inner wall, and the package 13 is manufactured by integrating the ceramic substrate 10 with the first and second ceramic frames 11 and 12. A plating base layer is also formed on the upper surface of the second ceramic frame 12.

【００１６】ここでセラミック基板１０、第１のセラミ
ック枠体１１、第２のセラミック枠体１２はすべて酸化
アルミニウムを主成分とし、メッキ下地層はタングステ
ンを主成分とするものである。Here, the ceramic substrate 10, the first ceramic frame 11, and the second ceramic frame 12 are all mainly composed of aluminum oxide, and the plating underlayer is mainly composed of tungsten.

【００１７】その後、パッケージ１３のメッキ下地層上
にニッケルメッキを行い、パッケージ１３の第２のセラ
ミック枠体１２の上端面部分に銀ろうを用いてパッケー
ジ１３と同じか同等の熱膨張係数を有するシームリング
２０を設ける。Thereafter, nickel plating is performed on the plating underlayer of the package 13, and the second ceramic frame 12 of the package 13 has the same or equivalent thermal expansion coefficient as that of the package 13 by using silver brazing at the upper end portion thereof. A seam ring 20 is provided.

【００１８】次に再びニッケルメッキを行った後金メッ
キを行い、内部接続電極１４及びシールド電極１５を形
成する。Next, after nickel plating is again performed, gold plating is performed to form the internal connection electrode 14 and the shield electrode 15.

【００１９】図１を見るとわかるように、内部接続電極
１４はパッケージ１３の内側壁の段差２２の上端面（第
１のセラミック枠体１１の上端面）にそれぞれ複数個、
内周端部に至るように形成され、その各辺はパッケージ
１３の各辺（第１のセラミック枠体１１の各辺）に平行
である。すなわち内部接続電極１４は略長方形あるいは
正方形である。As can be seen from FIG. 1, a plurality of internal connection electrodes 14 are provided on the upper end surface of the step 22 on the inner side wall of the package 13 (the upper end surface of the first ceramic frame 11).
It is formed so as to reach the inner peripheral end, and each side thereof is parallel to each side of the package 13 (each side of the first ceramic frame 11). That is, the internal connection electrode 14 is substantially rectangular or square.

【００２０】また、パッケージ１３の内部底面のシール
ド電極非形成部１８ａ，１８ｂの各辺はパッケージ１３
の各辺に平行で、第１のセラミック枠体１１の内周下端
部に至るように設けてある。すなわちシールド電極非形
成部１８ａ，１８ｂも略長方形あるいは正方形であり、
内部接続電極１４とシールド電極非形成部１８ａ，１８
ｂは略直交して形成されたことになる。Each side of the shield electrode non-forming portions 18a and 18b on the inner bottom surface of the package 13 is
The first ceramic frame 11 is provided so as to reach the lower end of the inner periphery of the first ceramic frame 11 in parallel with each side of the first ceramic frame 11. That is, the shield electrode non-formed portions 18a and 18b are also substantially rectangular or square,
Internal connection electrode 14 and shield electrode non-formed portions 18a, 18
b is formed substantially orthogonally.

【００２１】更にシールド電極非形成部１８ａ，１８ｂ
の第１のセラミック枠体１１の内周下端部の一辺と内部
接続電極１４の一辺が直交するように、パッケージ１３
を上面から見たときに内部接続電極１４のパッケージ１
３の内周側端部とシールド電極非形成部１８ａ，１８ｂ
とを対応させて、かつＳＡＷ素子１７の両側に表出する
シールド電極１５に一つずつシールド電極非形成部１８
ａ，１８ｂを形成している。Further, the shield electrode non-formed portions 18a, 18b
Package 13 so that one side of the inner peripheral lower end of the first ceramic frame 11 and one side of the internal connection electrode 14 are orthogonal to each other.
1 of the internal connection electrode 14 when viewed from above
3 and the non-shield electrode forming portions 18a and 18b
And the shield electrode non-forming portions 18 are provided one by one on the shield electrodes 15 exposed on both sides of the SAW element 17.
a, 18b.

【００２２】一方、圧電基板上に入、出力用の櫛形電
極、この櫛形電極の両側に反射器及び櫛形電極に電気的
に接続された接続電極を複数形成してＳＡＷ素子１７を
得る。On the other hand, a plurality of comb electrodes for input and output on the piezoelectric substrate, and a plurality of reflectors and connection electrodes electrically connected to the comb electrodes on both sides of the comb electrodes are formed to obtain the SAW element 17.

【００２３】次にパッケージ１３の内部底面のシールド
電極１５上にＳＡＷ素子１７を接着層１６を介して固定
する。この時、内部接続電極１４とＳＡＷ素子１７の接
続電極とは略同一面上に存在している。また上面から見
たときに内部接続電極１４とＳＡＷ素子１７の接続電極
の間にシールド電極非形成部１８ａ，１８ｂが存在して
いる。Next, a SAW element 17 is fixed via an adhesive layer 16 on the shield electrode 15 on the inner bottom surface of the package 13. At this time, the internal connection electrode 14 and the connection electrode of the SAW element 17 exist on substantially the same plane. When viewed from above, shield electrode non-formed portions 18a and 18b exist between the internal connection electrode 14 and the connection electrode of the SAW element 17.

【００２４】次いでパッケージ１３を上面から画像認識
し、パッケージ１３の相対向する側壁上端面それぞれに
おいてシールド電極非形成部１８ａ，１８ｂの第１のセ
ラミック枠体１１の内周下端部の一辺と内部接続電極１
４の一辺の直交点を検出し、この二点を結ぶ直線の中点
を基準とし、パッケージ１３の各種寸法とから内部接続
電極１４とワイヤ１９との接続部を決定する。Next, the package 13 is image-recognized from the upper surface, and is internally connected to one side of the inner peripheral lower end of the first ceramic frame 11 of the shield electrode non-formed portions 18a and 18b on the opposing upper end surfaces of the package 13 respectively. Electrode 1
The connection point between the internal connection electrode 14 and the wire 19 is determined from various dimensions of the package 13 with reference to the midpoint of a straight line connecting these two points.

【００２５】また、ＳＡＷ素子１７の表面に設けた櫛形
電極、接続電極などの電極パターンの認識を行い、この
接続電極とワイヤ１９とを接続する位置も決定する。Further, an electrode pattern such as a comb-shaped electrode and a connection electrode provided on the surface of the SAW element 17 is recognized, and the position where the connection electrode is connected to the wire 19 is also determined.

【００２６】その後ワイヤ１９の一端を内部接続電極１
４と、他端をＳＡＷ素子１７の接続電極と電気的に接続
する。Thereafter, one end of the wire 19 is connected to the internal connection electrode 1.
4 and the other end are electrically connected to connection electrodes of the SAW element 17.

【００２７】次いで、リッド２１をパッケージ１３の上
端面に設けたシームリング２０に溶接することにより、
ＳＡＷ素子１７をパッケージ１３内に封止する。Next, the lid 21 is welded to the seam ring 20 provided on the upper end surface of the package 13 to
The SAW element 17 is sealed in the package 13.

【００２８】（実施の形態２）まず、実施の形態１と同
様の内部接続電極１４及びシールド電極１５を有するパ
ッケージ１３及びＳＡＷ素子１７を形成する。(Embodiment 2) First, a package 13 having an internal connection electrode 14 and a shield electrode 15 and a SAW element 17 similar to those of Embodiment 1 are formed.

【００２９】次に、パッケージ１３のシールド電極１５
上に接着層１６を介してＳＡＷ素子１７を実装する。Next, the shield electrode 15 of the package 13
The SAW element 17 is mounted thereon via the adhesive layer 16.

【００３０】次にパッケージ１３を上面から画像認識
し、パッケージ１３の相対向する側壁上端面それぞれに
おいてシールド電極非形成部１８ａ，１８ｂの第１のセ
ラミック枠体１１の内周下端部の一辺と内部接続電極１
４の一辺の直交点を検出し、この二点を結ぶ直線の中点
を基準とし、パッケージ１３の各種寸法とからＳＡＷ素
子１７の実装位置を決定する。Next, the package 13 is image-recognized from the upper surface, and one side and the inner side of the inner peripheral lower end of the first ceramic frame 11 of the shield electrode non-formed portions 18a and 18b are respectively formed on the opposing upper end surfaces of the package 13. Connection electrode 1
Then, the mounting position of the SAW element 17 is determined from various dimensions of the package 13 with reference to the midpoint of a straight line connecting these two points.

【００３１】その後、パッケージ１３のシールド電極１
５上に接着層１６を介してＳＡＷ素子１７を実装する。Thereafter, the shield electrode 1 of the package 13
The SAW element 17 is mounted on the substrate 5 via the adhesive layer 16.

【００３２】次いでＳＡＷ素子１７の接続電極と内部接
続電極１４とをワイヤ１９で接続後、パッケージ１３の
上端面に設けたシームリング２０にリッド２１を溶接し
てＳＡＷ素子１７をパッケージ１３内に封止する。Next, after connecting the connection electrode of the SAW element 17 and the internal connection electrode 14 with the wire 19, the lid 21 is welded to a seam ring 20 provided on the upper end surface of the package 13 to seal the SAW element 17 in the package 13. Stop.

【００３３】（実施の形態３）図３は本発明の実施の形
態３におけるパッケージの上面図であり、図１と同番号
を付している部分については、実施の形態１で説明した
通りであるので説明を省略する。(Embodiment 3) FIG. 3 is a top view of a package according to Embodiment 3 of the present invention, and portions denoted by the same reference numerals as those in FIG. 1 are as described in Embodiment 1. Description is omitted because there is.

【００３４】以下に実施の形態１と異なる点についての
み説明する。Hereinafter, only differences from the first embodiment will be described.

【００３５】実施の形態１ではパッケージ１３を上面か
ら見たときに、シールド電極非形成部１８ａ，１８ｂと
内部接続電極１４の第１のセラミック枠体１１の内周側
端部とを対応させているが、本実施の形態においては、
シールド電極非形成部１８ａ，１８ｂと内部接続電極１
４の第１のセラミック枠体１１の内周側端部とを離して
形成している。In the first embodiment, when the package 13 is viewed from above, the shield electrode non-formed portions 18a and 18b correspond to the inner peripheral end of the first ceramic frame 11 of the internal connection electrode 14. However, in this embodiment,
Shield electrode non-formed portions 18a, 18b and internal connection electrode 1
The first ceramic frame 11 is formed so as to be separated from the inner peripheral end of the first ceramic frame 11.

【００３６】従って、パッケージ１３を上面から画像認
識する際、パッケージ１３の相対向する側壁上端面それ
ぞれにおいてシールド電極非形成部１８ａ，１８ｂの第
１のセラミック枠体１１の内周下端部の一辺の延長線と
内部接続電極１４の一辺の延長線の交点を検出し、この
二点を結ぶ直線の中点を基準とし、パッケージ１３の各
種寸法とから内部接続電極１４とワイヤ１９との接続部
を決定する。Therefore, when recognizing the image of the package 13 from the upper surface, the lower end of the inner peripheral lower end of the first ceramic frame 11 of the shield electrode non-formed portions 18a and 18b is formed on each of the opposing upper end surfaces of the package 13. The intersection of the extension and the extension of one side of the internal connection electrode 14 is detected, and the connection between the internal connection electrode 14 and the wire 19 is determined based on various dimensions of the package 13 with reference to the midpoint of a straight line connecting these two points. decide.

【００３７】（実施の形態４）図３は本発明の実施の形
態４におけるパッケージの上面図であり、図１と同番号
を付している部分については、実施の形態１，２で説明
した通りであるので説明を省略する。(Embodiment 4) FIG. 3 is a top view of a package according to Embodiment 4 of the present invention, and portions denoted by the same reference numerals as those in FIG. 1 have been described in Embodiments 1 and 2. Therefore, the description is omitted.

【００３８】以下に実施の形態１，２と異なる点につい
てのみ説明する。Hereinafter, only points different from the first and second embodiments will be described.

【００３９】実施の形態１，２ではパッケージ１３を上
面から見たときに、シールド電極非形成部１８ａ，１８
ｂと内部接続電極１４の第１のセラミック枠体１１の内
周側端部とを対応させているが、本実施の形態４におい
ても実施の形態３と同様に、シールド電極非形成部１８
ａ，１８ｂと内部接続電極１４の第１のセラミック枠体
１１の内周側端部とを離して形成している。In the first and second embodiments, when the package 13 is viewed from the upper surface, the shield electrode non-formed portions 18a, 18
b corresponds to the inner peripheral end of the first ceramic frame 11 of the internal connection electrode 14, but also in the fourth embodiment, as in the third embodiment, the shield electrode non-forming portion 18.
a, 18b and the inner peripheral end of the first ceramic frame 11 of the internal connection electrode 14 are formed apart from each other.

【００４０】従って、パッケージ１３を上面から画像認
識し、パッケージ１３の相対向する側壁上端面それぞれ
においてシールド電極非形成部１８ａ，１８ｂの第１の
セラミック枠体１１の内周下端部の一辺の延長線と内部
接続電極１４の一辺の延長線の直交点を検出し、この二
点を結ぶ直線の中点を基準とし、パッケージ１３の各種
寸法とからＳＡＷ素子１７の実装位置を決定する。Therefore, the package 13 is image-recognized from the upper surface, and an extension of one side of the inner peripheral lower end of the first ceramic frame 11 of the shield electrode non-formed portions 18a and 18b is provided on each of the opposing upper end surfaces of the package 13. An orthogonal point of the line and an extension of one side of the internal connection electrode 14 is detected, and a mounting position of the SAW element 17 is determined from various dimensions of the package 13 with reference to a middle point of a straight line connecting these two points.

【００４１】（実施の形態５）図４は本発明の実施の形
態５におけるＳＡＷデバイスの断面図であり、図１と同
番号で付している部分については、実施の形態１で説明
した通りであるので説明を省略する。(Embodiment 5) FIG. 4 is a sectional view of a SAW device according to Embodiment 5 of the present invention. Portions denoted by the same reference numerals as those in FIG. 1 are the same as those described in Embodiment 1. Therefore, the description is omitted.

【００４２】以下に実施の形態１と異なる点についての
み説明する。Hereinafter, only points different from the first embodiment will be described.

【００４３】実施の形態１においては第１のセラミック
枠体１１において内周側面と上端面とのなす角は直角で
あるが、本実施の形態５においては第１のセラミック枠
体１１ａにおいて内周側面と上端面とのなす角が鋭角と
なるようにしている。これで、第１のセラミック枠体１
１ａの上面の段差部の開口よりパッケージ１３の内底面
側を広く構成したことになる。In the first embodiment, the angle between the inner peripheral side surface and the upper end surface of the first ceramic frame 11 is a right angle, but in the fifth embodiment, the inner peripheral surface of the first ceramic frame 11a is The angle between the side surface and the upper end surface is set to be an acute angle. Thus, the first ceramic frame 1
This means that the inner bottom surface side of the package 13 is wider than the opening of the step portion on the upper surface 1a.

【００４４】第１のセラミック枠体１１ａは、セラミッ
クシートの所望の形状に打ち抜くことにより形成する。
従って、必ず内周側面はテーパー状となる。仮に内周側
面と上端面とのなす角が鋭角の場合、パッケージ１３を
上面から画像認識したとき、シールド電極非形成部１８
ａ，１８ｂの第１のセラミック枠体１１ａの内周下端部
の一辺あるいはその延長線と内部接続電極１４の一辺あ
るいはその延長線の直交点を精度良く検知することがで
きる。The first ceramic frame 11a is formed by punching a ceramic sheet into a desired shape.
Therefore, the inner peripheral side surface is always tapered. If the angle between the inner peripheral side surface and the upper end surface is an acute angle, when the image of the package 13 is recognized from the upper surface, the shield electrode non-forming portion 18 is formed.
It is possible to accurately detect a point orthogonal to one side or an extension of the inner peripheral lower end of the first ceramic frame 11a of the first and second internal electrodes 14a and 18b.

【００４５】このことは実施の形態２から実施の形態４
のＳＡＷデバイスについても同様のことが言える。This applies to the second to fourth embodiments.
The same can be said for the SAW device.

【００４６】以下に、本発明のポイントについて説明す
る。The points of the present invention will be described below.

【００４７】（１）実施の形態１，３においては、シー
ルド電極非形成部１８ａ，１８ｂの第１のセラミック枠
体１１の内周下端部の一辺あるいはその延長線と内部接
続電極１４の一辺あるいはその延長線の直交点を画像認
識し、ＳＡＷ素子１７の接続電極と内部接続電極１４と
をワイヤ１９で確実に接続する場合について説明した。(1) In the first and third embodiments, one side of the inner peripheral lower end of the first ceramic frame 11 of the shield electrode non-formed portions 18a, 18b or an extension thereof and one side of the internal connection electrode 14 or The case where the orthogonal points of the extension lines are image-recognized and the connection electrodes of the SAW element 17 and the internal connection electrodes 14 are securely connected with the wires 19 has been described.

【００４８】また、実施の形態２，４においては、ＳＡ
Ｗ素子１７をパッケージ１３内に実装する前に、シール
ド電極非形成部１８ａ，１８ｂの第１のセラミック枠体
１１の内周下端部の一辺あるいはその延長線と内部接続
電極１４の一辺あるいはその延長線の直交点を画像認識
し、ＳＡＷ素子１７の実装位置を決定する場合について
説明した。In Embodiments 2 and 4, the SA
Before mounting the W element 17 in the package 13, one side of the lower end of the inner peripheral portion of the first ceramic frame 11 of the shield electrode non-formed portions 18 a and 18 b or an extension thereof and one side of the internal connection electrode 14 or an extension thereof. The case where the orthogonal points of the line are image-recognized to determine the mounting position of the SAW element 17 has been described.

【００４９】このようにシールド電極非形成部１８ａ，
１８ｂを内部接続電極１４と略直交するように形成する
ことにより、ＳＡＷ素子１７の実装位置や内部接続電極
１４とワイヤ１９の接続位置を特定することができる。
もちろん一つのＳＡＷデバイスを製造する際に、ＳＡＷ
素子１７の実装位置と内部接続電極１４とワイヤ１９と
の接続位置を特定するために二度画像認識を行っても構
わない。As described above, the shield electrode non-formed portions 18a,
By forming 18 b so as to be substantially orthogonal to the internal connection electrode 14, the mounting position of the SAW element 17 and the connection position of the internal connection electrode 14 and the wire 19 can be specified.
Of course, when manufacturing one SAW device, the SAW
Image recognition may be performed twice in order to specify the mounting position of the element 17 and the connection position between the internal connection electrode 14 and the wire 19.

【００５０】（２）実施の形態１，３のように、内部接
続電極１４とワイヤ１９の接続位置を特定するために画
像認識を行う場合、シールド電極非形成部１８ａ，１８
ｂの幅は画像認識を行うレンズのピントずれの幅よりも
広くすることにより、誤認識を防止することができる。(2) As in Embodiments 1 and 3, when image recognition is performed to specify the connection position between the internal connection electrode 14 and the wire 19, the shield electrode non-formed portions 18a, 18
By making the width of b larger than the width of defocus of the lens for performing image recognition, erroneous recognition can be prevented.

【００５１】（３）ＳＡＷ素子１７の上面と内部接続電
極１４とを略同一面上に存在するようにすることによ
り、画像認識の際、焦点がＳＡＷ素子１７の内部接続電
極１４の両方に合うこととなり、シールド電極非形成部
１８ａ，１８ｂの第１のセラミック枠体１１ａの内周下
端部の一辺あるいはその延長線と内部接続電極１４の一
辺あるいはその延長線の直交点と、ＳＡＷ素子１７の接
続電極や櫛形電極などの電極パターンの認識を同じに行
うことができる。(3) By making the upper surface of the SAW element 17 and the internal connection electrode 14 exist on substantially the same plane, the focus is adjusted to both the internal connection electrode 14 of the SAW element 17 during image recognition. That is, a point orthogonal to one side or an extension of the lower end of the inner peripheral portion of the first ceramic frame 11a of the shield electrode non-formed portions 18a and 18b and one side or the extension of the internal connection electrode 14 and the SAW element 17 Recognition of electrode patterns such as connection electrodes and comb electrodes can be performed in the same manner.

【００５２】（４）実施の形態１，２においては、シー
ルド電極非形成部１８ａ，１８ｂの内部接続電極１４の
側端部に接する一辺と、内部接続電極１４のパッケージ
１３の内周側端部に接する一辺の交点を検出するので、
パッケージ１３の内周端部と内部底面端部との境界を確
実に認識できる。一方、実施の形態３，４においてはシ
ールド電極非形成部１８ａ，１８ｂの第１のセラミック
枠体１１ａの内周下端部の一辺と内部接続電極１４の一
辺の直交点を検出するため、例えばパッケージ１３の形
状精度にばらつきがある場合は、実施の形態１，２と比
較するとその位置認識精度は劣ることとなる。(4) In the first and second embodiments, one side of the shield electrode non-formed portions 18a and 18b in contact with the side end of the internal connection electrode 14, and the end of the internal connection electrode 14 on the inner peripheral side of the package 13. Since the intersection of one side that touches is detected,
The boundary between the inner peripheral edge and the inner bottom edge of the package 13 can be reliably recognized. On the other hand, in the third and fourth embodiments, for example, a package is used to detect an orthogonal point between one side of the inner peripheral lower end of the first ceramic frame 11a of the shield electrode non-formed portions 18a and 18b and one side of the internal connection electrode 14. In the case where there is a variation in the shape accuracy of the thirteenth embodiment, the position recognition accuracy is inferior to the first and second embodiments.

【００５３】従って、実施の形態１，２のようにパッケ
ージ１３を上面から見たときに、シールド電極非形成部
１８ａ，１８ｂと内部接続電極１４の第１のセラミック
枠体１１の内周側端部とが対応するように、シールド電
極非形成部１８ａ，１８ｂを形成することが望ましい。
またシールド電極非形成部１８ａ，１８ｂを形成する際
多少の位置ずれが生じても影響のないように、同一面上
の内部接続電極１４間の距離よりも、シールド電極非形
成部１８ａ，１８ｂの内部接続電極１４の側端部の辺の
距離を長くしておくことが望ましい。Therefore, when the package 13 is viewed from above as in the first and second embodiments, the inner peripheral end of the first ceramic frame 11 of the shield electrode non-formed portions 18a and 18b and the internal connection electrode 14 is formed. It is desirable to form the shield electrode non-formed portions 18a and 18b so as to correspond to the portions.
Also, the distance between the internal connection electrodes 14 on the same plane is smaller than the distance between the internal connection electrodes 14 so that even if a slight displacement occurs when forming the shield electrode non-formed portions 18a, 18b, It is desirable to increase the distance of the side of the side end of the internal connection electrode 14.

【００５４】（５）上記各実施の形態においては、シー
ルド電極非形成部１８ａ，１８ｂをパッケージ１３の段
差２２に設けた内部接続電極１４側の両端部に設けてい
る。一方の内部接続電極１４側にシールド電極非形成部
１８ａ，１８ｂを二つ設けて、シールド電極非形成部１
８ａ，１８ｂの第１のセラミック枠体１１ａの内周下端
部の一辺あるいはその延長線と内部接続電極１４の一辺
あるいはその延長線の直交点を認識し、位置決めを行う
ことができるが、より精度良く認識するためには、シー
ルド電極非形成部１８ａ，１８ｂをパッケージ１３の底
部のＳＡＷ素子１７の両側に表出するシールド電極１５
には、両者の距離ができるだけ長くなるように形成する
ことが望ましい。(5) In each of the above embodiments, the shield electrode non-formed portions 18a and 18b are provided at both ends on the side of the internal connection electrode 14 provided on the step 22 of the package 13. Two shield electrode non-forming portions 18a and 18b are provided on one internal connection electrode 14 side, and the shield electrode non-forming portion 1 is formed.
Positioning can be performed by recognizing an orthogonal point between one side or an extension of the inner peripheral lower end of the first ceramic frame 11a of 8a and 18b and one side of the internal connection electrode 14 or an extension thereof. In order to recognize well, the shield electrode non-forming portions 18 a and 18 b are exposed on both sides of the SAW element 17 at the bottom of the package 13.
It is preferable that the distance between the two is made as long as possible.

【００５５】（６）シールド電極１５と内部接続電極１
４と同じ材料を用いて形成していたため、従来パッケー
ジ１３を上面から見た場合、パッケージ１３の内周端部
と内部底面端部との境界認識が非常に困難であった。従
ってＳＡＷ素子１７の実装精度を悪化させないように、
パッケージ１３の内部を必要以上に大きくしてＳＡＷ１
７を実装していた。しかしながら本発明においては、パ
ッケージ１３の内周端部と底面端部との境界認識がで
き、ＳＡＷ素子１７の実装位置を決定できるので、パッ
ケージ１３の内部の大きさをＳＡＷ素子１７を実装でき
る必要最小限にすることができる。従って、ＳＡＷデバ
イスの小型化を行うことができる。(6) Shield electrode 15 and internal connection electrode 1
4, the conventional package 13 was very difficult to recognize the boundary between the inner peripheral edge and the inner bottom edge when the package 13 was viewed from above. Therefore, in order not to deteriorate the mounting accuracy of the SAW element 17,
SAW1 by making the inside of package 13 larger than necessary
7 was implemented. However, in the present invention, the boundary between the inner peripheral end and the bottom end of the package 13 can be recognized, and the mounting position of the SAW element 17 can be determined. Can be minimized. Therefore, the size of the SAW device can be reduced.

【００５６】（７）シールド電極１５はできるだけ大き
い方がそのシールド効果も大きい。シールド電極非形成
部１８ａ，１８ｂは三つ以上形成しても構わないが、二
つ形成すればＳＡＷ素子１７の実装位置を決定できるの
で、シールド電極非形成部１８ａ，１８ｂの数は二つ、
その大きさは必要最小限とすることが望ましい。(7) The larger the shield electrode 15 is, the greater the shielding effect is. Although three or more shield electrode non-formed portions 18a and 18b may be formed, if two are formed, the mounting position of the SAW element 17 can be determined. Therefore, the number of shield electrode non-formed portions 18a and 18b is two.
It is desirable that the size be the minimum necessary.

【００５７】（８）上記実施の形態においてはＳＡＷデ
バイスを例に説明したが、パッケージの上端面と底面に
電極を設けて、内部に素子を実装する電子部品において
は同様の効果が得られるものである。(8) In the above embodiment, a SAW device has been described as an example. However, similar effects can be obtained in an electronic component in which electrodes are provided on the upper and lower surfaces of a package and elements are mounted inside. It is.

【００５８】[0058]

【発明の効果】以上本発明によると、内部接続電極のワ
イヤとの接続位置を精度良く決定できるので素子と内部
接続電極とを確実に接続することができる。As described above, according to the present invention, the connection position of the internal connection electrode with the wire can be determined with high accuracy, so that the element and the internal connection electrode can be reliably connected.

【００５９】また、素子のパッケージへの実装精度も向
上させることができるのでパッケージの内部の大きさを
必要最小限にすることができ、電子部品の小型化を図る
ことができる。Also, since the mounting accuracy of the element in the package can be improved, the internal size of the package can be minimized, and the size of the electronic component can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施の形態１，２におけるリッドで封
止前のＳＡＷデバイスの上面図FIG. 1 is a top view of a SAW device before sealing with a lid according to Embodiments 1 and 2 of the present invention.

【図２】図１に示すＳＡＷデバイスのＡ−Ｂ断面図FIG. 2 is a cross-sectional view of the SAW device shown in FIG.

【図３】本発明の実施の形態３，４におけるリッドで封
止前のＳＡＷデバイスの上面図FIG. 3 is a top view of a SAW device before sealing with a lid according to Embodiments 3 and 4 of the present invention.

【図４】本発明の実施の形態５におけるＳＡＷデバイス
の断面図FIG. 4 is a sectional view of a SAW device according to a fifth embodiment of the present invention.

【図５】従来のＳＡＷデバイスのリッドで封止前の上面
図FIG. 5 is a top view before sealing with a lid of a conventional SAW device.

【図６】図５に示すＳＡＷデバイスの断面図FIG. 6 is a cross-sectional view of the SAW device shown in FIG.

【符号の説明】[Explanation of symbols]

１０ セラミック基板 １１ 第１のセラミック枠体 １１ａ 第１のセラミック枠体 １２ 第２のセラミック枠体 １３ パッケージ １４ 内部接続電極 １５ シールド電極 １６ 接着層 １７ ＳＡＷ素子 １８ａ シールド電極非形成部 １８ｂ シールド電極非形成部 １９ ワイヤ ２０ シームリング ２１ リッド ２２ 段差 DESCRIPTION OF SYMBOLS 10 Ceramic substrate 11 1st ceramic frame 11a 1st ceramic frame 12 2nd ceramic frame 13 Package 14 Internal connection electrode 15 Shield electrode 16 Adhesive layer 17 SAW element 18a Shield electrode non-forming part 18b Shield electrode non-forming Part 19 Wire 20 Seam ring 21 Lid 22 Step

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 相対向する壁側に段差を有し、この段差
の上端面に複数の内部接続電極を有し、内部底面にシー
ルド電極と、上面から見た時前記内部接続電極の一辺あ
るいはその延長線とその一辺が直交するようなシールド
電極非形成部を有するパッケージに素子を実装する第１
の工程と、次に前記内部接続電極の一辺あるいはその延
長線と前記シールド電極非形成部の一辺の交点を少なく
とも二点検出し、前記素子と前記内部接続電極とを接続
するワイヤの接続位置を決定する第２の工程と、次いで
前記素子と前記内部接続電極とをワイヤで接続する第３
の工程と、その後前記パッケージをリッドで封止する第
４の工程とを備えた電子部品の製造方法。A step having a plurality of internal connection electrodes on an upper end face of the step, a shield electrode on an internal bottom face, and one side of the internal connection electrode when viewed from above. A first method of mounting an element in a package having a shield electrode non-formed portion in which an extension line thereof and one side thereof are orthogonal to each other.
And inspecting at least two intersections between one side or an extension of the internal connection electrode and one side of the shield electrode non-formed portion, and determine a connection position of a wire connecting the element and the internal connection electrode. And a third step of connecting the element and the internal connection electrode with a wire.
And a fourth step of sealing the package with a lid thereafter. 【請求項２】 相対向する壁側に段差を有し、この段差
の上端面に複数の内部接続電極を有し、内部底面にシー
ルド電極と、上面から見た時前記内部接続電極の一辺あ
るいはその延長線とその一辺が直交するようなシールド
電極非形成部を有するパッケージに素子を実装する第１
の工程と、次いで前記素子と前記内部接続電極とをワイ
ヤで接続する第２の工程と、その後前記パッケージをリ
ッドで封止する第３の工程とを備え、前記第１の工程に
おいて、前記内部接続電極の一辺あるいはその延長線と
前記シールド電極非形成部の一辺の交点を少なくとも二
点検出し、前記素子の実装位置を決定する電子部品の製
造方法。2. An opposite wall having a step, a plurality of internal connection electrodes on an upper end face of the step, a shield electrode on an inner bottom face, and one side of the internal connection electrode when viewed from above. A first method of mounting an element in a package having a shield electrode non-formed portion in which an extension line thereof and one side thereof are orthogonal to each other.
And a second step of connecting the element and the internal connection electrode with a wire, and a third step of sealing the package with a lid, and then, in the first step, A method for manufacturing an electronic component, wherein at least two intersections between one side of a connection electrode or an extension thereof and one side of the shield electrode non-formed portion are checked to determine a mounting position of the element. 【請求項３】 相対向する壁側に段差を有し、この段差
の上端面に複数の内部接続電極を有し、内部底面にシー
ルド電極と、上面から見た時前記内部接続電極の一辺あ
るいはその延長線とその一辺が直交するようなシールド
電極非形成部を有するパッケージに素子を実装する第１
の工程と、次に前記素子と前記内部接続電極とをワイヤ
で接続する第２の工程と、その後前記パッケージをリッ
ドで封止する第３の工程とを備え、前記第１及び第２の
工程において、前記内部接続電極の一辺あるいはその延
長線と前記シールド電極非形成部の一辺の交点を少なく
とも二点検出し、前記素子の実装位置及び前記ワイヤの
接続位置を決定する電子部品の製造方法。3. A step is formed on a wall opposite to the step, a plurality of internal connection electrodes are provided on an upper end surface of the step, a shield electrode is provided on an inner bottom surface, and one side of the internal connection electrode when viewed from above. A first method of mounting an element in a package having a shield electrode non-formed portion in which an extension line thereof and one side thereof are orthogonal to each other.
A second step of connecting the element and the internal connection electrode with a wire, and a third step of sealing the package with a lid, and the first and second steps A method of manufacturing an electronic component, wherein at least two intersections between one side or an extension of the internal connection electrode and one side of the shield electrode non-formed portion are checked to determine a mounting position of the element and a connection position of the wire.
JP2000397702A 2000-12-27 2000-12-27 Electronic component manufacturing method Expired - Fee Related JP3438721B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000397702A JP3438721B2 (en) 2000-12-27 2000-12-27 Electronic component manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000397702A JP3438721B2 (en) 2000-12-27 2000-12-27 Electronic component manufacturing method

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP27420599A Division JP3216638B2 (en) 1999-09-28 1999-09-28 Electronic component and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JP2001185573A true JP2001185573A (en) 2001-07-06
JP3438721B2 JP3438721B2 (en) 2003-08-18

Family

ID=18862799

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000397702A Expired - Fee Related JP3438721B2 (en) 2000-12-27 2000-12-27 Electronic component manufacturing method

Country Status (1)

Country Link
JP (1) JP3438721B2 (en)

Also Published As

Publication number Publication date
JP3438721B2 (en) 2003-08-18

Similar Documents

Publication Publication Date Title
US6303470B1 (en) Semiconductor wafer and method for manufacturing semiconductor devices
JP2002222906A (en) Semiconductor device and manufacturing method therefor
JP3216638B2 (en) Electronic component and method of manufacturing the same
JP3301419B2 (en) Electronic component manufacturing method
JP2001185573A (en) Method for manufacturing electronic component
KR100397003B1 (en) Electronic device and method of manufacture thereof
JP2001230656A (en) Electronic component
JP2007113969A (en) Capacitive pressure sensor
JPH0713232Y2 (en) Sardip type semiconductor device
JPS61255039A (en) Semiconductor device
JP5371817B2 (en) Manufacturing method of glass sealed package
JP2973982B2 (en) Image inspection method of molded terminal of electronic component and chip type electronic component
JP3646980B2 (en) Capacitance type sensor and manufacturing method thereof
JP2006317182A (en) Acceleration sensor
JP3613194B2 (en) Electronic component and manufacturing method thereof
JP2006237127A (en) Capacitance element
JPH04129259A (en) Electronic parts
JP3756734B2 (en) Capacitive pressure sensor
JP3429437B2 (en) Package for solid-state imaging device and solid-state imaging device using the same
JPH09178578A (en) Capacitive sensor
JP2006184014A (en) Acceleration sensor
JP2006186704A (en) Method for manufacturing surface acoustic wave device
JP2005069813A (en) Measuring holder for electronic component
JP2002368177A (en) Lead frame and semiconductor device
JPH04246852A (en) Package for semiconductor device

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees