JP2001177219A - Manufacturing method of circuit board - Google Patents

Manufacturing method of circuit board

Info

Publication number
JP2001177219A
JP2001177219A JP2000338086A JP2000338086A JP2001177219A JP 2001177219 A JP2001177219 A JP 2001177219A JP 2000338086 A JP2000338086 A JP 2000338086A JP 2000338086 A JP2000338086 A JP 2000338086A JP 2001177219 A JP2001177219 A JP 2001177219A
Authority
JP
Japan
Prior art keywords
plating
laser
circuit
circuit portion
circuit part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000338086A
Other languages
Japanese (ja)
Inventor
Riyuuji Ootani
隆児 大谷
Takeshi Okamoto
剛 岡本
Yoshimitsu Nakamura
良光 中村
Yoshiyuki Uchinono
良幸 内野々
Sakuo Kamata
策雄 鎌田
Kunji Nakajima
勲二 中嶋
Toshiyuki Suzuki
俊之 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP2000338086A priority Critical patent/JP2001177219A/en
Publication of JP2001177219A publication Critical patent/JP2001177219A/en
Pending legal-status Critical Current

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  • Chemically Coating (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PROBLEM TO BE SOLVED: To enhance productivity by reducing the irradiation treatment time of electromagnetic waves, such as laser. SOLUTION: A catalyst for plating and its compound are deposited onto the surface of an insulating base material 1 for forming a plated foundation layer 2. Electromagnetic waves, such as those of laser, are applied to the boundary region between a circuit part 3 of the insulating base material and a non- circuit part 4 corresponding to the pattern of the non-circuit part 4, thus dispensing with the plated foundation layer 2 of an irradiation part where the electromagnetic waves such as laser are applied, while the non-irradiation part remains. After that, plating is made to the plated foundation layer 2. The irradiation of the laser or the like is made to the boundary region of the circuit part 3 in the non-circuit part 4, and there is not need to apply laser to the entire surface of the wide region of the non-circuit part 4.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、平面又は三次元立体の
絶縁性基材の表面に回路を形成することによって得られ
る回路板の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a circuit board obtained by forming a circuit on the surface of a planar or three-dimensional insulating substrate.

【0002】[0002]

【従来の技術】絶縁性基材の表面に回路を形成すること
によって回路板を製造するにあたって、回路間の絶縁部
となる非回路部の箇所にレーザ等を照射することによっ
てこの箇所にめっきがおこなわれないように処理し、そ
してこの後に回路形成用のめっきを施すようにした技術
が、特開平4−263490号公報や特開昭61−68
92号公報、特開平3−122287号公報で提供され
ている。
2. Description of the Related Art In manufacturing a circuit board by forming a circuit on the surface of an insulating base material, a portion of a non-circuit portion serving as an insulating portion between the circuits is irradiated with a laser or the like so that plating is applied to this portion. Japanese Patent Application Laid-Open No. 4-263490 and Japanese Patent Application Laid-Open No. Sho 61-68 disclose a technique in which processing is performed so as not to be performed, and thereafter plating for forming a circuit is performed.
92, and Japanese Patent Application Laid-Open No. 3-122287.

【0003】すなわち特開平4−263490号公報は
「薄膜回路の製造方法」に関するものであり、絶縁材の
基板の上に導体薄膜を形成し、パターン形成したホトマ
スクを通して導体薄膜にレーザ光を照射して導体薄膜を
除去し、導体薄膜のパターンに無電解めっきあるいは電
気めっきして導体を堆積させることによってめっき導体
パターンを形成するようにしてある。
[0003] That is, JP-A-4-263490 relates to a "method of manufacturing a thin film circuit", in which a conductive thin film is formed on an insulating substrate, and the conductive thin film is irradiated with a laser beam through a patterned photomask. The conductive thin film is removed by electroless plating or electroplating on the conductive thin film pattern to deposit a conductor, thereby forming a plated conductive pattern.

【0004】また特開昭61−6892号公報は「プリ
ント回路の製造方法」に関するものであり、化学めっき
反応用触媒を表面に設けた基板にパターン状にレーザ光
等の高強度光を照射して触媒作用を低下乃至消失させた
後、化学めっき処理して高強度光の非照射部に選択的に
めっきすることによってプリント回路を形成するように
してある。
Japanese Patent Application Laid-Open No. 61-6892 relates to "a method for manufacturing a printed circuit", in which a substrate provided with a catalyst for a chemical plating reaction on its surface is irradiated with high-intensity light such as laser light in a pattern. After the catalytic action is reduced or eliminated, a printed circuit is formed by selectively plating a non-irradiated portion with high intensity light by chemical plating.

【0005】さらに特開平3−122287号公報は
「基板の金属化方法」に関するものであり、基板の上に
触媒層を被着し、区域的に紫外線照射して触媒層を活性
化又は不動態化した後に、活性化区域にめっき等をする
ようにしてある。
Further, Japanese Patent Application Laid-Open No. 3-122287 relates to a "method of metallizing a substrate", in which a catalyst layer is deposited on a substrate, and the catalyst layer is activated or passivated by irradiating ultraviolet rays locally. After the activation, the activation area is plated or the like.

【0006】[0006]

【発明が解決しようとする課題】上記のように特開平4
−263490号公報や特開昭61−6892号公報、
特開平3−122287号公報のものでは、絶縁性基材
の非回路部にレーザや紫外線等を照射する工程を設けて
回路板を製造するようにしているが、いずれのものにあ
っても、非回路部の領域全面にめっきがなされないよう
にレーザや紫外線等を非回路部の領域の全面に照射する
ようにしている。しかしこのように非回路部の広い領域
の全面にレーザや紫外線等を照射すると、レーザや紫外
線等の照射処理時間が長く必要になって回路板の生産性
が低下するという問題があった。
As described above, Japanese Patent Laid-Open No.
-263490 and JP-A-61-6892,
In Japanese Unexamined Patent Publication No. 3-122287, a circuit board is manufactured by providing a step of irradiating a non-circuit portion of an insulating base material with a laser, ultraviolet light, or the like. A laser, ultraviolet light, or the like is applied to the entire surface of the non-circuit portion so that plating is not performed on the entire surface of the non-circuit portion. However, when the entire surface of the wide area of the non-circuit portion is irradiated with the laser, the ultraviolet light, or the like, there is a problem that the irradiation time of the laser, the ultraviolet light, or the like is long and the productivity of the circuit board is reduced.

【0007】本発明は上記の点に鑑みてなされたもので
あり、レーザ等の電磁波の照射処理時間を短縮して生産
性を高めることができる回路板の製造方法を提供するこ
とを目的とするものである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to provide a method of manufacturing a circuit board capable of shortening the irradiation time of an electromagnetic wave such as a laser and improving productivity. Things.

【0008】[0008]

【課題を解決するための手段】本発明に係る回路板の製
造方法は、絶縁性基材1の表面にめっき用触媒、めっき
用触媒の化合物を付着させてめっき下地層2を形成し、
絶縁性基材1の回路部3と非回路部4の境界領域に、非
回路部4のパターンに対応してレーザ等の電磁波を照射
することによって、非照射部を残してレーザ等の電磁波
を照射した照射部のめっき下地層2を除去した後、めっ
き下地層2にめっきを施すことを特徴とするものであ
る。
According to the method of manufacturing a circuit board of the present invention, a plating catalyst and a compound of a plating catalyst are adhered to the surface of an insulating base material 1 to form a plating base layer 2;
By irradiating the boundary region between the circuit portion 3 and the non-circuit portion 4 of the insulating base material 1 with an electromagnetic wave such as a laser corresponding to the pattern of the non-circuit portion 4, the electromagnetic wave such as a laser is emitted while leaving the non-irradiated portion. It is characterized in that plating is performed on the plating underlayer 2 after removing the plating underlayer 2 in the irradiated portion.

【0009】[0009]

【作用】絶縁性基材1の非回路部4の回路部3との境界
領域に沿ってレーザ等の電磁波を照射することによっ
て、非回路部4の領域の全面に電磁波を照射するような
必要なく、回路部3にめっきで回路5を形成することが
できる。そして非回路部4にもめっきがなされても、回
路部3とはレーザ等の電磁波の照射で分離絶縁されてお
り、回路板の回路性能に特に問題は生じない。
It is necessary to irradiate an electromagnetic wave such as a laser along the boundary region between the non-circuit portion 4 and the circuit portion 3 of the insulating base material 1 to irradiate the entire surface of the non-circuit portion 4 with the electromagnetic wave. Instead, the circuit 5 can be formed on the circuit portion 3 by plating. Even if the non-circuit portion 4 is plated, the circuit portion 3 is separated and insulated from the circuit portion 3 by irradiation of an electromagnetic wave such as a laser, so that there is no particular problem in the circuit performance of the circuit board.

【0010】[0010]

【実施例】以下本発明を実施例によって詳述する。The present invention will be described below in detail with reference to examples.

【0011】図1は本発明の一実施例を示すものであ
り、絶縁性基材1としてはポリイミド、ABS、ポリエ
ーテルイミド、液晶ポリマー、アルミナセラミックス等
の電気絶縁材料によって形成したものを用いるものであ
り、図1(a)のように平面状に形成したものの他に、
三次元立体状に作成したものを用いることができる。そ
して先ず、この絶縁性基材1の表面をクロム酸液やKO
H水溶液、リン酸液等で処理することによって、図1
(b)のように微細な凹凸11を付与する粗面化処理を
おこなう。
FIG. 1 shows an embodiment of the present invention. As an insulating substrate 1, a substrate made of an electrically insulating material such as polyimide, ABS, polyetherimide, liquid crystal polymer, and alumina ceramics is used. In addition to the one formed in a planar shape as shown in FIG.
A three-dimensionally formed one can be used. First, the surface of the insulating substrate 1 is coated with a chromic acid solution or KO.
By treating with H aqueous solution, phosphoric acid solution, etc.
As shown in (b), a roughening treatment for providing fine irregularities 11 is performed.

【0012】次に、絶縁性基材1の表面の全面に図1
(c)のようにめっき下地層2を形成する。めっき下地
層2はめっき用触媒やめっき用触媒の化合物を絶縁性基
材1の表面に付着させることによって形成することがで
きるが、図1の実施例では、無電解めっきの触媒となる
Pdを含有する液に絶縁性基材1を浸漬した後に、活性
化処理して、絶縁性基材1の表面にPd核付けをおこな
うことによって、めっき下地層2を形成するようにして
ある。
Next, FIG. 1 shows the entire surface of the insulating substrate 1.
The plating underlayer 2 is formed as shown in FIG. The plating base layer 2 can be formed by attaching a plating catalyst or a compound of the plating catalyst to the surface of the insulating substrate 1. In the embodiment of FIG. 1, Pd which is a catalyst for electroless plating is used. After the insulating substrate 1 is immersed in the contained solution, an activation treatment is performed, and Pd nucleation is performed on the surface of the insulating substrate 1 to form the plating base layer 2.

【0013】次に、絶縁性基材1の表面にレーザ等の電
磁波を照射して電磁波を照射した部分のめっき下地層2
を除去する。電磁波としてはレーザの他に、X線や紫外
線等を用いることができるが、レーザが最も好適である
ので、以下主として電磁波としてレーザを用いたものに
ついて説明する。このレーザとしては例えばQスイッチ
YAGレーザを用いることができるものであり、ガルバ
ノミラー等で操作することによってレーザを絶縁性基材
1の表面に移動させつつ照射するようにしてある。ガル
バノミラーはガルバノメータを用いて角度可変に形成し
たミラーであり、高速でビーム移動が可能であると共に
レーザスポット径も数十μmを得ることが可能である。
またレーザの照射は、絶縁性基材1の表面のうち回路5
を形成する箇所である回路部3以外の部分、すなわち回
路部3間の絶縁スペースとなる非回路部4においておこ
なわれるものであり、非回路部4の回路部3との境界領
域に非回路部4のパターン沿ってレーザを移動(走査)
させながら照射することによって、非回路部4の回路部
3との境界領域のめっき下地層2を除去するものであ
る。従って図1(d)に示すように、非回路部4のめっ
き下地層2のうち、レーザの照射部である回路部3との
境界部分のめっき下地層2は除去され、非回路部4のめ
っき下地層2のうちレーザの非照射部は、回路部3のめ
っき下地層2と共に除去されずに残されることになる。
レーザの照射エネルギーは例えば10〜300μJ/p
ulse程度が好ましく、めっき下地層2と共に絶縁性
基材1の表面部を同時に除去するようにしてもよい。こ
こで、非回路部4の幅(隣合う回路部3間の幅)が照射
レーザのスポット径(例えばφ100μm)と同等の場
合には、非回路部4に沿ってレーザを1回照射すること
によって、非回路部4の両側の境界領域のめっき下地層
2を除去することができる。
Next, the surface of the insulating substrate 1 is irradiated with an electromagnetic wave such as a laser, and a portion of the plating underlayer 2 where the electromagnetic wave is irradiated is irradiated.
Is removed. As the electromagnetic waves, X-rays, ultraviolet rays, and the like can be used in addition to lasers. Since lasers are most suitable, those using lasers as electromagnetic waves will be mainly described below. As this laser, for example, a Q-switched YAG laser can be used, and the laser is irradiated while moving to the surface of the insulating substrate 1 by operating with a galvanomirror or the like. The galvanometer mirror is a mirror formed to be variable in angle using a galvanometer, and can move a beam at a high speed and obtain a laser spot diameter of several tens of μm.
Laser irradiation is performed on the surface of the insulating substrate 1 by the circuit 5.
Is performed in a portion other than the circuit portion 3 where the circuit portion 3 is formed, that is, in the non-circuit portion 4 serving as an insulating space between the circuit portions 3. Move (scan) laser along pattern 4
By irradiating the substrate, the plating underlayer 2 in the boundary region between the non-circuit portion 4 and the circuit portion 3 is removed. Therefore, as shown in FIG. 1D, the plating underlayer 2 at the boundary with the circuit portion 3, which is the portion irradiated with the laser, is removed from the plating underlayer 2 of the non-circuit portion 4. The non-irradiated portion of the laser in the plating underlayer 2 is left without being removed together with the plating underlayer 2 of the circuit portion 3.
The irradiation energy of the laser is, for example, 10 to 300 μJ / p.
ulse is preferable, and the surface portion of the insulating base material 1 may be removed simultaneously with the plating base layer 2. Here, when the width of the non-circuit portion 4 (the width between the adjacent circuit portions 3) is equal to the spot diameter of the irradiation laser (for example, φ100 μm), the laser is irradiated once along the non-circuit portion 4. Thereby, the plating underlayer 2 in the boundary regions on both sides of the non-circuit portion 4 can be removed.

【0014】上記のようにしてレーザを絶縁性基材1の
表面の非回路部4に回路部3との境界領域に照射した
後、無電解銅めっき液等の無電解めっき浴に絶縁性基材
1を浸漬等することによって、レーザが照射されず絶縁
性基材1の表面に残っているめっき下地層2に銅等の無
電解めっき層12を10μm程度の厚みで析出させる。
このように無電解めっき層12を回路部3のめっき下地
層2の上に設けることによって、パターン形状の回路5
を形成することができるものである。無電解めっき層1
2は非回路部4に残留するめっき下地層2にも設けられ
ることになるが、回路部3のめっき下地層2と非回路部
4のめっき下地層2との境界部分はレーザ照射によって
除去されているために、回路5の絶縁性は確保されてお
り、性能上特に問題は生じない。
After irradiating the non-circuit portion 4 on the surface of the insulating substrate 1 with the laser to the boundary region with the circuit portion 3 as described above, the laser is applied to an electroless plating bath such as an electroless copper plating solution. By immersing the material 1 or the like, an electroless plating layer 12 of copper or the like is deposited to a thickness of about 10 μm on the plating base layer 2 remaining on the surface of the insulating substrate 1 without being irradiated with the laser.
By providing the electroless plating layer 12 on the plating base layer 2 of the circuit section 3 in this manner, the circuit
Can be formed. Electroless plating layer 1
2 is also provided on the plating underlayer 2 remaining in the non-circuit portion 4, but the boundary portion between the plating underlayer 2 of the circuit portion 3 and the plating underlayer 2 of the non-circuit portion 4 is removed by laser irradiation. Therefore, the insulation of the circuit 5 is ensured, and there is no particular problem in performance.

【0015】このように回路部3のめっき下地層2にめ
っきをして回路形成した後、必要に応じてソルダーレジ
スト、Niめっき、Auめっきを施すことによって、回
路板として仕上げることができる。上記のようにして回
路板を製造するにあたって、レーザの照射は絶縁性基材
1の非回路部4の回路部3との境界領域におこなってい
るだけであり、非回路部4の全面にレーザを走査させて
照射する必要はないので、非回路部4の広い領域の全面
にレーザを描画して照射する場合に比べてレーザの照射
処理時間を短縮することができ、回路板の生産性を高め
ることが可能になるものである。尚、上記実施例ではレ
ーザ照射後にめっきをおこなって回路形成するにあたっ
て、無電解めっきをおこなうようにしたが、無電解めっ
きの他に、電気めっきやCVD(化学蒸着)、PVD
(物理蒸着)等の任意のめっき手段を用いて回路形成を
することができるものである。
After the circuit is formed by plating the plating base layer 2 of the circuit portion 3 as described above, a solder resist, Ni plating, and Au plating are applied as necessary, thereby completing the circuit board. In manufacturing the circuit board as described above, the laser irradiation is performed only on the boundary region between the non-circuit portion 4 and the circuit portion 3 of the insulating base material 1, and the laser is applied to the entire surface of the non-circuit portion 4. It is not necessary to scan and irradiate, so that the laser irradiation processing time can be shortened as compared with the case where the laser is drawn and illuminated over the entire wide area of the non-circuit portion 4, and the productivity of the circuit board can be reduced. It is possible to increase. In the above embodiment, electroless plating is performed when forming a circuit by plating after laser irradiation. However, in addition to electroless plating, electroplating, CVD (chemical vapor deposition), PVD
The circuit can be formed using any plating means such as (physical vapor deposition).

【0016】[0016]

【発明の効果】上記のように本発明は、絶縁性基材の表
面にめっき用触媒、めっき用触媒の化合物を付着させて
めっき下地層を形成し、絶縁性基材の回路部と非回路部
の境界領域に、非回路部のパターンに対応してレーザ等
の電磁波を照射することによって、非照射部を残してレ
ーザ等の電磁波を照射したこの照射部のめっき下地層を
除去した後、めっき下地層にめっきを施すようにしたの
で、レーザの照射は非回路部のうち回路部との境界領域
におこなえば足りるものであり、非回路部の広い領域の
全面にレーザを照射する場合に比べてレーザの照射処理
時間を短縮することができ、回路板の生産性を高めるこ
とが可能になるものである。
As described above, according to the present invention, a plating catalyst and a compound of a plating catalyst are attached to the surface of an insulating substrate to form a plating underlayer, and a circuit portion of the insulating substrate and a non-circuit By irradiating an electromagnetic wave such as a laser corresponding to the pattern of the non-circuit portion to the boundary region of the portion, after removing the plating underlayer of the irradiated portion irradiated with the electromagnetic wave such as the laser leaving the non-irradiated portion, Since plating is applied to the plating underlayer, it is sufficient that laser irradiation is performed on the boundary region between the circuit portion and the non-circuit portion. Compared with this, the laser irradiation processing time can be shortened, and the productivity of the circuit board can be increased.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示すものであり、(a)乃
至(e)はそれぞれ斜視図である。
FIG. 1 shows an embodiment of the present invention, and (a) to (e) are perspective views.

【符号の説明】[Explanation of symbols]

1 絶縁性基材 2 めっき下地層 3 回路部 4 非回路部 5 回路 DESCRIPTION OF SYMBOLS 1 Insulating base material 2 Plating base layer 3 Circuit part 4 Non-circuit part 5 Circuit

───────────────────────────────────────────────────── フロントページの続き (72)発明者 中村 良光 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 内野々 良幸 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 鎌田 策雄 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 中嶋 勲二 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 鈴木 俊之 大阪府門真市大字門真1048番地松下電工株 式会社内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoshimitsu Nakamura 1048 Kadoma Kadoma, Osaka Pref. Matsushita Electric Works, Ltd. (72) Inventor Yoshiyuki Uchino 1048 Kadoma Kadoma, Kadoma, Osaka Pref. (72) Inventor Norio Kamada 1048 Kadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Works Co., Ltd. (72) Inventor Isuji Nakajima 1048 Kadoma Odoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Works Co., Ltd. 1048 Kadoma, Kamon, Fumonma-shi Matsushita Electric Works, Ltd.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性基材の表面にめっき用触媒、めっ
き用触媒の化合物を付着させてめっき下地層を形成し、
絶縁性基材の回路部と非回路部の境界領域に、非回路部
のパターンに対応してレーザ等の電磁波を照射すること
によって、非照射部を残してレーザ等の電磁波を照射し
たこの照射部のめっき下地層を除去した後、めっき下地
層にめっきを施すことを特徴とする回路板の製造方法。
1. A plating catalyst and a compound of a plating catalyst are attached to a surface of an insulating substrate to form a plating underlayer.
By irradiating the boundary region between the circuit part and the non-circuit part of the insulating base material with an electromagnetic wave such as a laser corresponding to the pattern of the non-circuit part, the non-irradiated part is irradiated with the electromagnetic wave such as a laser while leaving the non-irradiated part. A method for manufacturing a circuit board, comprising: plating a plating base layer after removing a plating base layer in a portion.
JP2000338086A 2000-11-06 2000-11-06 Manufacturing method of circuit board Pending JP2001177219A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000338086A JP2001177219A (en) 2000-11-06 2000-11-06 Manufacturing method of circuit board

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP21194193A Division JP3153682B2 (en) 1993-08-26 1993-08-26 Circuit board manufacturing method

Publications (1)

Publication Number Publication Date
JP2001177219A true JP2001177219A (en) 2001-06-29

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Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011004802A1 (en) * 2009-07-10 2011-01-13 三共化成株式会社 Method for producing formed circuit component
JP2011042818A (en) * 2009-08-19 2011-03-03 Sankyo Kasei Co Ltd Method for producing three-dimensional formed circuit component

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011004802A1 (en) * 2009-07-10 2011-01-13 三共化成株式会社 Method for producing formed circuit component
JP2011017069A (en) * 2009-07-10 2011-01-27 Sankyo Kasei Co Ltd Method for manufacturing formed-circuit parts
JP2011042818A (en) * 2009-08-19 2011-03-03 Sankyo Kasei Co Ltd Method for producing three-dimensional formed circuit component

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