JP2001177146A - Triangular shape semiconductor element and manufacturing method therefor - Google Patents

Triangular shape semiconductor element and manufacturing method therefor

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Publication number
JP2001177146A
JP2001177146A JP36337499A JP36337499A JP2001177146A JP 2001177146 A JP2001177146 A JP 2001177146A JP 36337499 A JP36337499 A JP 36337499A JP 36337499 A JP36337499 A JP 36337499A JP 2001177146 A JP2001177146 A JP 2001177146A
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surface
semiconductor
substrate
triangular
layer
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Masahiro Koto
Hiroaki Okagawa
Yoichiro Ouchi
Kazuyuki Tadatomo
一行 只友
洋一郎 大内
広明 岡川
雅弘 湖東
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Mitsubishi Cable Ind Ltd
三菱電線工業株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element capable of easily isolating an element from an epitaxial wafer in high yield and having no maldistribution of a injected carrier amount as fast as possible. SOLUTION: The triangular shape semiconductor element comprises a laminated structure for sequentially growing an Si-doped n-type GaN layer 2 through a GaN or AlN buffer layer 1 on a sapphire (c) surface substrate 1, an n-type AlGaN clad layer 31, an InGaN MQW light emitting layer 4, an Mg-doped p-type AlGaN clad layer 32, and a p-type GaN contact layer 5. In this case, the profile shape of the element becomes a triangular shape surrounded at its sidewall by and equivalent M surface ( 1-100} surface). Since such an element structure has an equivalent surface of the sidewall surface, hence has entirely equal crackableness and a sectional shape. Thus, the isolation of the element can be facilitated at a high quality level. As a result, the yield of the product can be improved.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明が属する技術分野】本発明は、六方晶系化合物半導体層を備える三角形状の半導体素子、例えば半導体発光素子及び受光素子に関するものである。 The present invention relates] is triangular semiconductor device comprising a hexagonal compound semiconductor layer, for example to a semiconductor light-emitting element and a light receiving element.

【0002】 [0002]

【従来の技術】近年、GaN系化合物半導体からなる発光素子や受光素子の開発が盛んに行われている。 In recent years, development of a light emitting element and a light receiving element formed of a GaN-based compound semiconductor has been actively performed. 一般的に素子形状としては立方体の形状で作られ、素子の上から見た形状は正方形又は長方形の矩形形状とされている。 Commonly element shape made in the shape of a cube, shape viewed from the top of the element is square or rectangular rectangular. ところで、GaN系化合物半導体は、サファイア基板上に結晶成長される場合が多いが、サファイアもGa Meanwhile, GaN-based compound semiconductor is are often grown on a sapphire substrate, even sapphire Ga
Nも硬い材料であるので、ダイシングのみで素子を完全に切り出すことは難しい。 Since N also a hard material, it is difficult to cut only the element entirely in dicing. このため、部分的なダイシング又はスクライブにより傷を与え、この傷を始点として割ることによって素子を分離するのが一般的である。 Therefore, given the wound by partial dicing or scribing, it is common to separate the elements by dividing the wound as a starting point.

【0003】 [0003]

【発明が解決しようとする課題】しかしながら、GaN The object of the invention is to, however, GaN
などの六方晶系の化合物半導体は、その結晶の基本構造からして互いに直交する面の両方、即ち矩形の素子の全ての面を高品位に割り出すことは困難である。 Compounds of hexagonal system such as semiconductors, both surfaces which are orthogonal to each other and from the basic structure of the crystal, i.e. be determined all aspects of rectangular elements with high quality is difficult. 例えば、 For example,
サファイア基板ではM面({1−100}面)が割れやすいが、直行するA面({11−20}面)は割れにくいという特性があり、M面でならば容易に且つ高品位に分割できるが、A面であるとスクライビングでは奇麗に分割できないという問題がある。 M-plane is a sapphire substrate ({1-100} plane) but is easily broken, there is a characteristic that A plane ({11-20} plane) is less cracking orthogonal, easily and divided into high quality if at M plane possible, it is impossible to clean divided in scribing to be a-plane. 従って、六方晶系の化合物半導体にて矩形の半導体素子を作製しようとする場合、 Therefore, when attempting to produce a rectangular semiconductor element in a compound semiconductor of hexagonal,
高品位分割ができない面を不可避的に具備せねばならず、エピタキシャル成長基板から素子をスクライブして分離する際に不良品が発生する可能性が大きくなるという問題があった。 The high-quality division can not face without must inevitably causes including, defective products there is a problem that can occur increases during separation by scribing the device from the epitaxial growth substrate.

【0004】また、例えばサファイア等の絶縁性基板上に半導体層を成長させた矩形の半導体発光素子の場合、 Further, for example, in the case of a rectangular semiconductor light emitting element and the semiconductor layer is grown on an insulating substrate such as sapphire,
その電極としては、矩形素子の対向する角の部分にボンディング用の電極をそれぞれ形成するのが一般的である As the electrodes, it is common to form respective electrodes for bonding to portions of the opposite corners of the rectangular element
(実用新案登録3027676号公報)。 (Utility Model Registration 3027676 JP). しかし、このような素子構造並びに電極構造であると、ボンディング電極が配置されていない残りの角付近の領域に注入されるキャリヤ量が少なくなるといった問題がある。 However, if it is such a device structure and the electrode structure, there is a problem carrier amount is reduced to be injected into the region near the remaining corner bonding electrode is not disposed.

【0005】従って本発明は、エピタキシャルウェハからの素子分離を容易に且つ歩留まりよく行うことができ、さらにはキャリア注入量の偏在が可及的に生ずることがない半導体素子を提供することを目的とする。 Accordingly the present invention comprises a purpose of the isolation from the epitaxial wafer easily and can yield performed well, further provides a semiconductor device uneven distribution of carrier injection amount is never as much as possible to produce to.

【0006】 [0006]

【課題を解決するための手段】本発明の半導体素子は、 Means for Solving the Problems A semiconductor device of the present invention,
六方晶系結晶の基板と、その上に形成された六方晶系化合物半導体とからなる三角形状の半導体素子であって、 A substrate of hexagonal crystal, a triangular-shaped semiconductor element composed of a thereon formed hexagonal compound semiconductor,
前記六方晶系化合物半導体の側周囲の面が{1−10 Surface of the side periphery of the hexagonal compound semiconductor is {1-10
0}面で構成されている、若しくは、前記六方晶系結晶基板の側周囲の面が{1−100}面で構成されていることを特徴とするものである。 0} is composed of plane, or is characterized in that the surface on the side periphery of the hexagonal crystal substrate is composed of a {1-100} plane.

【0007】上記半導体が、GaNを主な構成材料としている場合に本発明は特に好適である。 [0007] The semiconductor is, the present invention in the case where the GaN as a main constituent material is particularly preferred. 具体的には、< More specifically, <
1−100>方向と等価な3方向の切断面を備える厚肉のサファイア基板に、薄肉のGaN系化合物半導体層が成長されてなる三角形状の半導体素子が好適である。 A sapphire substrate thick with a 1-100> direction equivalent three directions of the cut surface, triangular shaped semiconductor element GaN-based compound semiconductor layer of the thin-walled, which are grown are preferred.

【0008】より具体的な本発明の半導体素子は、六方晶系化合物半導体層が少なくとも導電型の異なる2層以上の半導体層を有し、該三角形状の半導体素子に付与する電極パターンを、第1導電型の半導体層の表面に形成される透明電極と、この透明電極上であって三角形の一つの頂点近傍に配置される第1のボンディング電極と、 The semiconductor device of specific invention than [0008], hexagonal compound semiconductor layer has two or more layers of semiconductor layers having different at least conductivity type, an electrode pattern to be imparted to the triangular semiconductor device, the a transparent electrode formed on the surface of the first conductivity type semiconductor layer, a first bonding electrode disposed one near the vertex of the triangle a on the transparent electrode,
第1導電型の半導体層の一部切り欠きにより表出された第2導電型の半導体層の表面であって、前記第1のボンディング電極が配置された頂点と対向する三角形の辺に近接させて配置された第2のボンディング電極とから構成することを特徴とするものである。 A surface of the second conductivity type semiconductor layer which is exposed by the notch portion of the first conductive type semiconductor layer, is close to the sides of the triangle facing the vertex of the first bonding electrode is arranged it is composed of a second bonding electrode disposed Te is characterized in.

【0009】上記構成において、三角形状の半導体素子の各コーナー部に、曲面が施与するようにすることをが望ましい。 [0009] In the above configuration, in each corner portion of the triangular-shaped semiconductor element, that the curved surface is such that applied is desired.

【0010】また、本発明にかかる半導体素子の製法は、六方晶系結晶の基板上に六方晶系化合物半導体を成長させて積層体を形成し、該積層体の前記基板側表面において基板結晶の<11−20>方向にあたる三方向にスクライブ傷を入れ、若しくは半導体側表面において半導体結晶の<11−20>方向にあたる三方向にスクライブ傷を入れ、該スクライブ傷に沿って分割することで前記積層体から三角形状の半導体素子を得ることを特徴とするものである。 Furthermore, preparation of the semiconductor device according to the present invention, on a substrate of hexagonal crystal by growing a hexagonal compound semiconductor to form a laminate, the substrate crystal in the substrate-side surface of the laminate <11-20> put scribed in three directions corresponding to the direction, or put scribed in three directions corresponding to <11-20> direction of the semiconductor crystals in the semiconductor surface, the laminate by splitting along the scribed it is characterized in that to obtain a triangular-shaped semiconductor element from the body.

【0011】 [0011]

【作用】上記本発明の構成によれば、割れやすい面(例えばサファイアのM面)で周囲が形成された、三角形の形状の素子構造であるので、素子の側壁が高品位に形成された素子を提供することができる。 According to the configuration of the action The present invention, ambient in fragile surfaces (eg, M plane of the sapphire) are formed, since the element structure of triangular shape, element sidewall elements are formed in high quality it is possible to provide a. 即ち、エピタキシャル成長基板からの素子分離の際に、スクライブの傷を入れるだけで簡単に且つ側壁の品質が良好な状態で分割することができる。 That is, it is possible to the time of isolation from the epitaxial growth substrate, the quality of simple and sidewall just put scratches scribing dividing in good condition. この結果、光取り出し効率も向上するという付随的作用も奏する。 As a result, also Kanade incidental effect of also improving light extraction efficiency.

【0012】また、請求項5に示す態様でボンディング電極を配置することによって、三角形の一つの頂点から対向する辺へ電流が流れる様にできるので、チップ全面にキャリヤ注入が可能になり、矩形素子の場合に問題となるキャリア注入の偏在の問題を解消できる。 [0012] By arranging the bonding electrode in the manner shown in claim 5, it is possible from one of the vertices of the triangle as current flows into the sides opposing enables carrier injection over the entire surface of the chip, rectangular element You can eliminate the uneven distribution of the problem of the made carrier injection problem in the case of.

【0013】さらに本発明の半導体素子の製法によれば、六方晶系結晶基板若しくは化合物半導体は120° Furthermore, according to the manufacturing method of the semiconductor device of the present invention, the hexagonal crystal substrate or a compound semiconductor is 120 °
互いにずれた三方向の<11−20>方向線を有するが、これに沿ってスクライブ傷を入れて割ることで、若干の面乱れが発生する可能性はあるものの、割られてできた面をほぼ{1−100}面とすることができ、高品質な面で囲まれた三角形状の半導体素子を製造することができる。 Has three directions of <11-20> direction lines offset from one another, by dividing put scribed along which though slight surface turbulence is likely to occur, was Deki been divided surface approximately {1-100} may be a surface, it is possible to manufacture a triangular-shaped semiconductor device surrounded by high quality surface.

【0014】 [0014]

【発明の実施の態様】以下発明の実施態様につき詳細に説明する。 [Aspect of the practice of the invention will be described in detail embodiments of the following invention. 図1は一般的なGaN系LED構造の一例を示した図である。 Figure 1 is a diagram showing an example of a general GaN-based LED structure. 図にしたがって説明すると、サファイアc面基板1上に、低温成長したGaNまたはAlNバッファ層10を介してSiドープのn型GaN層2、n With reference to FIG, on the sapphire c-plane substrate 1, a low temperature grown GaN or AlN buffer layer 10 through the n-type Si-doped GaN layer 2, n
型AlGaNクラッド層31、InGaN系のMQW発光層4、Mgドープのp型AlGaNクラッド層32、 Type AlGaN cladding layer 31, MQW light emitting layer 4 of InGaN-based, Mg-doped p-type AlGaN cladding layer 32,
p型GaNコンタクト層5を順次成長して素子構造のエピタキシャル成長基板(エピ基板)が形成される。 p-type epitaxial growth substrate sequentially growing device structure GaN contact layer 5 (epitaxial substrate) is formed. この時、サファイア基板1の面方位とGaN系デバイス構造部Dの面方位は30度ずれることが知られている。 At this time, the plane orientation of the plane orientation and the GaN-based device structure portion D of the sapphire substrate 1 is known to deviate 30 degrees. すなわち、サファイア基板1のM面、A面がGaN系デバイス構造部DのA面、M面となる。 That, M plane of the sapphire substrate 1, A plane is A-plane, M-plane of GaN-based device structure portion D.

【0015】通常のフォトリソグラフィー技術、RIE [0015] The conventional photolithography technique, RIE
技術、電極形成技術を使って素子化したあと、サファイア面側からダイヤモンドのポイントでスクライブ(けがく)し、機械的に曲げ応力を加えてブレーク(破断)して素子分離する。 Technology, After element processing using an electrode formation technology, scribed (scribing) with diamond points from the sapphire side, added mechanical bending stress isolation to break (fracture) with. この時、サファイア基板の方が圧倒的に厚いために、サファイア基板の割れ方に素子分離の仕上がりが殆ど左右される。 In this case, due to the overwhelmingly thicker sapphire substrate, finish most dependent of the isolation to crack the way of the sapphire substrate. 図1の様に方形状にチップを切り出す場合、サファイアA面({11−20}面)とM面({1−100}面)で側面が囲まれた形状となる。 When cutting a chip in a square shape as in FIG. 1, a shape sides surrounded by sapphire A plane ({11-20} plane) and M plane ({1-100} plane). この時、M面の方が比較的平たんな面となり、A面はがたがたした荒れた面となる。 In this case, those of the M surface is a relatively flat surface, A plane is rattling the rough surface. 一方、M面はサファイアのへき開面であるR面({1−102}面)が発生しやすい性質も合わせ持ち、特段の注意が必要となる。 On the other hand, M surface has also to R-plane ({1-102} plane) property of easily generated is cleavage plane of the sapphire requires otherwise note.

【0016】すなわち、直交する面の性質が大きく異なるために、素子分離工程に特別な注意が必要であり、得られたチップの形状も異方性が強い。 [0016] That is, because the nature of the orthogonal plane are largely different, it requires special attention to the isolation step, shape anisotropy of the resulting chip is strong. このため、異常な割れ方をする場合が多発し、製品の歩留まりを低下させる要因となっている。 Therefore, when an abnormal cracks way is frequently, which is a factor of lowering the product yield.

【0017】これに対し、図2は本発明にかかるGaN [0017] In contrast, GaN according to Figure 2 the present invention
系LED構造の一例を示し、サファイアc面基板1上に、低温成長したGaNまたはAlNバッファ層10を介してSiドープのn型GaN層2、n型AlGaNクラッド層31、InGaN系のMQW発光層4、Mgドープのp型AlGaNクラッド層32、p型GaNコンタクト層5を順次成長した積層構造を備えている点は上記と同様であるが、素子の外形形状が、その側壁が等価なM面({1−100}面)で囲まれた三角形をしている点で相違している。 Shows an example of the system LED structure on the sapphire c-plane substrate 1, a low temperature grown GaN or n-type GaN layer 2 of Si-doped through the AlN buffer layer 10, n-type AlGaN cladding layer 31, MQW light emitting layer of InGaN-based 4, p-type Mg doped AlGaN is clad layer 32, that it includes sequentially grown layered structure a p-type GaN contact layer 5 are as defined above, the outer shape of the element, the sidewalls equivalent M surface It is different in that it the triangle surrounded by ({1-100} plane). このような素子構造であれば、側壁面が等価な面であるから、全く同一の割れやすさ、断面形状をしており、容易に且つ高品位に素子分離が行える結果、製品の歩留まりの向上を達成できる。 With such a device structure, because it is the equivalent plane side wall surface, quite ease cracking of the same, has a cross-sectional shape, the results can be performed easily and isolation in high quality, improve product yield It can be achieved. なお、本発明において{1−100}面という場合、その面が完全無欠に{1−100}面であることのみを指すのではなく、スクライブの際や素子分割の際等に不可避的に生じてしまうような若干の誤差を許容するものである。 In the case of {1-100} plane in the present invention, not refer to only the surface is {1-100} plane flawless, inevitably occur when such during scribing and device division certain errors that would those tolerated.

【0018】上記三角形状のGaN系LEDに付与する電極パターンは、図示するように、p型GaNコンタクト層5の表面に形成される透明電極71と、この透明電極71上であって三角形の一つの頂点近傍に配置される第1のボンディング電極61と、p型半導体層の一部切り欠きにより表出されたn型GaN層2の表面であって、前記第1のボンディング電極61が配置された頂点と対向する三角形の辺に近接させて配置された第2のボンディング電極62と、第2のボンディング電極62から延伸される帯状電極72とから構成している。 The electrode pattern to be imparted to the triangular GaN-based LED, as illustrated, a transparent electrode 71 formed on the surface of the p-type GaN contact layer 5, one triangle a on the transparent electrode 71 one of the first bonding electrode 61 vertices are arranged in the vicinity, a part cut-away exposed n-type surface of GaN layer 2 by the p-type semiconductor layer, the first bonding electrode 61 is arranged and a second bonding electrode 62 disposed in close proximity to the sides of the triangle facing the vertex constitutes a strip electrode 72, which is drawn from the second bonding electrode 62.

【0019】取出電極の位置関係をこのように配置することにより、三角形に頂点に形成された第1のボンディング電極61から、第2のボンデング電極62が形成された辺までの距離が略等しくなり、この結果均一な電流注入を可能とすることができる。 [0019] The positional relationship between the take-out electrode by such arrangement, the first bonding electrode 61 formed on the vertex in a triangle, the distance to the side where the second Bondengu electrode 62 is formed is substantially equal , it is possible to enable this result uniform current injection. 発光素子の場合、外部量子効率を方形の場合と比較すると、約15%向上することが可能である。 For the light emitting element and the external quantum efficiency compared with the case of the square, it is possible to improve by about 15%.

【0020】本発明で用いる六方晶系化合物半導体としては、例えばGaN、AlGaN、InGaAlN、I Examples of the hexagonal compound semiconductor used in the present invention, for example GaN, AlGaN, InGaAlN, I
nGaNなどが例示できる。 Such as nGaN can be exemplified. 目的とする半導体素子が発光素子である場合、基板側からGaNバッファ層、Si When a semiconductor device of interest is a light emitting device, GaN buffer layer from the substrate side, Si
ドープn−GaN層、Siドープn−AlGaN層、I Doped n-GaN layer, Si-doped n-AlGaN layer, I
nGaN系多層量子井戸構造層、Mgドープp−AlG nGaN-based multi-layer quantum well structure layer, Mg-doped p-AlG
aN層、Mgドープp−GaN層からなる多層構造が例示できる。 aN layer, multilayer structures can be exemplified made of Mg-doped p-GaN layer.

【0021】また本発明で用いる六方晶系の結晶基板としては、サファイア基板、SiC基板、GaN基板、Z [0021] As the crystal substrate of the hexagonal system used in the present invention, a sapphire substrate, SiC substrate, GaN substrate, Z
nOなどの各種六方晶系の結晶基板を用いることが出来るが、この基板の上に成長させる六方晶系化合物半導体の品質を向上させるためには、サファイア基板、SiC nO It is possible to use various hexagonal crystal substrate, such as, in order to improve the quality of the hexagonal growing crystal compound semiconductor on the substrate is a sapphire substrate, SiC
基板、GaN基板を用いることが好ましい。 Substrate, it is preferable to use a GaN substrate.

【0022】本発明の代表的な実施例として、上述したように、サファイア基板上にGaN系化合物半導体からなる発光層を成長させたLEDが挙げられる。 Representative examples of the invention, as described above, GaN-based LED light-emitting layer was grown to a compound semiconductor can be mentioned on a sapphire substrate. この場合、サファイア基板の面方位とGaN系化合物半導体の面方位は30度ずれることになるが、一般的にLED等のデバイスは、発光部等を構成するGaN系化合物半導体層は10μm以下程度の薄肉であり、これに対しサファイア基板は50〜500μm程度の厚肉である。 In this case, the plane orientation of the plane orientation and the GaN-based compound semiconductor of the sapphire substrate will be displaced 30 degrees, typically such as an LED device, GaN-based compound semiconductor layer constituting the light-emitting portion or the like of the degree 10μm or less is a thin-walled, whereas the sapphire substrate is a thick of about 50~500μm. 従ってこのような場合にあっては、厚肉のサファイア基板の切断面を、ほぼ<1−100>方向と等価な3方向の切断面を備えるように素子分離すれば、容易且つ高品位な素子分離が行い得る。 Therefore in a case such, the cut surfaces of the sapphire substrate of thick, if isolation to comprise approximately <1-100> direction equivalent three directions of the cut surface, easy and high-quality elements separation can be carried out.

【0023】本発明の三角形状の半導体素子は、エピタキシャル成長基板から各素子が三角形状を呈するように、しかもその分離面がほぼ{1−100}面となるように素子分離をすることで得られる。 The triangular-shaped semiconductor device of the present invention is obtained by the device from the epitaxial growth substrate to exhibit a triangular, yet the isolation as the separation surface is substantially {1-100} plane . このような分離の方法としては、エピタキシャル成長基板の前記基板側表面において基板結晶の<11−20>方向にあたる三方向にスクライブ傷を入れ、該スクライブ傷に沿ってナイフエッジで機械的な力をかける等して分割する方法が挙げられる。 As a method for such separation, putting scribing cracks in three directions corresponding to <11-20> direction of the substrate crystal in the substrate-side surface of the epitaxial growth substrate, applying a mechanical force with a knife edge along the scribed how to divide the like by equally.

【0024】基板が半導体層より充分厚い通常の場合は上記の方法で良い。 [0024] The substrate may the method as described above in the case of sufficiently thick than usual semiconductor layer. 例えば、GaN系半導体発光素子の場合は80μm程度の厚さのサファイア基板に数μm厚さのGaN系化合物半導体層が積層された態様となるが、この場合サファイア基板の裏面にスクライブ傷を入れて割れば、サファイアの{1−100}面とGaNの{1−100}面との間には30°のズレが存在しているものの、厚さによる優位性により全体がサファイアの{1−100}面で分割されることになる。 For example, although several μm thick GaN-based compound semiconductor layer of the sapphire substrate of about 80μm thickness in the case of GaN-based semiconductor light-emitting element is laminated manner, a scribe scratches on the rear surface of this case sapphire substrate by dividing, although there is displacement of 30 ° between the sapphire {1-100} plane of GaN of {1-100} plane, generally by superiority due to the thickness of the sapphire {1-100 It will be split} plane. 一方、サファイア基板が40μm程度の厚さで、GaN系化合物半導体層の厚さが20μm程度の特殊な素子にあっては、 On the other hand, in the sapphire substrate of about 40μm thickness, in the thickness of the GaN-based compound semiconductor layer is a special element of approximately 20 [mu] m,
サファイア基板の裏面側から割るとGaN層が機械強度的に優勢となって奇麗な分割面が得られない可能性があるので、このような場合は、半導体側表面において半導体結晶の<11−20>方向にあたる三方向にスクライブ傷を入れて割るようにしてもよい。 Since Dividing from the back side of the sapphire substrate GaN layer may not be obtained clean dividing plane becomes mechanical strength to predominate, such a case, the semiconductor surface of the semiconductor crystal <11-20 > it may be divided When a scribe scratch in three directions corresponding to the direction. なお、サファイアに代えてSiC基板やGaN基板を用いる場合は、上記の{1−100}面のズレは生じないため、基板側、半導体側のいずれから割っても良い。 In the case of using a SiC substrate or a GaN substrate in place of sapphire, because not caused misalignment of the above {1-100} plane, the substrate side, may be divided from one of the semiconductor side.

【0025】ボンディング電極61,62の配置位置は、一方が三角形の頂点に位置し、他方が当該頂点と対向する辺に沿った任意の位置にあれば良い。 The position of the bonding electrodes 61 and 62, one is located at the apex of the triangle, the other may be in any position along the side opposite to the said apex. 例えば図2 For example, FIG. 2
においては、第2のボンディング電極62を対向辺の中央に配置しているが、これを第1のボンディング電極6 In, although disposing the second bonding electrode 62 in the center of the opposing side, the first bonding electrode so 6
1が配置されていない残りの2つの頂点のいずれか近傍に配置するようにしても良い。 1 may be arranged in the vicinity one of the remaining two vertices that are not disposed. また、第2のボンディング電極62を頂点に配置し、第1のボンディング電極6 Further, the second bonding electrode 62 disposed on the apex, the first bonding electrode 6
1をその対向辺の中央付近に配置してもよい。 1 may also be arranged near the center of the opposing side.

【0026】透明電極71は実質的に透明な導電性薄膜で構成された電極が用いられるが、この他に不透明ではあるが櫛型に電極パターンを設けることで実質的に透明性を担保した電極であっても良い。 The transparent electrode 71 is substantially transparent conductive thin film configured electrode is used, there is opaque Other was backed substantially transparent by providing an electrode pattern in a comb-shaped electrode it may be. また、帯状電極72 Also, the strip electrodes 72
は電流注入効率をより向上させたい場合に必要に応じて設ければ良い。 It may be provided as necessary when it is desired to improve the current injection efficiency.

【0027】なお、GaN基板上にGaN系のデバイス構造を形成した場合、基板とデバイス構造部の結晶方位が一致しているので、素子断面全部が等価なM面({1 [0027] Note that when forming a device structure of a GaN-based on a GaN substrate, the crystal orientation of the substrate and the device structure are the same, the element cross-section entirely equivalent M plane ({1
−100}面)で三方が囲まれることになりより好ましい。 More preferable it will be three sides surrounded by -100} plane). また、導電性の基板であるので、第一のボンディング電極61は三角形の頂点の隅、あるいは中央付近とどこにでも設けることができる。 Further, since it is a conductive substrate, the first bonding electrode 61 can be provided even corners or near the where the center, the apex of the triangle.

【0028】ところで、本発明にあっては半導体素子を三角形状とするため、そのコーナー部は自ずと矩形素子に比べて鋭利となり機械的破損を受け易くなりがちである。 By the way, in the present invention to a semiconductor device and a triangular shape, the corner portion is naturally prone susceptible to mechanical failure becomes sharp as compared to the rectangular element. そこで、コーナー部には面取り的な曲面を施与することが望ましい。 Therefore, the corner portion is desirably of applying a chamfer curved surface. この曲面の形成方法としては、エッチング加工用のマスク形状を曲面に施与する等の方法を採用することができる。 The method of forming the curved surface, it is possible to employ a method such as applying a mask shape for etching a curved surface.

【0029】 [0029]

【実施例】以下具体的な実施例につき説明する。 [Example] will be explained below specific examples. 本実施例では図2に示した構造のサファイア基板上にデバイス構造を形成した例を示す。 In the present embodiment shows an example of forming a device structure on a sapphire substrate having the structure shown in FIG. 使用した結晶成長装置は通常のMOVPE装置である。 Crystal growth apparatus used is usually of the MOVPE apparatus. まず、サファイアc面基板をMOVPE装置の反応管内の所定の場所に装填し、10 First, loading the sapphire c-plane substrate in place of the reaction tube MOVPE apparatus, 10
50℃の水素雰囲気中で5分間サーマルクリーニングを行った。 5 min thermal cleaning was carried out in a 50 ° C. a hydrogen atmosphere. 次に、350℃まで基板温度を下げてからAl Then, Al was lowered substrate temperature to 350 ° C.
Nのバッファ層を20nm成長し、1000℃まで昇温してから3μmのn−GaNを成長した。 A buffer layer of N was 20nm grown, to grow an n-GaN of 3μm from was heated to 1000 ° C.. ドーパントはSiである。 Dopant is Si. 更に、50nm厚みのn−AlGaNを成長し、700℃に基板温度を下げてInGaN系の層(MQW構造、Well層は3層)を成長した。 Furthermore, the growth of the n-AlGaN of 50nm thickness, a layer of InGaN system by lowering the substrate temperature to 700 ° C. (MQW structure, Well layer 3 layer) was grown. 再度、 again,
1000℃に昇温してからMgドープのp−AlGaN From the temperature was raised of Mg-doped to 1000 ℃ p-AlGaN
層を30nm成長し、引き続きp−GaN層を成長した。 The layers were 30nm growth, continued growth of the p-GaN layer. 反応管内雰囲気を窒素ガスに切り替えて室温まで冷却した。 The reaction tube atmosphere was cooled to room temperature is switched to nitrogen gas.

【0030】通常のフォトリソグラフィー技術、反応性イオンエッチング技術(RIE)、真空蒸着技術を使ってエピタキシャル基板を素子加工した。 The conventional photolithographic technique, reactive ion etching technique (RIE), and device processing the epitaxial substrate using vacuum deposition techniques. サファイア基板は350μmの厚みがあるので、全体を80μmになるように研磨を行った。 Since the sapphire substrate is the thickness of 350 .mu.m, was polished so that the entire 80 [mu] m. その後、サファイア基板側からダイヤモンド刃の付いたポイントで<11−20>方向と等価な3方向にスクライブした。 Then scribed <11-20> direction equivalent three directions at the point marked with the sapphire substrate side of the diamond blade. スクライブの傷に沿ってナイフエッジで機械的な力をかけて素子分離を行った。 Was isolation over a mechanical force with a knife edge along the scribe wounds. その結果、等価な{1−100}面で囲まれたLE LE Consequently, surrounded by equivalent {1-100} plane
Dチップが作製された。 D chip is fabricated.

【0031】 [0031]

【発明の効果】以上説明した通りの本発明の三角形状の半導体素子によれば、側周囲を構成する面が{1−10 According to a triangular-shaped semiconductor device of the present invention as has been described in the foregoing, the surface constituting a side periphery {1-10
0}面で構成されているので、エピタキシャル成長基板からの素子分割の際、デバイスチップの各端面が均質な形状でブレーキングされる。 0} which is configured by surface, when the device divided from the epitaxial growth substrate, the end faces of the device chip is braking in a homogeneous form. 従って、極めて高品位な側周囲を備える半導体素子を得ることができ、製品の歩留まりを向上させることができる。 Therefore, it is possible to obtain a semiconductor device having a very high quality side periphery, thereby improving the yield of products. また、三角形状とすることで、キャリヤ注入も全面に均等に起こるために、量子効率も格段に向上させることができる。 In addition, by a triangular shape, in order to take place evenly carrier injection even entirely, it can be dramatically improved quantum efficiency.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】従来の矩形型GaN系LED構造を示す斜視図である。 1 is a perspective view showing a conventional rectangular-type GaN-based LED structure.

【図2】本発明の三角形状のGaN系LED構造を示す斜視図である。 It is a perspective view showing a triangular GaN-based LED structure of the present invention; FIG.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 基板 31,32 クラッド層 4 発光層 61,62 ボンディング電極 D GaN系デバイス構造部 1 substrates 31 and 32 cladding layer 4 the light-emitting layers 61 and 62 bonding electrode D GaN-based device structure

───────────────────────────────────────────────────── フロントページの続き (72)発明者 大内 洋一郎 兵庫県伊丹市池尻4丁目3番地 三菱電線 工業株式会社伊丹製作所内 Fターム(参考) 5F041 AA03 AA41 CA05 CA23 CA34 CA40 CA46 CA65 CA74 CA76 CA77 CA88 ────────────────────────────────────────────────── ─── front page of the continuation (72) inventor Yoichiro Ouchi Hyogo Prefecture Itami Ikejiri 4-chome third address Mitsubishi cable Industries Co., Ltd. Itami Works in the F-term (reference) 5F041 AA03 AA41 CA05 CA23 CA34 CA40 CA46 CA65 CA74 CA76 CA77 CA88

Claims (7)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 六方晶系結晶の基板と、その上に形成された六方晶系化合物半導体とからなる三角形状の半導体素子であって、前記六方晶系化合物半導体の側周囲の面が{1−100}面で構成されていることを特徴とする三角形状の半導体素子。 1. A hexagonal system and a substrate of crystal, a triangular-shaped semiconductor element composed of a thereon formed hexagonal compound semiconductor, the surface on the side periphery of the hexagonal compound semiconductor is {1 triangular semiconductor device characterized by being constituted by -100} plane.
  2. 【請求項2】 六方晶系結晶の基板と、その上に形成された六方晶系化合物半導体とからなる三角形状の半導体素子であって、前記六方晶系結晶基板の側周囲の面が{1−100}面で構成されていることを特徴とする三角形状の半導体素子。 Wherein a substrate of hexagonal crystal, a triangular-shaped semiconductor element composed of a thereon formed hexagonal compound semiconductor, the surface on the side periphery of the hexagonal crystal substrate {1 triangular semiconductor device characterized by being constituted by -100} plane.
  3. 【請求項3】 上記六方晶系化合物半導体が、GaNを主な構成材料としていることを特徴とする請求項1または2記載の半導体素子。 Wherein said hexagonal compound semiconductor, a semiconductor device according to claim 1 or 2, wherein the that the GaN as the main constituent material.
  4. 【請求項4】 側周囲の面が{1−100}面で構成されている三角形状で厚肉のサファイア基板に、薄肉のG 4. A thick in triangular surface surrounding side is constituted by {1-100} plane sapphire substrate, thin G
    aN系化合物半導体層が成長されてなる請求項2記載の三角形状の半導体素子。 aN based compound semiconductor layer are grown claims 2 triangular semiconductor device according.
  5. 【請求項5】 六方晶系化合物半導体層が少なくとも導電型の異なる2層以上の半導体層を有し、該三角形状の半導体素子に付与する電極パターンを、第1導電型の半導体層の表面に形成される透明電極と、この透明電極上であって三角形の一つの頂点近傍に配置される第1のボンディング電極と、第1導電型の半導体層の一部切り欠きにより表出された第2導電型の半導体層の表面であって、前記第1のボンディング電極が配置された頂点と対向する三角形の辺に近接させて配置された第2のボンディング電極とから構成することを特徴とする請求項1または2に記載の半導体素子。 5. The hexagonal compound semiconductor layer has two or more layers of semiconductor layers having different at least conductivity type, an electrode pattern to be imparted to the triangular-shaped semiconductor element, on the surface of the first conductive type semiconductor layer a transparent electrode formed, and a first bonding electrode is placed even on the transparent electrode in one near the vertex of the triangle, the second, which is exposed by the notch portion of the first conductive type semiconductor layer a surface of the conductive semiconductor layer, wherein, characterized in that composed of a second bonding electrode to which the first bonding electrode is disposed close to the sides of the triangle facing the vertex disposed the semiconductor device according to claim 1 or 2.
  6. 【請求項6】 上記三角形状の半導体素子の各コーナー部に、曲面が施与されていることを特徴とする請求項1 6. A each corner of the triangular-shaped semiconductor device according to claim 1, the curved surface is characterized in that it is applied
    〜5いずれかに記載の半導体素子。 5 The semiconductor device according to any one.
  7. 【請求項7】 六方晶系結晶の基板上に六方晶系化合物半導体を成長させて積層体を形成し、該積層体の前記基板側表面において基板結晶の<11−20>方向にあたる三方向にスクライブ傷を入れ、若しくは半導体側表面において半導体結晶の<11−20>方向にあたる三方向にスクライブ傷を入れ、該スクライブ傷に沿って分割することで前記積層体から三角形状の半導体素子を得ることを特徴とする半導体素子の製法。 7. grown hexagonal hexagonal compound semiconductor on a substrate crystal to form a laminate, the <11-20> direction corresponding to three directions of the substrate crystal in the substrate-side surface of the laminate put scribing cracks, or the semiconductor surface placed scribed in <11-20> direction corresponding to three directions of the semiconductor crystals, to obtain a triangular-shaped semiconductor device from the laminate by splitting along the scribed preparation of a semiconductor device characterized.
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