JP2001176885A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent peeling and breakage of a gate electrode in a manufacturing process of a Schottky junction gate type field-effect transistor. SOLUTION: The gate electrode of the Schottky junction gate type field-effect transistor and an ohmic electrode in the source-drain region are formed simultaneously using the same metal. Then the gate electrode and the ohmic electrode adjacent to it are temporarily connected using a conductive layer in the manufacturing process of a semiconductor device. Subsequently, a cleaning process, such as ultrasonic cleaning, is applied to a compound semiconductor substrate in this state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a compound semiconductor field-effect transistor.

[0002]

2. Description of the Related Art Since a compound semiconductor such as GaAs has a higher electron mobility than Si, it has excellent high frequency characteristics, and a field effect transistor (hereinafter referred to as a MESFET) using a Schottky junction gate or an integrated analog. Various developments to signal amplifier circuits, digital signal amplifier circuits, and the like are in progress. And such a MESFE
The miniaturization of the gate length is most effective for speeding up.

Hereinafter, a typical method for manufacturing such a MESFET will be described with reference to FIG. FIG. 5 is a sectional view of a MESFET formed on a compound semiconductor in the order of manufacturing steps.

[0004] As shown in FIG.
In the spacer oxide film 102 on 01, there is a gate opening formed at a desired place by a known dry etching technique. Then, a Schottky conductive layer 103 is formed on the entire surface by WSi sputtering, and a gate electrode 104 is formed thereon by plating or the like.

Next, as shown in FIG. 5B, using the gate electrode 104 as an etching mask, the Schottky conductive layer 103 is processed by a known dry etching technique.
An isolated strip-shaped gate electrode is formed.

Conventionally, in the case of a MESFET used in the millimeter wave band (30 GHz or more), in order to improve the cutoff frequency and the maximum oscillation frequency, as shown in FIG.
The spacer oxide film 102 is entirely removed from the surface of the GaAs substrate 101 by wet etching of HF (hydrofluoric acid) or vapor etching of HF. Then, a protective insulating film 105 is formed on the entire surface to protect the gate electrode 104. Further, the n ⁺ type diffusion layer 106 is formed by the ion implantation of Si and the heat treatment. These n ⁺ type diffusion layers 106
Are the source / drain regions of the MESFET. In this way, the parasitic capacitance between the gate and the source / drain is reduced.

Finally, as shown in FIG. 5D, a desired region is opened by wet etching by a known photolithography technique, and an ohmic electrode 107 is formed by AuGe deposition and a lift-off process. Thus, the basic structure of the conventional MESFET is formed.

[0008]

However, in such a conventional method, ultrasonic cleaning (hereinafter referred to as US processing) in the cleaning process after the removal of the spacer oxide film 102 or the lift-off process causes the gate electrode 104 to lie laterally. When there is no object supporting the gate electrode 104 when a directional force is applied, the gate electrode 104 is likely to be broken or the Schottky conductive layer 103 is likely to be peeled off from the Schottky interface.

Such a problem becomes more remarkable as the gate length of the MESFET becomes smaller.

An object of the present invention is to provide a method of manufacturing a semiconductor device which prevents the above-mentioned peeling or breaking of a gate electrode by a simple method.

[0011]

For this purpose, a method of manufacturing a semiconductor device according to the present invention comprises the steps of forming an insulating film on a compound semiconductor substrate and providing an opening in a predetermined region of the insulating film; Forming a gate electrode and a source / drain ohmic electrode of the Schottky junction gate type field effect transistor with the same metal at the same time.

Further, a method of manufacturing a semiconductor device according to the present invention
Forming an insulating film on the compound semiconductor substrate and providing a plurality of openings reaching the semiconductor substrate surface in the insulating film;
Forming a diffusion layer for a source / drain of a Schottky junction gate type field effect transistor on the surface of the semiconductor substrate in a predetermined opening of the plurality of openings;
A step of forming a conductive layer covering the entire surface of the semiconductor substrate in the opening, and forming a gate electrode of a Schottky junction gate type field effect transistor on the conductive layer on the opening; Simultaneously forming the ohmic electrodes with the same metal.

After the gate electrode and the source / drain ohmic electrodes of the Schottky junction gate type field effect transistor are simultaneously formed of the same metal, a resist mask covering the gate electrode and the adjacent ohmic electrode is formed. Forming a resist, etching the conductive layer using the resist mask as an etching mask, etching and removing the entire insulating film, and removing a first protective insulating layer over the entire surface after removing the insulating film. And a step of cleaning the semiconductor substrate.

Further, after the formation of the first protective insulating layer,
The conductive layer remaining between the gate electrode and the adjacent ohmic electrode and the first protective insulating layer are selectively etched away to separate the gate electrode and the adjacent ohmic electrode. Then, after separating the gate electrode from the adjacent ohmic electrode, a second protective insulating layer is formed on the entire surface.

Here, the conductive layer is formed by laminating a barrier metal and a silicide in this order. Alternatively, the gate electrode and the ohmic electrode are formed by Au plating.

As described above, according to the present invention, the gate electrode of the Schottky junction gate type field effect transistor and the ohmic electrodes of the source / drain regions are simultaneously formed of the same metal. Further, a gate electrode and an ohmic electrode adjacent thereto are temporarily connected by a conductive layer in a manufacturing process of a semiconductor device. Then, the semiconductor substrate is cleaned in this state. For this reason, there is no occurrence of defects such as breakage of the gate electrode in the manufacturing process of the MESFET and peeling of the sputtered metal from the Schottky interface.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A feature of the present invention is that in a method of manufacturing a GaAs MESFET having a fine gate length, a gate electrode and an ohmic electrode are formed of the same metal in the same step, and the metal of the gate electrode and the ohmic electrode is further formed. By selectively removing the gate electrode, peeling or breaking of the gate electrode is prevented.

Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. Here, FIG. 1 and FIG. 2 are cross-sectional views in the order of the manufacturing process of the MESFET of the present invention.

First, as shown in FIG.
An opening for forming a gate electrode and an ohmic electrode is formed in a desired place in the spacer oxide film 2 on the substrate 1 by a known dry etching technique. And
The n ⁺ type diffusion layer 3 is formed by the ion implantation of Si and the heat treatment. These n ⁺ -type diffusion layers 3 become source / drain regions of the MESFET.

In this state, a conductive layer 4 such as WSi / TiN / Pt is laminated on the entire wafer by sputtering or the like.
Is formed. Here, TiN / Pt is a barrier metal of titanium nitride / platinum, and WSi is tungsten silicide.

Next, as shown in FIG. 1B, the resist mask 5 is used as a mask for Au plating, and a gate electrode 6 and an ohmic electrode 7 are formed by a known plating technique.

Thereafter, as shown in FIG. 1C, a resist mask 8 is formed between the adjacent gate electrode 6 and ohmic electrode 7, and the conductive layer 4 is selectively removed by a known dry etching technique. .

By doing so, the conductive layer 4 is left around the gate electrode 6. Then, the resist mask 8 is removed. In such a state, as shown in FIG. 1D, the spacer oxide film 2 is removed by etching with HF in a gas phase. Subsequently, a first protective insulating layer 9 is formed on the entire surface by chemical vapor deposition (CVD) of a silicon oxide film.
Is formed. The first protective insulating layer 9 also enters the hollow portion and adheres to the surface of the remaining conductive layer 4.

Next, as shown in FIG. 2A, a resist mask 10 having an opening between the gate electrode 6 and the ohmic electrode 7 is formed by a known photolithography technique. Then, as shown in FIG. 2B, the first protective insulating layer 9 and the conductive layer 4 between the adjacent gate electrode 6 and ohmic electrode 7 are etched away by a known dry etching technique. Then, the resist mask 10 is removed and removed in a known manner.

Finally, as shown in FIG. 2C, a second protective insulating layer 11 is formed on the entire surface. This second protective insulating layer 11 is a silicon nitride film. In this way ME
The basic structure of the SFET is formed.

As described above, in the present invention, since the gate electrode 6 is formed simultaneously with the ohmic electrode 7 in the same step,
There is no step of forming the ohmic electrode 107 by metal vapor deposition after forming the gate electrode 104 as in the related art, and the step of forming the MESFET can be shortened.
Further, in the cleaning step after the removal of the spacer oxide film 2, the US
During processing, the gate electrode 6 is supported by the adjacent ohmic electrode 7. For this reason, since there is this support against the lateral force, it is possible to prevent such a defect that the gate electrode 6 is broken. Therefore, the production yield is high and MESF
The capacitance existing between the gate and the source of ET is reduced, and M
The performance such as the cutoff frequency of the ESFET is improved, and a higher frequency can be achieved.

Next, a second embodiment of the present invention will be described with reference to FIGS. Here, FIG. 3 shows the ME of the present invention.
It is sectional drawing of the manufacturing process order of some SFETs. And
FIG. 4 is a plan view corresponding to the above sectional view. Here, the same components as those of the first embodiment are denoted by the same reference numerals. The feature of the second embodiment is that an opening is formed in the resist mask 8 by the selective removal of the conductive layer 4 described in FIG. 1C of the first embodiment.

As in the first embodiment, as shown in FIG. 3A, a gate electrode and an ohmic electrode are formed on the spacer oxide film 2 on the GaAs substrate 1 by a known dry etching technique. Opening is formed.
Here, as shown in FIG.
And source / drain openings 13 are formed adjacent to each other and alternately. Then, the n ⁺ -type diffusion layer 3 is formed by the ion implantation of Si and the heat treatment. These n ⁺ -type diffusion layers 3 become source / drain regions of the MESFET. In this state, as shown in FIGS. 3 (a) and 4 (a), WSi / TiN / P
The conductive layer 4 to be laminated as t is formed.

Here, similarly to the first embodiment, the conductive layer 4 having the silicide / barrier metal structure forms a Schottky junction at the gate opening 12 and n at the source / drain opening 13. Ohmic connection with ⁺ type diffusion layer 3.

Next, as shown in FIGS. 3B and 4B, the resist mask 5 is used as a mask for Au plating, and a gate electrode 6 and an ohmic electrode 7 are formed by a known plating technique. .

Next, as shown in FIGS. 3C and 4C, a resist mask 8a is formed between the adjacent gate electrode 6 and ohmic electrode 7. Here, a resist opening 14 is formed in a predetermined region in the resist mask 8a. Then, the conductive layer 4 is selectively removed by a known dry etching technique.

The following is the same as that described in the first embodiment. That is, by doing so, the conductive layer 4 is left around the gate electrode 6. Then, the resist mask 8a is removed. In such a state, as shown in FIG. 1D, the spacer oxide film 2 is removed by etching with HF in a gas phase. Subsequently, a first protective insulating layer 9 is formed on the entire surface by a chemical vapor deposition (CVD) method of a silicon oxide film.

Next, as shown in FIG. 2A, a resist mask 10 having an opening between the gate electrode 6 and the ohmic electrode 7 is formed by a known photolithography technique. Then, as shown in FIG. 2B, the first protective insulating layer 9 and the conductive layer 4 between the adjacent gate electrode 6 and ohmic electrode 7 are etched away by a known dry etching technique. Then, the resist mask 10 is removed and removed in a known manner.

Finally, as shown in FIG. 2C, a second protective insulating layer 11 is formed on the entire surface. This second protective insulating layer 11 is a silicon nitride film. In this way ME
The basic structure of the SFET is formed.

As described above, in the second embodiment, the resist opening 14 is provided between the gate electrode 6 and the ohmic electrode 7.
Are formed. Therefore, the resist opening 14
Through this, the conductive layer 4 and the spacer oxide film 2 can be quickly removed by etching, and the above-mentioned etching step is greatly reduced. In addition, the same effect as that described in the first embodiment is obtained.

In the above embodiment, TiN / Pt is used as the barrier metal, and WSi is used as the silicide. And these form the conductive layer. The present invention is not limited to such a barrier metal or silicide. It should be noted that a similar effect can be obtained even if another barrier metal or silicide is applied.

[0037]

As described above, according to the present invention, the gate electrode of the Schottky junction gate type field effect transistor and the ohmic electrodes of the source / drain regions are simultaneously formed of the same metal. In the manufacturing process of the semiconductor device, the gate electrode and the ohmic electrode adjacent thereto are temporarily connected by a conductive layer. Then, the semiconductor substrate is cleaned in this state.

For this reason, according to the method of manufacturing a semiconductor device of the present invention, defects such as breakage of the gate electrode and peeling of the Schottky conductive layer from the Schottky interface in the MESFET manufacturing process occur. Is gone.

The effect of the present invention becomes more remarkable as the gate length becomes shorter in order to improve the driving capability of the MESFET or shorten the driving frequency. The present invention relates to a MESFET formed on a compound semiconductor such as GaAs.
To further enhance the performance of the device.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a first embodiment of the present invention in the order of manufacturing steps.

FIGS. 2A and 2B are cross-sectional views illustrating a first embodiment of the present invention in the order of manufacturing steps.

FIG. 3 is a cross-sectional view illustrating a second embodiment of the present invention in the order of manufacturing steps.

FIG. 4 is a plan view for explaining a second embodiment of the present invention in the order of manufacturing steps.

FIG. 5 is a cross-sectional view illustrating a related art in the order of manufacturing steps.

[Explanation of symbols]

Reference Signs List 1,101 GaAs substrate 2,102 spacer oxide film 3,106 n ⁺ -type diffusion layer 4 conductive layer 5,8,8a, 10 resist mask 6,104 gate electrode 7,107 ohmic electrode 9 first protective insulating layer 11th 2 protective insulating layer 12 gate opening 13 source / drain opening 14 resist opening 103 Schottky conductive layer 105 protective insulating film

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA05 BB06 BB09 BB28 BB30 CC01 CC03 DD08 DD16 DD37 DD52 DD53 DD65 FF07 FF18 GG12 5F102 GB01 GC01 GD01 GJ05 GS02 GT03 GT05 GV06 GV07 GV08 HB01 HB02 HB07 HB08

Claims (7)

[Claims] A step of forming an insulating film on a compound semiconductor substrate and providing an opening in a predetermined region of the insulating film; Forming a drain ohmic electrode and the same metal at the same time. 2. A step of forming an insulating film on a compound semiconductor substrate and providing a plurality of openings reaching the surface of the semiconductor substrate in the insulating film, wherein the semiconductor substrate has a predetermined opening among the plurality of openings. Forming a source / drain diffusion layer of a Schottky junction gate type field effect transistor on the surface, forming a conductive layer covering the semiconductor substrate surface of the opening over the entire surface, Forming a gate electrode of a Schottky junction gate type field effect transistor and ohmic electrodes for source / drain simultaneously with the same metal on the conductive layer above. 3. A resist mask for simultaneously forming the gate electrode and the source / drain ohmic electrodes of the Schottky junction gate type field effect transistor with the same metal and covering the gate electrode and the adjacent ohmic electrode. Forming, the step of etching and removing the conductive layer using the resist mask as an etching mask, and the step of etching and removing all the insulating film,
3. The method according to claim 2, further comprising: forming a thin first protective insulating layer on the entire surface after removing the insulating film; and cleaning the semiconductor substrate. 4. After the formation of the first protective insulating layer, the conductive layer remaining between the ohmic electrode adjacent to the gate electrode and the first protective insulating layer are selectively removed by etching, and the first protective insulating layer is adjacent to the gate electrode. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the ohmic electrode is separated. 5. The method according to claim 4, wherein a second protective insulating layer is formed on the entire surface after the gate electrode and the adjacent ohmic electrode are cut off. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive layer is formed by laminating a barrier metal and a silicide in this order. 7. The semiconductor device according to claim 1, wherein the gate electrode and the ohmic electrode
The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed by u plating.