TWI505378B - Half lift-off processes to fabricate a gate electrode of a semiconductor component - Google Patents

Description

Semiconductor device gate half lift process

The present invention relates to a gate fabrication technique for a semiconductor device, and more particularly to a gate half lift process for a semiconductor device.

It is known that the surface roughness of the gate of a semiconductor component directly affects the characteristics of DC, high frequency and anti-noise of the component. When the surface is rougher, the surface state and surface defects increase, and the gate leakage current rate increases, resulting in gate control. Reduced ability. Generally, the gate structure of a semiconductor component is fabricated in a back-end process, and the success or failure of the gate structure can affect the overall component process yield. The gate structure is mainly made by using the conventional wet lift technique to lift away the metal other than the gate by the liquid lift, but the adhesion between the gate metal and the component layer of the semiconductor component is too weak. However, it is easy to cause the entire metal film to be detached, or the adhesion between the metal film and the lift-off photoresist is too strong to separate the complete shape of the gate metal. Therefore, the traditional use of wet lift technology must strictly control the ratio of the thickness of the photoresist to the thickness of the metal film. When the thickness of the photoresist is too thin or the thickness of the metal film is too thick, it cannot be lifted off the gate metal. The rest of the metal caused the move to fail.

In order to solve the above problems, the main object of the present invention is to provide a gate half lift process for a semiconductor device, which can effectively improve the success rate of the gate lift to improve the gate process.

A second object of the present invention is to provide a gate half lift process for a semiconductor device, which can improve the thickness ratio of the photoresist layer to the thickness of the metal layer film and the thickness of the metal layer film, thereby increasing the gate metal. The thickness can still be lifted smoothly to reduce the gate resistance.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses a gate half lift process for a semiconductor device, comprising the steps of: firstly, providing a semiconductor device comprising a component layer and a source and a drain on the component layer; a photoresist layer on the semiconductor device, the first photoresist layer covering the source and the drain; then, patterning the first photoresist layer to form at least one gate opening at the source Between the drains; thereafter, depositing a metal layer film on the first photoresist layer, and filling the gate film into the gate opening to form a gate metal; and then forming a second light Resisting a layer on the metal layer film; thereafter, patterning the second photoresist layer to form an etch stop pad on the gate opening, the etch stop pad being larger than the gate opening to completely cover the a gate metal; thereafter, etching the metal layer film to etch away the exposed portion of the metal layer film outside the etch barrier; thereafter, removing the second photoresist layer and the first photoresist layer The metal layer film is covered by the second photoresist layer and The outer one of gate opening and exposed portions of the gate metal and the residual portion of the metal layer of the thin film; and finally, sonicated manner remove residual portion of the metal thin film layer.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the foregoing gate half lift process, the residual thickness of one of the remaining portions of the metal layer film may be less than a protruding thickness of the gate metal on the first photoresist layer.

In the foregoing gate-half lift process, the first photoresist layer provides a lift height that is at least greater than the gate metal in the first photoresist layer One of the upper points highlights the height.

In the above-described gate half lift process, the residual portion of the metal layer film may be in a zigzag shape extending around the periphery of the gate metal.

In the aforementioned gate half lift process, the gate metal may be an elongated metal electrode between the source and the drain.

In the foregoing gate half lift process, the gate opening between the source and the drain may be plural, such that the gate metal is in a plurality of line types.

In the foregoing gate half lift process, the step of etching the metal layer film may include wet etching, and the step of removing the second photoresist layer and the first photoresist layer may include wet Lift off.

100‧‧‧Semiconductor components

110‧‧‧Component layer

111‧‧‧Semiconductor substrate

112‧‧‧buffer layer

113‧‧‧Barrier layer

114‧‧‧First spacer

115‧‧‧channel layer

116‧‧‧Second spacer

117‧‧‧Shawite layer

121‧‧‧ source

122‧‧‧汲polar

123‧‧‧GaAs pad

124‧‧‧ pedestal cushion

130‧‧‧First photoresist layer

131‧‧‧gate opening

140‧‧‧Metal film

141‧‧ ‧ gate metal

142‧‧‧ exposed parts

143‧‧‧ Coverage

144‧‧‧Residual parts

145‧‧‧Sawtooth edge

150‧‧‧second photoresist layer

151‧‧‧etching barrier

H1‧‧‧ lift height

T1‧‧‧ deposition thickness

T2‧‧‧ residual thickness

Figure 1 is a cross-sectional perspective view of a semiconductor device having a gate, a source and a drain.

2A to 2I are schematic cross-sectional views showing steps in a gate half lift process of a semiconductor device in accordance with an embodiment of the present invention.

3A and 3B are schematic views of the components before and after the ultrasonic oscillation step of the gate half lift process according to an embodiment of the present invention.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. For the components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some ratios of dimensions and other related dimensions are either exaggerated or simplified to provide a clearer Chu's description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

In accordance with an embodiment of the present invention, a gate half lift process of a semiconductor device is illustrated on the cross-sectional schematic of steps 2A through 2I and on the components before and after the ultrasonic oscillating step of FIGS. 3A and 3B. See the schematic. A semiconductor device according to the gate half lift process is illustrated as a cutaway perspective view of FIG. The gate half lift process of the semiconductor device includes the following steps.

First, as shown in FIG. 2A, a semiconductor device 100 is provided. The semiconductor device 100 includes an element layer 110 and a source 121 and a drain on the element layer 110, but A gate has not been formed, and the surface of the element layer 110 used to form the gate is a smooth surface. As shown in FIG. 1, the device layer 110 can be a metal oxide semi-false crystal high electron mobility field effect transistor, which comprises a semiconductor substrate 111 at the bottom such as gallium arsenide (GaAs) and sequentially a buffer layer 112 on the semiconductor substrate 111, a barrier layer such as aluminum gallium arsenide (AlGaAs), and a first spacer layer 114 such as aluminum gallium arsenide (AlGaAs) a spacer layer, such as a channel layer of inGaAs (InGaAs), a second spacer layer 116 such as InGaP, and a layer such as phosphating. A Schottky layer 117 of InGaP, the surface of the Schwant layer 117 may form an oxide layer (not shown) between the source 121 and the drain 122 Or may not form an oxide layer. In addition, a gallium arsenide pad layer 123 may be disposed under the source electrode 121, and a pedestal pad layer 124 may be disposed under the drain electrode 122.

Then, as shown in FIG. 2B, a first photoresist layer 130 is formed on the semiconductor device 100, and the first photoresist layer 130 covers the source electrode 121 and the drain electrode 122. The first photoresist layer 130 is selectable from Shipley. Ultra-I 123 i-line photoresist, the application speed is more than 7000 rpm, and the film thickness of the first photoresist layer 130 is about 0.5 micrometers, that is, 500 nanometers (nm) to favor the gate metal 141 layer. Formed into a line width shape; or, the first photoresist layer 130 may be an image reversal photoresist provided by Clariant and numbered AZ5214E, and the application speed is more than 7000 rpm, the first photoresist layer The film thickness of 130 is about 1 micron. Next, as shown in FIG. 2B, the first photoresist layer 130 is patterned to form at least one gate opening 131 between the source 121 and the drain 122. The shape and size of the gate opening 131 can be defined by a yellow lithography method, and the yellow lithography method can use a deep UV light pattern to illuminate the first photoresist layer 130 and then develop to form the gate. Hole 131. In this step, the gate opening 131 between the source electrode 121 and the drain electrode 122 may be plural, so that the subsequently formed gate metal 141 is in a plurality of line types (eg, 1 and 2I). Figure shows).

Thereafter, as shown in FIG. 2C, a metal layer film 140 is deposited on the first photoresist layer 130, and the metal layer film 140 is filled in the gate opening 131 to form a gate metal 141. The material of the metal layer film 140 may be gold (Au). In this embodiment, the first photoresist layer 130 provides a lift height H1 that is greater than a deposition thickness T1 of the metal layer film 140. The deposited thickness T1 of the metal layer film 140 may be about 164 nanometers (nm). In this embodiment, the gate metal 141 can protrude from the lift height H1 provided by the first photoresist layer 130, and the protrusion height is approximately equal to the deposition thickness T1 of the metal layer film 140 (as shown in FIG. 2G). Show).

Thereafter, as shown in FIG. 2D, a second photoresist layer 150 is formed on the metal layer film 140. The formation of the second photoresist layer 150 can be performed by a coating operation of a spin coater. Based on subsequent etching considerations, the second photoresist layer 150 may also be selected from Image reversal photoresist, numbered AZ5214E, supplied by Clariant.

Then, as shown in FIG. 2E, the second photoresist layer 150 is patterned to form an etch stop pad 151 on the gate opening 131. The etch stop pad 151 is larger than the gate opening 131 to The gate metal 141 is completely covered. The etch stop pad 151 can be formed over the gate opening 131 by a yellow lithography.

Thereafter, as shown in FIGS. 2F and 2G, the metal layer film 140 is etched to remove the exposed portion 142 of the metal layer film 140 outside the etch stop pad 151, thereby weakening the gate metal 141 and the metal layer. The bonding force between the other portions of the film 140 includes the covering portion 143 of the metal layer film 140 on the first photoresist layer 130 and away from the gate opening 131. The method of etching the metal layer film 140 may be wet etching, and a potassium iodide solution (KI solution) may be used. In this step, the metal layer film 140 still has a residual portion 144 that is not completely etched. The residual thickness T2 of the residual portion 144 may be smaller than the gate metal 141 protruding from the first photoresist layer 130. The height, that is, the residual thickness T2 is smaller than the deposited thickness T1 of the metal layer film 140. Under the protection of the etch stop pad 151, the surface of the gate metal 141 has a good surface smoothness that is not etched. At the same time, the first photoresist layer 130 also protects the source electrode 121 and the drain electrode 122 from the etching liquid, so the first photoresist layer 130 serves as an anti-ohmic coating layer.

Thereafter, as shown in FIG. 2H, the second photoresist layer 150 and the first photoresist layer 130 are removed to cover the metal layer film 140 and covered by the second photoresist layer 150 and opened at the gate. A portion 143 outside the hole 131 is the portion 143 of the metal layer film 140 that is originally covered by the second photoresist layer 150 and outside the gate opening 131 in FIG. 2G. Further, in this step, the gate metal 141 and the remaining portion 144 of the metal layer film 140 are exposed. The step of simultaneously removing the second photoresist layer 150 and the first photoresist layer 130 is wet lifting and needs The element layer 110 is heated, and the remover used is a photoresist obtained by Microchem.

Finally, as shown in Fig. 2I, the residual portion 144 of the metal layer film 140 is removed by ultrasonic vibration using an ultrasonic oscillator (not shown). As shown in FIG. 3A, before the ultrasonic oscillation step, the residual portion 144 of the metal layer film 140 may be in a zigzag shape extending around the periphery of the gate metal 141, that is, the sawtooth edge 145 of the residual portion 144 in FIG. 3A. . As shown in FIG. 3B, after the ultrasonic oscillation step, the residual portion 144 of the metal layer film 140 is removable to leave the gate metal 141 in a complete shape. As shown in FIG. 3B, the gate metal 141 can be an elongated metal electrode between the source electrode 121 and the drain electrode 122. For example, the gate metal 141 is between the source electrode 121 and the drain electrode 122. The size of the gap can be 1 x 100 μm ² , so the gate metal 141 is in a line type and can be connected to a larger area of the gate pad (not shown). The height of the gate metal 141 can be less than the height of the source 121 and the drain 122 (as shown in FIG. 1).

Therefore, the gate-half lift-off process system of the semiconductor device provided by the present invention can effectively improve the gate lift-off success rate to improve the gate process. Moreover, the thickness ratio of the photoresist layer to the thickness of the metal layer film can be improved for the choice of the photoresist and the thickness of the metal layer film, and the thickness ratio of the photoresist layer to the thickness of the metal layer film can be reduced, which is advantageous for the selection of the thin photoresist to facilitate the gate size. The miniaturization, or increase the gate metal height and other process considerations, so the thickness of the gate metal can be lifted smoothly to reduce the gate resistance. The gate half lift process of the semiconductor device is particularly applicable to the manufacture of microelectronic components, communication components, and low power high speed components.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. It is still within the technical scope of the present invention to make any simple modifications, equivalent changes and modifications made by the skilled artisan without departing from the technical scope of the present invention.

110‧‧‧Component layer

121‧‧‧ source

122‧‧‧汲polar

130‧‧‧First photoresist layer

131‧‧‧gate opening

140‧‧‧Metal film

141‧‧ ‧ gate metal

143‧‧‧ Coverage

144‧‧‧Residual parts

150‧‧‧second photoresist layer

151‧‧‧etching barrier

H1‧‧‧ lift height

T1‧‧‧ deposition thickness

T2‧‧‧ residual thickness

Claims (7)

A gate-half lift-off process for a semiconductor device, comprising: providing a semiconductor device comprising an element layer and a source and a drain on the device layer; forming a first photoresist layer on the semiconductor device The first photoresist layer covers the source and the drain; the first photoresist layer is patterned to form at least one gate opening between the source and the drain; depositing a metal film On the first photoresist layer, and the metal layer film is filled in the gate opening to form a gate metal; forming a second photoresist layer on the metal layer film; patterning the second light a resist layer to form an etch stop pad on the gate opening, the etch stop pad being larger than the gate opening to completely cover the gate metal; etching the metal layer film to etch away the metal layer film a exposed portion outside the etch stop pad; removing the second photoresist layer and the first photoresist layer to lift off the metal layer film covered by the second photoresist layer and outside the gate opening a portion and revealing a residual portion of the gate metal and the metal layer film, The residual portion of the metal layer film is located between the portion of the metal layer film covered by the second photoresist layer and outside the gate opening and the gate metal, and after the etching step and the shifting The residual portion of the metal layer film is exposed in the slit of the second photoresist layer before the step; and the residual portion of the metal layer film is removed by ultrasonic vibration. According to the gate half lift process of the semiconductor device of claim 1, wherein the residual thickness of one of the remaining portions of the metal layer film is smaller than a protruding height of the gate metal on the first photoresist layer. A gate-half lift-off process for a semiconductor device according to claim 1, wherein the first photoresist layer provides a lifting height that is at least greater than a protruding height of the gate metal on the first photoresist layer. The gate half lift process of the semiconductor device according to the first aspect of the patent application, wherein the residual portion of the metal layer film is in a zigzag shape extending around the periphery of the gate metal. The gate half lift process of the semiconductor device according to claim 1, wherein the gate metal is an elongated metal electrode between the source and the drain. The gate half lift process of the semiconductor device according to claim 1, wherein the gate opening between the source and the drain is plural, so that the gate metal is a plurality of lines state. According to the gate half lift process of the semiconductor device of claim 1, wherein the step of etching the metal layer film comprises wet etching, and removing the second photoresist layer and the first photoresist layer The steps include wet lifting.