JP2000353708A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device, with which the prevention of lowering of the yield of production and the improvement of high frequency characteristic can be compatibly accomplished when a microscopic gate electrode is formed, and to obtain a manufacturing method of the semiconductor device. SOLUTION: In a T-shaped cross-sectional gate electrode on which gate resistance is reduced, an insulating film 13, which is formed between a gate electrode 11 and a semiconductor substrate 10 for the purpose of retaining the gate electrode 11, is partially removed in the width direction (longitudinal direction). In the structure, as the gate electrode 11 is retained, and at the same time, an insulating film 12 is partially removed, gate parasitic capacitance can be decreased without lowering the yield of production, when the gate electrode is formed, and high frequency characteristic can also be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor having a fine gate having a T-shaped cross section and a method of manufacturing the same, and more particularly to a semiconductor which avoids a decrease in yield when forming a fine gate electrode and improves high frequency characteristics. The present invention relates to a device and a semiconductor device manufacturing method.

[0002]

2. Description of the Related Art A conventional field-effect transistor having a T-shaped fine gate having a cross-section is disclosed in, for example,
As shown in JP-A-92277, a gate electrode support pattern made of an insulating film material is provided on both sides of a T-shaped gate electrode foot section so as to sandwich the foot section, and the gate is damaged at the time of lift-off. It is used to avoid a decrease in yield due to separation or the like. FIG. 43 is a cross-sectional view illustrating a device structure of a conventional semiconductor device. As shown in FIG. 43, this conventional field effect transistor has a Ga
A T-shaped gate electrode 203 is formed on an As substrate 201, and a T-shaped gate electrode 203 and a GaAs substrate 201 are provided in a state where an insulating material 204 is provided so as to sandwich both sides of the foot of the T-shaped gate electrode 203. It has a shape that fills the gap. As described above, in the related art, by providing the gate electrode support pattern 204, the T-shaped gate electrode 203 is provided.
Irrespective of the width of contact between the substrate and the GaAs substrate 201, the T-shaped gate electrode 203 is not damaged even by ultrasonic treatment or the like applied to remove unnecessary resist at the time of lift-off. It is possible to form well.

[0003]

However, in the prior art, since the space formed between the gate electrode and the substrate is filled with an insulating material without any gap, the space between the gate electrode and the source electrode, between the substrate and the drain electrode is reduced. However, there is a problem in that the parasitic capacitance generated between them becomes large, and the high-frequency characteristics are reduced, particularly, the cutoff frequency and the maximum oscillation frequency are reduced. Further, if all the insulating film material is removed after the lift-off is completed in order to improve the high frequency characteristics, there is also a problem that the yield is reduced due to the fine gate.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device and a semiconductor device capable of avoiding a reduction in yield when forming a fine gate electrode and improving high frequency characteristics. It is to provide a manufacturing method.

[0005]

SUMMARY OF THE INVENTION The gist of the present invention is to provide a semiconductor device capable of avoiding a decrease in yield when forming a fine gate electrode and improving high-frequency characteristics. Having a gate support pattern for holding the T-shaped gate electrode in cross section with an insulating film material so that a portion supporting the gate electrode and a portion not supporting the gate electrode exist in the gate width direction of the gate electrode. The semiconductor device is characterized in that the semiconductor device is configured. The gist of the invention according to claim 2 is that a portion supporting the gate electrode in a gate width direction and a portion not supporting the gate electrode are provided on both the source electrode side of the gate electrode and the drain electrode side of the gate electrode. And the gate support position on the drain electrode side of the gate electrode and the gate support position on the source electrode side of the gate electrode are configured to be symmetrical about the gate electrode as a central axis. The semiconductor device according to claim 1. The gist of the invention described in claim 3 is that, on the source electrode side of the gate electrode, there are a portion supporting the gate electrode and a portion not supporting the gate electrode in a gate width direction, and a drain of the gate electrode is provided. 2. The semiconductor device according to claim 1, wherein the gate support pattern is configured so as to be continuous in the gate width direction on the electrode side. The gist of the invention according to claim 4 is that, on the drain electrode side of the gate electrode, there are a portion supporting the gate electrode and a portion not supporting the gate electrode in a gate width direction, and a source electrode of the gate electrode is provided. 2. The semiconductor device according to claim 1, wherein the gate support pattern is configured so as to be continuously present in a gate width direction on a side. 3. The gist of the invention described in claim 5 is that
On both the source electrode side of the gate electrode and the drain electrode side of the gate electrode, there are a portion that supports the gate electrode in the gate width direction and a portion that does not support the gate electrode. 2. The semiconductor device according to claim 1, wherein the gate support position and the gate support position of the gate electrode on the source electrode side are configured to be asymmetric about the gate electrode. . The gist of the invention described in claim 6 is that the gate electrode is held by an insulating film having a gap at least in a portion in contact with a foot portion of the gate electrode and a substrate. 1 is a semiconductor device. The gist of the invention described in claim 7 is that the gate electrode is held by an insulating film having a gap at least in a portion in contact with a foot portion of the gate electrode and a substrate, and the insulating film holds the gate electrode. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a configuration that does not exist.
The gist of the invention according to claim 8 is that the holding pattern of the gate electrode is formed to include an insulating film having a relative dielectric constant of about 3 to about 1. Exists in the device. The gist of the present invention is that the ratio of the area of the insulating film remaining to support the gate electrode to the area above the gate is set to be larger than 0 and 0.75 or less. 2. The semiconductor device according to claim 1, wherein:
The gist of the invention according to claim 10 is a method of manufacturing a semiconductor device for achieving both a reduction in yield when forming a fine gate electrode and an improvement in high-frequency characteristics, wherein a cross-sectional T-shaped gate having reduced gate resistance is provided. Forming a gate supporting pattern for holding the electrode with an insulating film material, and forming a portion supporting the gate electrode and a portion not supporting the gate electrode in a gate width direction of the gate electrode. In the method of manufacturing a semiconductor device. The gist of the invention according to claim 11 is that a portion supporting the gate electrode in a gate width direction and a portion not supporting the gate electrode are provided on both the source electrode side of the gate electrode and the drain electrode side of the gate electrode. Forming, and forming a gate supporting position on the drain electrode side of the gate electrode and a supporting position on the source electrode side of the gate electrode symmetrically with respect to the gate electrode as a central axis. Item 10 is the method for manufacturing a semiconductor device according to Item 10. The gist of the invention according to claim 12 is a step of forming a portion supporting the gate electrode in the gate width direction and a portion not supporting the gate electrode on the source electrode side of the gate electrode, and forming the gate support pattern. The method of manufacturing a semiconductor device according to claim 10, further comprising a step of forming the gate electrode on the drain electrode side without a break in the gate width direction. The gist of the invention according to claim 13 is a step of forming a portion supporting the gate electrode in a gate width direction and a portion not supporting the gate electrode on the drain electrode side of the gate electrode, The method according to claim 10, further comprising a step of forming the gate electrode on the source electrode side without a break in the gate width direction. The gist of the invention according to claim 14 is that a part supporting the gate electrode in a gate width direction and a part not supporting the gate electrode are provided on both the source electrode side of the gate electrode and the drain electrode side of the gate electrode. Forming a gate, and asymmetrically forming a gate support position on the drain electrode side of the gate electrode and a support position on the source electrode side of the gate electrode with the gate electrode as a central axis. Item 10 is the method for manufacturing a semiconductor device according to Item 10. The gist of the invention described in claim 15 is that the step of holding the gate electrode by an insulating film having a gap at least in a portion in contact with a foot portion of the gate electrode and a substrate is provided. Of the present invention. The gist of the invention described in claim 16 is that the step of forming the holding pattern of the gate electrode using an insulating film having a relative dielectric constant of about 3 to about 1 is provided. Of the present invention. The gist of the invention described in claim 17 is a step of forming a remaining insulating film for supporting the gate electrode so that a ratio of the insulating film to a gate upper area is larger than 0 and 0.75 or less. The semiconductor device manufacturing method according to claim 10, wherein:

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The feature of each of the embodiments described below is that a region where an insulating film exists between a low resistance portion and a substrate in order to hold a T-shaped gate electrode is partially formed in the gate width direction. By providing an insulating film partially in the gate width direction, it is possible to prevent the gate electrode from being destroyed and to prevent an increase in parasitic capacitance. As a result, it is possible to prevent a decrease in gate yield and improve high-frequency characteristics. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First Embodiment) First, the first embodiment of the present invention
The embodiment will be described in detail with reference to the drawings. FIG. 1 is a sectional view for explaining a device structure of a semiconductor device according to a first embodiment of the present invention. Referring to FIG. 1A, a top view of a gate portion of a T-section field effect transistor according to a first embodiment is shown. FIG.
(B) and FIG. 1 (c) are cross-sectional views along the AA ′ cutting line and the BB ′ cutting line in FIG. 1 (a).

In this embodiment, as shown in FIG. 1C, an insulating film 12 is formed between the gate electrode 11 and the semiconductor substrate 10 to hold the gate electrode 11. Further, as shown in the cross-sectional views of FIGS. 1B and 1C, in the cross-sectional portion shown in FIG. 1B, the space between the gate electrode 11 and the semiconductor substrate 10 is buried with an insulating film 12. Figure 1
In the section shown in FIG. 1C, the space between the gate electrode 11 and the semiconductor substrate 10 is buried with an insulating film 12. FIG.
1A, 1B and 1C, the insulating film 12 is partially removed in the width (longitudinal direction) of the gate electrode 11. In the present embodiment, the gate electrode 11
In addition, since the insulating film 12 is partially removed at the same time, the gate yield in forming the gate electrode is improved, the gate parasitic capacitance is reduced, and the high-frequency characteristics can be improved.

(Second Embodiment) Next, a second embodiment of the present invention will be described.
The embodiment will be described in detail with reference to the drawings. FIG. 2 is a sectional view for explaining a device structure of a semiconductor device according to a second embodiment of the present invention. Referring to FIG. 2A, there is shown a top view of a gate portion of a cross-sectional T-shaped field effect transistor as a second embodiment of the present invention. FIG. 2B and FIG. 2C show A- in FIG.
It is sectional drawing along each of A 'cutting line and BB' cutting line.

In this embodiment, FIGS. 2B and 2
As shown in (c), the gate electrode 21 and the semiconductor substrate 20
An insulating film 22 is formed to hold the gate electrode 21 therebetween. Further, as shown in the cross-sectional views of FIGS. 2B and 2C, in the cross-sectional portion shown in FIG. 2B, the gate electrode 21 and the semiconductor are formed on one side (for example, the source electrode side) of the gate electrode 21. The space between the substrates 20 is not buried with the insulating film 22, and the space between the gate electrode 21 and the semiconductor substrate 20 is buried with the insulating film 22 in the cross section shown in FIG. As shown in FIGS. 2A, 2B, and 2C, the insulating film 22 has a width (longitudinal direction) of the gate electrode 21.
Has been partially removed. In the present embodiment, since the insulating film is partially removed at the same time as holding the gate electrode 21, the gate yield at the time of forming the gate electrode is improved, the gate parasitic capacitance is reduced, and the high-frequency characteristics can be improved. It has the effect of becoming. In particular, if the insulating film 22 on the source electrode side is removed as in the present embodiment, the parasitic capacitance between the gate and the source can be reduced, and the cutoff frequency Ft that defines the current gain can be improved.

(Third Embodiment) Next, a third embodiment of the present invention will be described.
The embodiment will be described in detail with reference to the drawings. FIG. 3 is a cross-sectional view for explaining a device structure of a semiconductor device according to a third embodiment of the present invention. Referring to FIG. 3A, there is shown a top view of a gate portion of a cross-sectional T-shaped field effect transistor according to a third embodiment of the present invention. 3 (b) and 3 (c) show A- in FIG. 3 (a).
It is sectional drawing along each of A 'cutting line and BB' cutting line.

In this embodiment, FIGS. 3B and 3
As shown in (c), the gate electrode 31 and the semiconductor substrate 30
An insulating film 32 is formed to hold the gate electrode 31 therebetween. Further, as shown in the cross-sectional views of FIGS. 3B and 3C, in the cross-sectional portion shown in FIG. 3B, the gate electrode 31 and the semiconductor on one side (for example, the drain electrode side) of the gate electrode 31. The space between the substrates 30 is not buried with the insulating film 32, and the space between the gate electrode 31 and the semiconductor substrate 30 is buried with the insulating film 32 in the cross section shown in FIG. As shown in FIGS. 3A, 3B, and 3C, the insulating film 32 is partially removed in the width (longitudinal direction) of the gate electrode 31. In the present embodiment, since the insulating film is partially removed at the same time as holding the gate electrode 31, the gate yield at the time of forming the gate electrode is improved, the gate parasitic capacitance is reduced, and the high-frequency characteristics can be improved. It has the effect of becoming. In particular, if the insulating film 22 on the drain electrode side is removed as in the present embodiment, the parasitic capacitance between the gate and the drain can be reduced, and the maximum oscillation frequency Fma defining the maximum available power gain can be reduced.
x can be improved.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described.
The embodiment will be described in detail with reference to the drawings. FIG. 4 is a sectional view for explaining a device structure of a semiconductor device according to a fourth embodiment of the present invention. Referring to FIG. 4A, a top view of a gate portion of a cross-sectional T-shaped field effect transistor is shown as a fourth embodiment of the present invention. 4 (b) and 4 (c) show A- in FIG. 4 (a).
It is sectional drawing along each of A 'cutting line and BB' cutting line.

In the present embodiment, FIGS.
As shown in (c), the gate electrode 41 and the semiconductor substrate 40
An insulating film 42 is formed to hold the gate electrode 41 therebetween. In addition, as shown in the cross-sectional views of FIGS. 4B and 4C, in the cross-sectional portion shown in FIG. 4B, between the gate electrode 41 and the semiconductor substrate 40 (for example, on the source electrode side).
Is not buried in the insulating film 42. On the contrary, in the cross section shown in FIG. 4C, the insulating film 42 is formed between the gate electrode 41 and the semiconductor substrate 40 (for example, on the drain electrode side).
Not embedded in 4 (a), 4 (b), 4
As shown in (c), the insulating film 42 is partially removed in the width (longitudinal direction) of the gate electrode 41, and the insulating film 42 is alternately present on the drain electrode side and the source electrode side. Thus, the interval between the insulating films 42 can be increased as compared with the first embodiment without lowering the gate yield. In this embodiment mode, the insulating film is partially removed at the same time as the gate electrode 41 is held.
This has the effect of improving the gate yield when forming the gate electrode, reducing the gate parasitic capacitance, and improving the high frequency characteristics.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described.
The embodiment will be described in detail with reference to the drawings. FIG. 5 is a cross-sectional view illustrating a device structure of a semiconductor device according to a fifth embodiment of the present invention. Referring to FIG. 5A, a top view of a gate portion of a cross-sectional T-shaped field effect transistor is shown as a fifth embodiment of the present invention. FIG. 5B is a cross-sectional view taken along the line AA ′ in FIG. 5A.

In this embodiment, as shown in FIG. 5B, an insulating film 72 is provided between the gate electrode 71 and the semiconductor substrate 70.
And a gap 73 is formed to hold the gate electrode 71.
As shown in the cross-sectional view of FIG. 5B, a void 73 is formed in the insulating film 72 between the gate electrode 71 and the semiconductor substrate 70. With the structure shown in FIGS. 5A and 5B, the gate yield at the time of forming the gate electrode is improved, and when the void 73 exists in the insulating film 72, the relative permittivity of the void is the same as that of vacuum. As a result, the gate parasitic capacitance can be reduced as compared with the case where only the insulating film 72 holds,
This has the effect of improving high-frequency characteristics.

(Sixth Embodiment) Next, a sixth embodiment of the present invention will be described.
The embodiment will be described in detail with reference to the drawings. FIG. 6 is a sectional view for explaining a device structure of a semiconductor device according to a sixth embodiment of the present invention. Referring to FIG. 6A, there is shown a top view of a gate portion of a cross-sectional T-shaped field effect transistor according to a sixth embodiment of the present invention. 6 (b) and 6 (c) show A- in FIG. 6 (a).
It is sectional drawing along each of A 'cutting line and BB' cutting line.

In this embodiment, FIGS. 6A and 6
As shown in (c), the gate electrode 81 and the semiconductor substrate 80
An insulating film 82 is formed to hold the gate electrode 81 therebetween. As shown in the cross-sectional views of FIGS. 6B and 6C, in the cross-sectional portion shown in FIG. 6B, the space between the gate electrode 81 and the semiconductor substrate 80 is buried with an insulating film 82. 6C, the space between the gate electrode 81 and the semiconductor substrate 80 is buried with an insulating film 82, and a gap 83 exists in the insulating film 82. As shown in FIGS. 6A, 6B, and 6C, the insulating film 82 is partially removed in the width (longitudinal direction) of the gate electrode 81. In this embodiment, since the insulating film is partially removed at the same time as holding the gate electrode 81, the gate yield at the time of forming the gate electrode is improved, and when the gap 83 exists in the insulating film 82, the ratio of the gap is reduced. Since the dielectric constant becomes 1 which is the same as that of vacuum, there is an effect that the gate parasitic capacitance is reduced and the high-frequency characteristics can be improved as compared with the case where only the insulating film 82 is used.

(Seventh Embodiment) Next, a seventh embodiment of the present invention will be described.
The embodiment will be described in detail with reference to the drawings. FIG. 7 is a sectional view for explaining a device structure of a semiconductor device according to a seventh embodiment of the present invention. Referring to FIG. 7A, a top view of a gate portion of a cross-sectional T-shaped field effect transistor is shown as a seventh embodiment of the present invention. 7 (b) and 7 (c) show A- in FIG. 7 (a).
It is sectional drawing along each of A 'cutting line and BB' cutting line.

In this embodiment, FIGS. 7B and 7
As shown in (c), the gate electrode 91 and the semiconductor substrate 90
An insulating film 92 is formed to hold the gate electrode 91 therebetween. As shown in the cross-sectional views of FIGS. 7B and 7C, in the cross-sectional portion shown in FIG. 7B, the insulating film 92 exists under the gate electrode 91, but the gate electrode 9
1 and the semiconductor substrate 90 are not buried with the insulating film 92, and in the cross section shown in FIG.
The gap between the semiconductor substrate 90 and the semiconductor substrate 90 is buried with an insulating film 92, and a gap 93 exists in the insulating film 92. FIG.
7A, FIG. 7B, and FIG. 7C, the insulating film 92 is partially removed in the width (longitudinal direction) of the gate electrode 91. In this embodiment mode, the insulating film is partially removed at the same time as the gate electrode 91 is held.
The gate yield at the time of forming the gate electrode is improved, and when the gap 93 exists in the insulating film 92, the relative permittivity of the gap becomes 1 which is the same as that of vacuum. This has the effect of reducing the capacitance and improving the high frequency characteristics.

(Eighth Embodiment) Next, an eighth embodiment of the present invention will be described.
The embodiment will be described in detail with reference to the drawings. FIG. 8 is a sectional view for explaining a device structure of a semiconductor device according to an eighth embodiment of the present invention. Referring to FIG. 8A, there is shown a top view of a gate portion of a cross-sectional T-shaped field effect transistor as an eighth embodiment of the present invention. 8 (b) and 8 (c) show A- in FIG. 8 (a).
It is sectional drawing along each of A 'cutting line and BB' cutting line.

In the present embodiment, FIGS.
As shown in (c), the gate electrode 101 and the semiconductor substrate 1
00 to hold the gate electrode 101
2 are formed. Further, as shown in the cross-sectional views of FIGS. 8B and 8C, in the cross-sectional portion shown in FIG.
On one side of the gate electrode 101 (for example, on the source electrode side), the space between the gate electrode 101 and the semiconductor substrate 100 is not buried with the insulating film 102, and even on the buried side, a gap is formed in the insulating film 102. 103 exists. In the cross section shown in FIG.
8 and the semiconductor substrate 100 are buried with an insulating film 102, and a gap 103 exists in the insulating film 102 as in FIG. 8B. 8 (a), 8 (b), 8
As shown in (c), the insulating film 102 is formed on the gate electrode 10.
1 is partially removed in the width (longitudinal) direction. In this embodiment mode, since the insulating film is partially removed at the same time as the gate electrode 101 is held, the gate yield at the time of forming the gate electrode is improved. By setting the dielectric constant to 1 which is the same as that of vacuum, there is an effect that the gate parasitic capacitance is reduced and the high frequency characteristics can be improved as compared with the case where the insulating film 102 is used to hold the dielectric constant.

FIGS. 9 and 10 are sectional views showing a case where an insulating film for gate protection is finally formed according to the present invention.
In the above embodiment, the cross section is improved at the gate formation stage. In the final form of the device, as shown in FIGS. 9 and 10, FIGS. 1 (b), (c) to 8 (b), ( A protective film 1102 is formed on each of the cross-sectional shapes of the first to eighth embodiments shown in c), and a measure is taken to avoid deterioration of the gate electrode 1101 due to moisture or the like.
At this time, FIGS. 9 (a) to 9 (c) and FIGS. 10 (d) to 10 (f)
When the insulating film 1104 or the insulating film 1105 having the void 1106 does not exist between the gate electrode 1101 and the semiconductor substrate 1103, it is necessary to prevent the protective film 1102 from filling the gap. .

(Ninth Embodiment) Next, a ninth embodiment of the present invention will be described.
The embodiment will be described in detail with reference to the drawings. FIG.
FIG. 14 to FIG. 14 are process diagrams for explaining a semiconductor device manufacturing method according to the ninth embodiment of the present invention. FIG.
As shown in (a), a GaAs active layer 1202 (for example, 1 × 10 ⁻¹⁷ cm) required for transistor operation
^An insulating film (for example, a 200 nm thick SiO 2 film) is formed on a semiconductor substrate
₂ , relative permittivity 3.9) 1203 is formed. Subsequently, as shown in FIG. 11B, a first resist film 1204 is applied and formed on the insulating film 1203, and a resist opening 1205 is formed at a desired position by exposure. Then FIG.
As shown in (c), the insulating film 1203 is etched through the resist opening 1205 using the first resist film 1204 as a mask to form an insulating film opening 1206 and expose the GaAs active layer 1202. Subsequently, as shown in FIG. 12D, the exposed GaAs active layer 1202 is etched to a desired depth so as to have a desired threshold. Subsequently, the gate metal 1211 (for example, WSi / Pt / Au
After performing sputter deposition on the entire surface, an etched insulating film opening 1206 is formed on the gate metal 1211.
The second resist film 1 so as to have a desired size
After coating and forming 207, exposure is performed to remove unnecessary portions of the resist, and the gate metal 1211 is exposed. Subsequently, FIG.
As shown in FIG. 2E, the second resist film 1207
The gate metal 1211 exposed with the mask as a mask is dry-etched to form a gate electrode 1208, and the insulating film 1203
Is exposed. Subsequently, as shown in FIG. 12F, a third resist film 1209 is applied and formed on the entire surface. Subsequently, as shown in FIG. 13G, a resist mask of a desired size including the gate electrode 1208 and crossing over the gate electrode 1208 in a stripe pattern as shown in the top view of FIG. Form 1210. Subsequently, FIG.
As shown in the top view of (i), the insulating film 120 exposed by the resist mask 1210 with buffered hydrofluoric acid
3 and the insulating film 1203 under the gate electrode 1208 are removed by etching, and then the unnecessary resist mask 1210 is removed. That is, FIGS. 14 (j) and 14 (k) are cross-sectional views taken along the line AA 'and the line BB' in FIG. 14 (i), respectively. like,
In the cross section shown in FIG.
Removing the insulating film 1203 between the semiconductor substrate 1201 and
In the cross section shown in FIG.
An insulating film 1203 is embedded between the semiconductor substrate 1201 and the insulating film 1203. In the present embodiment, since the insulating film 1203 is partially removed at the same time as holding the gate electrode 11, the gate yield at the time of forming the gate electrode is improved, the gate parasitic capacitance is reduced, and the high frequency characteristics are improved. By such a process, the gate cross-sectional structure shown in FIG. 1 can be formed. The cross-sectional structures in FIGS. 2, 3 and 4 can be easily formed by changing the shape of the resist mask 1210 in FIG.

(Tenth Embodiment) Next, a tenth embodiment of the present invention will be described in detail with reference to the drawings. FIGS. 15 to 18 are process diagrams for explaining a semiconductor device manufacturing method according to the tenth embodiment of the present invention. FIGS. 15 to 18 show an embodiment of a process of forming the structure of FIG. 4 using a low-k insulating film having applicability. FIG.
It is assumed that up to 2 (f) are formed by the same process. FIG.
As shown in the top view of (a), a part of the gate electrode 1306 and a first insulating film 1303 (for example, a silicon dioxide film,
A first resist mask 1308 having an opening pattern exposing a part of the relative dielectric constant (3.9) is formed. continue,
As shown in the top view of FIG. 15B, a first insulating film 1303 having a void 1310 exposed through a first resist mask 1308 and a first insulating film 1303 under a gate electrode 1306 are formed.
The insulating film 1303 is removed by etching. That is, FIG. 16C and FIG. 16D show A-
FIG. 16 is a cross-sectional view along the A ′ cutting line and the BB ′ cutting line. As shown in this cross-sectional view, in the cross-sectional portion shown in FIG. 16C, one side of the gate electrode 1306 (for example,
On the source electrode side), the first insulating film 1303 between the gate electrode 1306 and the semiconductor substrate 1301 is removed. In the cross section shown in FIG. 16D, for example, the gate electrode 1306 and the semiconductor substrate 1301 on the drain side are removed. The first insulating film 1303 between them is removed. Subsequently, FIG.
As shown in the top view of (e), a coatable second insulating film having a smaller relative dielectric constant than the first insulating film 1303 (for example, a fluorinated polyimide FPI-136M manufactured by DuPont, a relative dielectric constant of 2.6) , Hereinafter referred to as an FPI film) 1311. Subsequently, as shown in a top view of FIG. 17F, the first insulating film 1303 and the second insulating film 1311 over the gate electrode 1306 are removed by oxygen plasma. Subsequently, FIG.
As shown in the top view of (g), the remaining first insulating film 130
3 is removed by wet etching with buffered hydrofluoric acid. That is, FIG. 18 (h) is equivalent to A-
FIG. 4 is a cross-sectional view taken along the line A ′,
Reference numeral 11 denotes a structure in which the gate electrode 1306 is partially removed in the width (longitudinal direction) of the gate electrode 1306 and the second insulating film 1311 is alternately provided on the drain electrode side and the source electrode side. Since the insulating film is partially removed at the same time as the holding, the gate yield at the time of forming the gate electrode is improved, the gate parasitic capacitance is reduced, and the effect of improving the high-frequency characteristics is brought about. The gate cross-sectional structure shown in FIG. 4 can be formed.

(Eleventh Embodiment) Next, an eleventh embodiment of the present invention will be described in detail with reference to the drawings. FIG. 19 to FIG. 24 are process diagrams for explaining the semiconductor device manufacturing method according to the eleventh embodiment of the present invention. As shown in FIG. 19A, a GaAs active layer 1402 (for example, 1 × 10 ⁻¹⁷ ) necessary for transistor operation is provided.
A first insulating film 1403 (for example, SiO ₂ having a thickness of 200 nm and a relative dielectric constant of 3.9) is formed over a semiconductor substrate 1401 on which an n layer of cm ⁻³ has a thickness of 100 nm. After coating and forming the first resist, the first resist mask 1404 is formed at a desired position by performing exposure and development.
Is formed, and the first insulating film 1403 is exposed. continue,
As shown in FIG. 19B, the first resist mask 14
After the first insulating film 1403 exposed by the step 04 is removed by etching, an unnecessary first resist mask 1404 is removed. FIG. 20 (c) shows a top view of this. Subsequently, as shown in FIG. 20D, a second resist mask 1405 is applied and formed, a second resist mask 1405 is formed by exposure and development, and a resist opening 1406 is formed at a desired position on the first insulating film 1403. To form Then Figure 2
As shown in FIG. 1E, the first insulating film 1403 exposed through the resist opening 1406 is etched to form a gate insulating film opening 1407, and the active layer 1402 is exposed. Subsequently, as shown in FIG.
After removing the resist mask 1405, the second insulating film 1408 having a lower relative dielectric constant than the first insulating film 1403 is formed.
(For example, Dow Cycloten manufactured by Dow Chemical Company)
e 5021 (benzocyclobutene) benzocyc
After forming a low resist, a relative dielectric constant of 2.6, hereinafter a BCB film), a third resist film is applied and formed, and then a third resist mask 1 is formed immediately above the gate insulating film opening 1407.
An opening 409 is formed. Subsequently, as shown in FIG. 21G, the second insulating film is etched through the third resist mask 1409 to form a gate opening 1410, and the active layer 1402 is exposed. Subsequently, FIG.
As shown in (h), the remaining third resist mask 14
After removing 09, the exposed active layer 1402 is etched to a desired depth to a desired threshold. continue,
A gate metal 1411 (for example, a WSi / Pt / Au layer structure) is sputter deposited on the entire surface. Subsequently, FIG.
As shown in (i), a fourth resist film is formed on the gate metal 1411 so as to have a desired size including the gate opening 1410, and then exposed and developed to remove unnecessary portions of the resist. Then, a fourth resist mask 1412 is formed so as to expose the gate metal 1411. Subsequently, as shown in FIG. 22 (j), the gate metal 1411 exposed by the fourth resist mask 1412 is dry-etched to form a gate electrode 1413, and the second insulating film 1408 is exposed. Subsequently, as shown in a top view of FIG. 23 (k), a fifth resist film is applied over the entire surface and a fifth resist mask 1414 which does not cover the end of the first insulating film 1403 is formed. Subsequently, FIG.
As shown in the top view of FIG.
Removes the second insulating film 1408 by dry etching (eg, oxygen), and removes the remaining fifth resist mask 141.
4 is removed. That is, FIGS. 24 (m) and 24 (n)
FIG. 24 is a sectional view taken along the line AA ′ of FIG. 23 (l). As shown in FIG.
8 exist under the gate electrode 1413 and the first
Of the insulating film 1403 can be covered. Subsequently, as shown in FIG. 24N, a void 1415 can be formed in the second insulating film 1408 by removing the first insulating film 1403 by wet etching with buffered hydrofluoric acid. . Gate electrode 1413
And at the same time, the insulating film is partially removed, so that the gate yield during the formation of the gate electrode is improved, the gate parasitic capacitance is reduced, and the effect of improving the high frequency characteristics is brought about. , FIG.
Can be formed as shown in FIG.

(Twelfth Embodiment) Next, a twelfth embodiment of the present invention will be described in detail with reference to the drawings. FIGS. 25 to 30 are process charts for explaining a semiconductor device manufacturing method according to the twelfth embodiment of the present invention. As shown in FIG. 25A, a GaAs active layer 1502 (for example, 1 × 10 ⁻¹⁷ ) necessary for transistor operation is used.
A first insulating film 1503 (for example, SiO ₂ having a thickness of 200 nm) is formed on a semiconductor substrate 1501 on which an n layer of cm ⁻³ has a thickness of 100 nm, and then a first resist is applied and formed. After that, a first resist mask 1504 is formed at a desired position by performing exposure and development, and the first insulating film 1503 is exposed. Subsequently, as shown in FIG. 25B, after the first insulating film 1503 exposed by the first resist mask 1504 is removed by etching, the unnecessary first resist mask 1504 is removed. FIG. 26 (c) shows a top view of this. Subsequently, FIG.
2D, a second resist is applied and formed, a second resist mask 1505 is formed by exposure and development, and a resist opening 150 is formed at a desired position on the first insulating film 1503.
6 is formed. Next, as shown in FIG. 27E, the first insulating film 150 exposed through the resist opening 1506 is formed.
3 is etched to form a gate insulating film opening 1507, exposing the active layer 1502. Subsequently, FIG.
As shown in (f), the remaining second resist mask 15
05, a second insulating film 1508 having a relative dielectric constant smaller than that of the first insulating film 1503 is formed, a third resist film is applied and formed, and then a gate insulating film opening 150 is formed.
An opening made by the third resist mask 1509 is formed directly above 7. Subsequently, as shown in FIG. 27G, the third insulating film is etched through the third resist mask 1509 to form a gate opening 1510, exposing the active layer 1502. Subsequently, as shown in FIG. 28H, after removing the remaining third resist mask 1509, the exposed active layer 1502 is etched to a desired depth so as to have a desired threshold. Subsequently, the gate metal 1511
(For example, a WSi / Pt / Au layer structure) is sputter-deposited on the entire surface. Subsequently, as shown in FIG.
A fourth resist film is formed on the gate metal 1511 so as to have a desired size including the gate opening 1510, and then exposed and developed to remove unnecessary portions of the resist, thereby exposing the gate metal 1511. Next, a fourth resist mask 1512 is formed. Subsequently, as shown in FIG. 28J, the gate metal 1511 exposed by the fourth resist mask 1512 is dry-etched to form the gate electrode 1.
513 is formed, and the second insulating film 1508 is exposed.
Subsequently, as shown in a top view of FIG. 29K, the remaining fourth resist mask 1512 and the exposed second insulating film 1508 are removed. That is, FIG. 29 (l), FIG.
9 (m) is an AA ′ cutting line, BB ′ in FIG. 29 (k).
FIG. 29 is a cross-sectional view taken along the cutting line. As shown in FIG. 29 (l), a second insulating film 1508 is present below the gate electrode 1513 and covers the first insulating film 1503. be able to. At the position shown in FIG.
The first insulating film 1503 and the second insulating film 1508 can be provided below the gate electrode 1513 as a layered structure. Subsequently, the first insulating film 1503 is removed by wet etching with buffered hydrofluoric acid, thereby forming the second insulating film 1508 as shown in FIG.
A void 1515 can be formed therein, and FIG.
As shown in (o), the first insulating film 1503 below the second insulating film 1508 can be removed. Gate electrode 1
At the same time, the first insulating film 150 is partially retained.
3, the gate yield at the time of forming the gate electrode is improved, the gate parasitic capacitance is reduced, and the effect of improving the high-frequency characteristics is brought about. By such a process, as shown in FIG. A gate cross-sectional structure can be formed.

(Thirteenth Embodiment) Next, a thirteenth embodiment of the present invention will be described in detail with reference to the drawings. FIGS. 31 to 36 are process charts for explaining a semiconductor device manufacturing method according to the thirteenth embodiment of the present invention. As shown in FIG. 31A, a GaAs active layer 1602 (for example, 1 × 10 ⁻¹⁷ ) necessary for transistor operation is provided.
A first insulating film 1603 (for example, SiO ₂ having a thickness of 200 nm) is formed over a semiconductor substrate 1601 on which an n layer having a thickness of cm ⁻³ and a thickness of 100 nm are formed, and then a first resist is applied and formed. After that, a first resist mask 1604 is formed at a desired position by performing exposure and development, and the first insulating film 1603 is exposed. Subsequently, as shown in FIG. 31B, after the first insulating film 1603 exposed by the first resist mask 1604 is removed by etching, the unnecessary first resist mask 1604 is removed. continue,
As shown in FIG. 31C, a second resist is applied and formed, a mask 1605 is formed by exposure and development, and a resist opening 1606 is formed at a desired position on the first insulating film 1603. Next, as shown in FIG. 32D, the first insulating film 1603 exposed through the resist opening 1606 is etched to form a gate insulating film opening 1607, and the active layer 1602 is exposed. Subsequently, as shown in FIG. 32E, after removing the remaining second resist mask 1605, the second insulating film 1603 has a lower relative dielectric constant than the first insulating film 1603.
After forming the insulating film 1608, a third resist film is applied and formed, and then the third resist film is formed immediately above the gate insulating film opening 1607.
An opening is formed by the resist mask 1609. Subsequently, as shown in FIG. 32F, the third insulating film is etched through the third resist mask 1609 to form a gate opening 1610, and the active layer 1602 is exposed.
The exposed active layer 1602 is etched to a desired depth to a desired threshold, and then, as shown in FIG. 33 (g), after removing the remaining third resist mask 1609, the gate metal 1611 is removed. (For example, WSi / Pt / Au
Layer structure) is sputter-deposited on the entire surface. Subsequently, FIG.
As shown in FIG. 3 (h), a fourth metal is formed on the gate metal 1611 so as to have a desired size including the gate opening 1610.
After applying and forming the resist film, the resist in an unnecessary portion is removed by exposure and development, and a fourth resist mask 1612 is formed so as to expose the gate metal 1611. Subsequently, as shown in FIG. 33I, the gate metal 1611 exposed by the fourth resist mask 1612 is dry-etched to form a gate electrode 1613, and the second insulating film 1608 is exposed. Subsequently, as shown in the top views of FIGS. 34 (j) and 34 (k), a fifth resist mask 1 covering the gate electrode 1613 in a stripe shape.
614 are formed. Subsequently, as shown in the top view of FIG. 35L, the second insulating film 1608 exposed by the fifth resist mask 1614 and the second insulating film 1608 below the gate electrode 1613 are removed. That is, FIG.
FIG. 35 (n) is a sectional view taken along line AA ′ of FIG.
FIG. 35 is a sectional view taken along each of the B ′ cutting lines, and FIG.
As shown in (m), the second insulating film 1608 exists under the gate electrode 1613 and the first insulating film 16
03 can be covered. FIG.
In the portion shown in FIG. 3N, only the base portion of the gate electrode 1613 can be held by the first insulating film 1603.
Next, the first insulating film 1603 is removed by wet etching with buffered hydrofluoric acid to obtain a structure shown in FIG.
As shown in (o), a gap 1 is formed in the second insulating film 1608.
615 can be formed. In FIG. 36 (p), the first insulating film 1603 has been removed. Since the insulating film is partially removed at the same time as holding the gate electrode 1613, the gate yield at the time of forming the gate electrode is improved, the gate parasitic capacitance is reduced, and the effect of improving high-frequency characteristics is brought about. By such a process, a gate sectional structure as shown in FIG. 6 can be formed.

(Fourteenth Embodiment) Next, a fourteenth embodiment of the present invention will be described in detail with reference to the drawings. FIGS. 37 to 42 are process charts for explaining a semiconductor device manufacturing method according to the fourteenth embodiment of the present invention. As shown in FIG. 37A, a GaAs active layer 1702 (for example, 1 × 10 ⁻¹⁷ ) necessary for transistor operation is provided.
A first insulating film 1703 (for example, SiO ₂ having a thickness of 200 nm) is formed on a semiconductor substrate 1701 on which an n-layer of cm ⁻³ has a thickness of 100 nm, and then a first resist is applied and formed. After that, the first resist mask 1704 is formed at a desired position by performing exposure and development, and the first insulating film 1703 is exposed. Subsequently, as shown in FIG. 37B, after the first insulating film 1703 exposed by the first resist mask 1704 is removed by wet etching with buffered hydrofluoric acid, the unnecessary first resist mask is removed. . Subsequently, a second insulating film 1705 is formed as shown in FIG. Next, as shown in FIG. 38D, after a second resist is applied and formed, the resist opening 17 is formed at a desired position immediately above the first insulating film 1703 by exposure and development using a second resist mask 1706.
07 is formed. Subsequently, as shown in FIG.
Second insulating film 1 exposed through resist opening 1707
705 (eg, FPI film) and first insulating film 170
3 is continuously removed by etching, and the gate insulating film opening 17 is removed.
08 to expose the active layer 1702. continue,
As shown in FIG. 38 (g), the exposed active layer 1702 is etched to a desired depth so as to have a desired threshold to form a gate opening 1709, and then as shown in FIG. 39 (h). After removing the remaining second resist mask 1706, the gate metal 1710 (for example, WSi / Pt /
Au layer structure) is sputter deposited on the entire surface. continue,
As shown in FIG. 39 (i), on the gate metal 1710,
After a third resist film is applied and formed to have a desired size including the gate opening 1709, the third resist film is exposed and developed to remove unnecessary portions of the resist and expose the gate metal 1710 so as to expose the gate metal 1710. A mask 1711 is formed. Subsequently, as shown in FIG. 39 (j), the gate metal 1710 exposed by the third resist mask 1711 is dry-etched to form a gate electrode 1712, and the second insulating film 1705 is exposed. Subsequently, after removing the remaining third resist mask 1711, as shown in the top view of FIG. 40 (k), after forming the third insulating film 1713,
A fourth resist film is applied and formed to form a fourth resist mask 1714 as shown in FIG. 40 (k), which is a top view of FIG. 40 (k) and a sectional view taken along line AA ′ of FIG. Subsequently, as shown in FIGS. 41 (m) and 41 (n) along the AA ′ cutting line and the BB ′ cutting line in FIG. 40 (k), the fourth resist mask 1714 is formed with buffered hydrofluoric acid. Then, the third insulating film 1713 which is exposed is removed, and the second insulating film 1705 is exposed. Subsequently, FIG. 41 (o), FIG.
As shown in FIG. 2 (p), the remaining fourth
Resist mask 1714 and second insulating film 1705
Is removed, and the first insulating film 1703 is exposed. Subsequently, as shown in FIG. 42 (q) and FIG. 42 (r), one side of the gate metal 1710 is held by removing the first insulating film 1703 with buffered hydrofluoric acid,
A structure in which the void 1715 exists can be formed.
Since the insulating film is partially removed at the same time as holding the gate metal 1710 in this manner, the gate yield at the time of forming the gate electrode is improved, the gate parasitic capacitance is reduced, and the effect of improving high-frequency characteristics is brought about. By such a process, the gate sectional structure shown in FIG. 8 is formed.

As described above, according to each of the above embodiments, at least a part of the insulating film provided between the gate electrode and the substrate for supporting the gate is removed in the longitudinal direction of the gate electrode, or the relative dielectric constant is reduced. By embedding with an insulating film material including a low dielectric constant film of 3 or less, a parasitic capacitance generated between a gate electrode and a source electrode or between a gate electrode and a drain electrode can be reduced, and a reduction in yield when forming a gate electrode occurs. There is an effect that a cutoff frequency and a maximum oscillation frequency can be improved, and a semiconductor device and a method of manufacturing a semiconductor device that can improve high-frequency characteristics can be provided.

It should be noted that the present invention is not limited to the above embodiments, and it is clear that the embodiments can be appropriately modified within the scope of the technical idea of the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, and can be set to numbers, positions, shapes, and the like suitable for carrying out the present invention. In each drawing, the same components are denoted by the same reference numerals.

[0032]

According to the present invention, as described above, at least a part of the insulating film provided between the gate electrode and the substrate for supporting the gate is removed in the longitudinal direction of the gate electrode. By embedding with an insulating film material including a low dielectric constant film having a dielectric constant of 3 or less, a parasitic capacitance generated between a gate electrode and a source electrode or between a gate electrode and a drain electrode can be reduced, and the yield at the time of gate electrode formation can be reduced. It is possible to provide a semiconductor device and a method of manufacturing a semiconductor device that can increase cut-off frequency and maximum oscillation frequency without generating the same, and can further improve high-frequency characteristics.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a device structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a device structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining a device structure of a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a device structure of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a sectional view illustrating a device structure of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a device structure of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a device structure of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 8 is a sectional view for explaining a device structure of a semiconductor device according to an eighth embodiment of the present invention;

FIG. 9 is a cross-sectional view showing a case where an insulating film for gate protection is finally formed according to the present invention.

FIG. 10 is a cross-sectional view showing a case where an insulating film for gate protection is finally formed according to the present invention.

FIG. 11 is a process chart for explaining a semiconductor device manufacturing method according to a ninth embodiment of the present invention.

FIG. 12 is a process chart illustrating a method of manufacturing a semiconductor device according to a ninth embodiment of the present invention.

FIG. 13 is a process chart illustrating a method of manufacturing a semiconductor device according to a ninth embodiment of the present invention.

FIG. 14 is a process chart illustrating a method of manufacturing a semiconductor device according to a ninth embodiment of the present invention.

FIG. 15 is a process chart illustrating a method of manufacturing a semiconductor device according to a tenth embodiment of the present invention.

FIG. 16 is a process chart illustrating a method of manufacturing a semiconductor device according to a tenth embodiment of the present invention.

FIG. 17 is a process chart for explaining the semiconductor device manufacturing method according to the tenth embodiment of the present invention;

FIG. 18 is a process chart illustrating a semiconductor device manufacturing method according to a tenth embodiment of the present invention.

FIG. 19 is a process chart illustrating a method of manufacturing a semiconductor device according to an eleventh embodiment of the present invention.

FIG. 20 is a process chart illustrating a method of manufacturing a semiconductor device according to an eleventh embodiment of the present invention.

FIG. 21 is a process chart illustrating a method of manufacturing a semiconductor device according to an eleventh embodiment of the present invention.

FIG. 22 is a process chart illustrating a method of manufacturing a semiconductor device according to an eleventh embodiment of the present invention.

FIG. 23 is a process chart illustrating a method of manufacturing a semiconductor device according to an eleventh embodiment of the present invention.

FIG. 24 is a process chart illustrating a method for manufacturing a semiconductor device according to an eleventh embodiment of the present invention.

FIG. 25 is a process chart illustrating a method of manufacturing a semiconductor device according to a twelfth embodiment of the present invention.

FIG. 26 is a process chart illustrating a method of manufacturing a semiconductor device according to a twelfth embodiment of the present invention.

FIG. 27 is a process chart illustrating a method of manufacturing a semiconductor device according to a twelfth embodiment of the present invention.

FIG. 28 is a process chart illustrating a method of manufacturing a semiconductor device according to a twelfth embodiment of the present invention.

FIG. 29 is a process chart illustrating a method of manufacturing a semiconductor device according to a twelfth embodiment of the present invention.

FIG. 30 is a process chart illustrating a method of manufacturing a semiconductor device according to a twelfth embodiment of the present invention.

FIG. 31 is a process chart illustrating a method of manufacturing a semiconductor device according to a thirteenth embodiment of the present invention.

FIG. 32 is a process chart illustrating a method of manufacturing a semiconductor device according to a thirteenth embodiment of the present invention.

FIG. 33 is a process chart illustrating a method of manufacturing a semiconductor device according to a thirteenth embodiment of the present invention.

FIG. 34 is a process chart illustrating a method for manufacturing a semiconductor device according to a thirteenth embodiment of the present invention.

FIG. 35 is a process diagram illustrating a method of manufacturing a semiconductor device according to a thirteenth embodiment of the present invention.

FIG. 36 is a process chart illustrating the method of manufacturing the semiconductor device according to the thirteenth embodiment of the present invention.

FIG. 37 is a process chart illustrating a method of manufacturing a semiconductor device according to a fourteenth embodiment of the present invention.

FIG. 38 is a process diagram illustrating a method for manufacturing a semiconductor device according to a fourteenth embodiment of the present invention.

FIG. 39 is a process chart illustrating the method of manufacturing the semiconductor device according to the fourteenth embodiment of the present invention.

FIG. 40 is a process chart illustrating a method of manufacturing a semiconductor device according to a fourteenth embodiment of the present invention.

FIG. 41 is a process chart illustrating a method of manufacturing a semiconductor device according to a fourteenth embodiment of the present invention.

FIG. 42 is a process chart illustrating a method of manufacturing a semiconductor device according to a fourteenth embodiment of the present invention;

FIG. 43 is a cross-sectional view illustrating a device structure of a conventional semiconductor device.

[Explanation of symbols]

10, 20, 30, 40, 70, 80, 90, 100 ...
The semiconductor substrates 11, 21, 31, 41, 71, 81, 91, 101 ...
Gate electrodes 12, 22, 32, 42, 72, 82, 92, 102 ...
Insulating films 73, 83, 93, 103 ... air gap 1101 ... gate electrode 1102 ... protective film 1103 ... semiconductor substrate 1104, 1105 ... insulating film 1106 ... air gap

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yoichi Makino F-term (reference) 5F102 FA00 GB01 GC01 GD01 GJ05 GR04 GR09 GR11 GS02 GS04 GS07 GS09 GT03 5-7-1 Shiba, Minato-ku, Tokyo GV01 GV05 HC15 HC18

Claims (17)

[Claims] 1. A semiconductor device for avoiding a decrease in yield when forming a fine gate electrode and improving high-frequency characteristics at the same time, wherein a T-shaped gate electrode having a reduced gate resistance is held by an insulating film material. A semiconductor device having a gate support pattern, wherein a portion supporting the gate electrode and a portion not supporting the gate electrode are configured to exist in a gate width direction of the gate electrode. 2. A portion supporting the gate electrode and a portion not supporting the gate electrode in a gate width direction both on a source electrode side of the gate electrode and on a drain electrode side of the gate electrode. 2. The device according to claim 1, wherein the gate support position on the drain electrode side and the gate support position on the source electrode side of the gate electrode exist symmetrically about the gate electrode as a center axis. Semiconductor device. 3. A part supporting the gate electrode and a part not supporting the gate electrode in a gate width direction on the source electrode side of the gate electrode, and the gate support part on the drain electrode side of the gate electrode. 2. The semiconductor device according to claim 1, wherein the pattern is configured so as to exist without a break in the gate width direction. 4. On the drain electrode side of the gate electrode,
There is a portion supporting the gate electrode and a portion not supporting the gate electrode in a gate width direction, and on the source electrode side of the gate electrode, the gate support pattern is configured so as to exist continuously in the gate width direction. The semiconductor device according to claim 1, wherein 5. A portion that supports the gate electrode in a gate width direction and a portion that does not support the gate electrode both on the source electrode side of the gate electrode and on the drain electrode side of the gate electrode. 2. The device according to claim 1, wherein the gate support position on the drain electrode side and the gate support position on the source electrode side of the gate electrode exist asymmetrically about the gate electrode as a center axis. 3. Semiconductor device. 6. The semiconductor device according to claim 1, wherein the gate electrode is held by an insulating film having a gap at least in a portion in contact with a foot portion of the gate electrode and a substrate. 7. A structure in which the gate electrode is held by an insulating film having a gap at least in a portion in contact with a foot portion of the gate electrode and a substrate, and a structure in which the insulating film does not exist to hold the gate electrode. The semiconductor device according to claim 1, wherein: 8. The semiconductor device according to claim 1, wherein the holding pattern of the gate electrode includes an insulating film having a relative dielectric constant of about 3 to about 1. 9. A ratio of the area of the insulating film remaining to support the gate electrode to the area above the gate,
2. The semiconductor device according to claim 1, wherein the semiconductor device is configured to be set to be larger than 0 and equal to or smaller than 0.75. 10. A method of manufacturing a semiconductor device, which achieves both a reduction in yield when forming a fine gate electrode and an improvement in high-frequency characteristics, wherein a gate electrode having a reduced T-shaped gate electrode is made of an insulating film material. A method for manufacturing a semiconductor device, comprising: forming a gate supporting pattern to be held; and forming a portion supporting the gate electrode and a portion not supporting the gate electrode in a gate width direction of the gate electrode. 11. A step of forming a portion supporting the gate electrode and a portion not supporting the gate electrode in a gate width direction on both the source electrode side of the gate electrode and the drain electrode side of the gate electrode; 11. The semiconductor device according to claim 10, further comprising a step of forming a gate supporting position on the drain electrode side of the electrode and a supporting position on the source electrode side of the gate electrode symmetrically with respect to the gate electrode as a center axis. Production method. 12. A step of forming a portion supporting the gate electrode in the gate width direction and a portion not supporting the gate electrode on the source electrode side of the gate electrode, wherein the gate support pattern is formed without a break in the gate width direction. The method according to claim 10, further comprising a step of forming the gate electrode on the drain electrode side. 13. A step of forming a portion supporting the gate electrode in a gate width direction and a portion not supporting the gate electrode on a drain electrode side of the gate electrode; and forming the gate support pattern without a break in the gate width direction. The method according to claim 10, further comprising a step of forming the gate electrode on the source electrode side. 14. A step of forming a portion supporting the gate electrode and a portion not supporting the gate electrode in a gate width direction on both the source electrode side of the gate electrode and the drain electrode side of the gate electrode; 11. The semiconductor device according to claim 10, further comprising: asymmetrically forming a gate support position on the drain electrode side of the electrode and a support position on the source electrode side of the gate electrode with the gate electrode as a center axis. Production method. 15. The method of manufacturing a semiconductor device according to claim 10, further comprising a step of holding the gate electrode by an insulating film having a gap at least in a portion in contact with a foot portion of the gate electrode and a substrate. 16. The method according to claim 10, further comprising the step of forming the holding pattern of the gate electrode using an insulating film having a relative dielectric constant of about 3 to about 1. 17. The method according to claim 17, further comprising the step of forming an insulating film remaining to support the gate electrode so that a ratio of the insulating film to the gate upper area is larger than 0 and equal to or smaller than 0.75. Item 11. The method for manufacturing a semiconductor device according to item 10.