TW575943B - Floating gate oxide formation method of flash memory - Google Patents

Abstract

A floating gate oxide formation method of flash memory comprises the following steps: first, forming a gate oxide on a semiconductor substrate and a doped poly-silicon layer on the gate oxide; second, forming an oxide layer on the doped poly-silicon layer and then forming a nitride layer on the oxide layer; third, removing the nitride layer of the part that is used to define a floating gate and expose a part of the oxide layer; fourth, using the nitride layer as a hard mask to wetly etch the oxide layer and remove the oxide layer that is not covered by the nitride layer and a part of oxide layer that is beneath the nitride layer, wherein a part of the doped poly-silicon layer is exposed; and finally oxidizing the doped poly-silicon layer to form a floating gate oxide layer on the exposed doped poly-silicon layer.

Description

575943 V. Description of the invention 领域 Field of the invention: The present invention relates to a method for forming a floating gate oxide of a flash memory (f 1 ashmem 0ry), and particularly to a method for improving flash memory. Method for forming floating gate oxide layer of flash memory with forward tunneling voltage (FTV) performance. Background of the Invention: δ-th thinking is generally divided into two types: volatile memory (v 〇 1 a ^ 丨 1 emem 〇ry) and non-volatile sense (non-volatile memory), including non-volatile memory The characteristic is that the stored data can be retained for a long time when the power is turned off. Common non-volatile memory mainly includes read-only memory (ROM), programmable read-only memory (pROM), erasable programmable read-only memory (EPROM), and electronically erasable programmable read-only memory Memory (EEpROM) and flash memory. Forward voltage and fast flashing can erase programmable read-only memory

A kind of split gate (SPLIT-GATED) non-volatile memory takes electrical parameters. Among them, the shape of the floating gate oxide layer (nοating ga = 〇xlde) is the main factor that determines the performance of the forward breakdown voltage. I: In the process of flash memory system of ί, since the edge of the floating layer formed by it does not have sharp corners, it is related to the subsequent processes.

575943

The distance between the control gate and the control gate cannot be reduced. In other words, the traditional voltage value is used to achieve that the control gate formed by the control gate is lowered at the floating gate. Switching to a lower forward tunnel gate or smaller, so the flash memory junction conduction electrons required for occasional transfer from the floating site to the floating gate cannot make the forward current tunnel voltage structure impossible. The purpose of moving a gate to a control place.

For the method of forming the floating gate of the traditional flash memory, please refer to FIG. 1 as shown in FIG. 1A and FIG. 1A. An interlayer ㈣ layer is formed on the material conductor substrate 10 in sequence. 2. A doped polycrystalline silicon layer is formed. Layer 丨 6. Then, a part of the nitrided layer 16 located at the gate of Qinyang is removed to expose a part of the doped polycrystalline silicon layer. Next, referring to FIG. 1 β, the doped polycrystalline silicon layer 4 is oxidized to form a polycrystalline silicon oxide layer (a so-called floating gate oxide layer) 18 on the exposed part of the doped polycrystalline silicon layer 14. Next, referring to FIG. 1c, the nitrided layer 16 is removed, and then the floating gate oxide layer 8 is used as a mask, and a part of the doped polycrystalline silicon layer 14 is removed to define the floating gate 14a. It is worth noting here that if the edge of the floating gate oxide layer 8 shown in FIG. 1C can have a sharper

"Big angle" is the shortest distance between the control gate and the control gate formed by the subsequent process, which can reduce the forward voltage required for the conduction electrons to transmit between the floating gate and the control gate. Drop even lower. In order to explain the relationship between the edge sharpness of the floating gate oxide layer 18 and the forward breakdown voltage performance, please refer to FIG. 2, which is a conventional flash memory formed by the subsequent process following FIG. Schematic cross-section. As shown in Figure 2, the floating gate 1 4 a and the control gate 2 3 are separated by a tunnel.

Page 5 575943 5. Description of the invention (3) Emulsifying layer (tunneling oxide layer) 22, and it can be seen from the figure that 'if the edge of the floating gate oxide layer 18 can have sharper corners, it will be floating. The smaller the minimum distance of the tunneling oxide layer 22 for the conduction electrons transmitted between the gate 14a and the control gate 23, the lower the required forward voltage can be lowered. Therefore, in order to obtain better forward voltage performance, the edges of the floating gate oxide layer must have sharp corners as much as possible. Therefore, how to propose a new process to enable the edges of the floating gate oxide layer to , It seems quite important. The invention has a much sharper purpose and summary: The purpose of the present invention is to provide a flash memory formation method I to improve the flash forward voltage of the flash memory :: layer layer: clearly provides a A method for flash memory, which includes at least the following steps: Formation of a pallidation layer to form a gate oxide layer on a half of the conductive layer: on the polar oxide layer; forming an oxide layer; doped poly "doped polycrystalline stone: Formation layer on the oxide layer; removal on the desired layer ;;: layer; forming a layer to expose a part of the oxide layer; "nitriding layer is the rest; 3 part nitriding_ X dry curtain, wet etching 575943

4. Description of the invention (4) m: "Partial oxide layer" and partially doped polycrystalline silicon layer is exposed, and the "heteropolycrystalline silicon layer" is formed to form a floating gate oxide layer over the exposed area. l Zaxi Sweet Silicon Oxide: 正 Positive; 去 Remove part of the oxide layer that is not covered by the aging layer and located at 85 where the above-mentioned method of forming the oxide layer includes thermal oxidation or chemical vapor phase = doped polycrystalline silicon The formation method includes low pressure chemical vapor deposition (LPCVD). In addition, the method for forming the above-mentioned nitrided layer includes a plasma CVD method (PECVD). The etchant used in the wet etching method includes hydrofluoric acid, in which the nitrogen etch used in the wet etching method is etched by nitrogen. Fluoric acid, its concentration is about one percent, and its execution time is about ',,,,,,,,,,,,,,,,,,,,,, and Detailed description of the invention:

The present invention is mainly to provide a method for forming a floating gate oxide layer that can improve the flashover constant flashover voltage performance. Today, a flash memory according to an embodiment of the present invention shown in FIGS. The formation method of the floating gate is used to explain that the floating gate oxide layer formed by using the present invention can surely improve the forward breakdown voltage performance of the flash C memory as follows: As shown in FIG. 3A, a semiconductor substrate is first provided. 30, wherein the semiconductor substrate 30 may be a < 100 > or < 111 >

Page 7 575943

semiconductors. Deficiency in sitting 32, doped polycrystalline conductor substrate 3. A gate oxide layer is sequentially formed on top of the conventional micro-density oblique oxide layer 35 and a nitride layer 36. Next, use the part of L = = to remove the floating idle located in the desired definition by the method of f in Figure 3 β, and use Q + to get out of the oxide layer 3 5. Next, please refer to the manufacturing method. Wet etching of the oxide layer 35 using warm · as an etching mask ^ s & s. ,,,, and the like will cause the nitride layer 36 to be doped between 2 and Γ. The underlayer of the oxide layer 35 undergoes a slight undercut (_21 In other words, the part that is not covered by the nitrided layer 36 is oxidized away. The part of the oxide just below the vaporized layer 36 is oxidized =: thus making it located in the nitrided layer. The part directly under layer 36 is doped with a_ ', and will be exposed. Among them, the width W1 of the undercut, as shown in FIG. 3B, is about 20 to 30 angstroms. For details, please refer to FIG. 3C. The doped polycrystalline silicon layer 34 is oxidized, so that the exposed partly doped polycrystalline silicon layer 34 forms a polycrystalline silicon oxide layer (also known as a foreign gate oxide layer) 38. It is worth noting here Compared with the conventional flash 5 memory process, some of the doped polycrystalline silicon layers 3 and 4 exposed in the present invention are located directly under the nitride layer 36 and are in contact with the nitride layer 36. There is a gap between them, so the floating gate oxide layer 38 formed by the present invention is compared with the floating gate oxide layer formed by the traditional flash memory system. The edges can have sharper sharp corners, where the width W2 of the sharp corners is as shown in FIG. 3c, and is widened to about 200 to 250 angstroms. Then, referring to FIG. 3D, wet etching is used. The nitride layer 36 and the oxide layer 35 are sequentially removed, and then the floating gate oxide layer 575943 is removed.

V. Description of the invention (6) 38 is a mask, except for a part of the doped polycrystalline layer 34, to define that the floating gate is lower. 2 & In this way, the edge of the floating gate oxide layer 38 formed by using the present invention has a sharper angle, so the shortest distance between the gate and the gate formed by the subsequent process can be shortened. It is small, which can make the forward voltage required for the conduction of electrons between the floating gate and the control gate drop. According to a preferred embodiment of the present invention, the gate oxide layer 32 or the oxide layer 35 It can be formed by a thermal oxidation method or a chemical vapor deposition method. A method for forming the doped polycrystalline silicon layer 34 includes a low pressure chemical vapor deposition (LPCVD) method. The nitriding method was formed using low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition (PECVD). In addition, the thickness of the nitride layer is about 700 angstroms to 900 angstroms, the thickness of the doped polycrystalline silicon layer 34 is about 900 angstroms to 11,000 angstroms, and the thickness of the oxide layer 35 is about 5 angstroms. Approximately between 25 Angstroms and 35 Angstroms. Also described above are the wet etchants used to remove part of the oxide layer 3 5 before forming the floating gate oxide layer 38, and the wet used to remove the remaining oxide layer 3 5 after forming the floating gate oxide layer 38. The etchant may contain hydrofluoric acid at a concentration of about one percent, and the preferred execution time is about 85 seconds to 95 seconds. In order to explain in more detail the effect of improving forward voltage performance achieved by the present invention, please refer to FIG. 4, which is a schematic cross-sectional view of a flash memory of the present invention formed by performing subsequent processes following FIG. 3D. As shown in Figure 4, there is a tunneling oxide layer 42 between the floating gate 34a and the control gate 43, and it can be seen from the figure that due to 575943 V. Description of Invention (7) Application According to the present invention, the edge of the floating gate oxide layer 38 formed by the parallel gate, # ,,, and the like can have a sharper edge, and the conduction between the floating gate 34a and the control gate 43 is increased. The minimum distance of the tunneling oxide layer 42 of the two IS teeth can be smaller, so the forward tunneling voltage can be lowered. Oxidation; upper: ΐ: the floating gate of the flash memory formed by i f Ming voltage performance 1, /, has sharper corners, so it can improve forward through the invention better! For example, the above is clear, but all other equivalent changes or modifications that do not depart from the present invention are covered by the present invention: all the equivalent changes or modifications * ′ should be regarded as the scope of the patent application, which is equivalent to the scope of protection.

575943 Brief description of the drawings. Figures A ~ C are cross-sectional views of semiconductor wafers, showing the steps of forming a conventional flash memory floating gate. Figure 2 is a conventional flash memory formed by the subsequent process following Figure 1C. Figure 3 is a cross-sectional view of a semiconductor wafer, showing the steps for forming a floating gate of a flash memory according to an embodiment of the present invention; Figure 4 is a subsequent process institute following Figure 3D. A schematic cross-sectional view of the formed flash memory of the present invention. Part numbers: semiconductor substrates 10, 30; gate oxide layers 1 2, 3 2; doped polycrystalline silicon layers 1 4, 3 4; floating gates 14a, 34a; thermal oxide layers 3 5; nitride layers 16, 3 6; floating gate oxide layers 18, 3 8; tunneling oxide layers 22, 42; undercut width W1; sharp corner width W2; control gates 23, 43.

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Claims (1)

575943 ----- No. 91118843 End of the year 7; $ q 6. Application scope 1. A method for forming a floating gate oxide layer of flash memory, which includes at least the following steps: μ million method to form a gate oxide Layer on a semiconductor substrate; forming a floating gate layer on the gate oxide layer; forming an oxide layer on the floating gate layer; forming a hard mask layer on the oxide layer; Define part of the hard mask layer at the floating gate, and part of the oxide layer; exposed, the hard mask layer is the mask, except for the part that is not covered by the hard mask layer. A part of the oxide layer directly below the hard cover curtain layer, and a part of the floating gate layer; and the exposed gate layer is exposed to oxidation so that the exposed part of the floating gate layer is exposed. A floating gate oxide layer is formed on the electrode layer. 2. The method according to item 1 of the scope of patent application, wherein the method for forming the above-mentioned oxide layer includes a thermal oxidation method. 3 L ·, ° The method of applying for item 1 of the patent scope, wherein the method for forming the above oxide layer includes a chemical vapor deposition method. 4: The method according to item 1 of the scope of patent application, wherein the method for forming the floating gate layer includes a low pressure chemical vapor deposition (LPCVD) method. 5. The method of claim 1 in the scope of patent application, wherein the above-mentioned hard cover is formed 575943 ^ SS—91118843 6. Scope of patent application: Amendment Including plasma enhanced chemical vapor deposition (pECVD). 6 The method of hard order is as described in the first item of the patent scope of the tomb Vt ', wherein the above-mentioned removal of the adjacent 4: part of the oxide layer and the one directly under the hard cover curtain layer. For this emulsified layer, a wet etching method is used. 7. As described in the patent application scope item 6, let ^ make the moment concentration of the agent is about;: of! Wet method described the implementation of the wet remaining moment 8 time, such as: 2 = around item 7 The method is 9 in the above; if the Fangben Ganshi system of the first patent application scope is a doped polycrystalline silicon layer. A method, wherein the above-mentioned floating gate layer 10 · As in the scope of the patent application] is a nitride layer. The method, wherein the above-mentioned hard cover curtain layer 11. As described in the first patent application, there is a method of being covered by the hard cover curtain layer, wherein the above is removed. . The width of the oxide layer is about 20 to 30. 12. A flash memory case + the following steps: · The method of forming the heart / pre-brake, this method includes at least page 13 575943 Case No. Q111RRW 6. Application scope Modified to form a gate oxide layer on a semiconductor substrate; forming a floating gate layer on the gate oxide layer; forming an oxide layer on the floating gate layer; forming a hard cover curtain layer on the On the oxide layer; the part of the oxide layer located at the place where the floating gate is to be defined; the more excellent layer M is exposed; the curtain layer 47 is covered; and the parts not covered by the hard curtain layer are removed Layer and the floating gate layer exposed on the hard cover curtain layer h; ... lice layer, and = the floating idler layer, so that the exposed part forms a floating gate oxide layer Removing the hard mask layer on the j-bit layer; removing the oxide layer; and using the floating gate oxide layer as a mask, removing the exposed floating layer 'to define a floating gate. 13. The method according to item 12 of the patent application scope, wherein the above-mentioned method for forming reed oxide includes a thermal oxidation method. 14. The method according to item 12 of the patent application range, wherein the method for forming the above-mentioned oxide layer includes a chemical vapor deposition method. 15: The method according to item 12 of the scope of patent application, wherein the method for forming the floating gate layer includes a low pressure chemical vapor deposition (LPCVD) method. 575943 ^ "Nongliang" JJJ8843 ^ Patent application scope Ά_ ± Correction j g • The method described in item 12 of the patent scope, wherein the hard mask formation method includes plasma enhanced chemical vapor deposition (PECVD). 1 Mask 7. The method of item 12 of the curtain range, except that the oxidized sound that is not part of the hard cover is removed: ΐ: and the plane ^ κ noise located directly under the hard cover curtain layer, using the wet etching method. 18 · As the Fang Zhigan of the 17th scope of the application for the patent, the etchant used is a hydrofluoric acid with a concentration of about 2 used by the wet etching method. The application of the wet incision as described in item 18 of the scope of patent application, the time is about 85 to 95 seconds. You /, China The above floating gate is long ::: Miscellaneous: Second method ... 21. If the scope of patent application is No. 12 > Ancient & is a nitrided layer. The method of which the above-mentioned hard cover curtain layer 2 2 · As in item 12 of the scope of patent application, there is a part covered by the hard cover curtain layer ^ method, wherein the above is removed. 77 The width of this oxide layer is about 20 to 30. Page 15 Case No. 91118843 VI. Patent application scope 2 3. A flash memory cell structure at least includes: a gate oxide layer, a floating gate electrode, located above a semiconductor substrate, and separated from the semiconductor substrate; The floating gate oxide layer is located above the floating gate electrode, and ^ both ends of the emulsified layer have sharp corners; χ floating gate electrode is an insulating dielectric layer, which is located on the outer surface of the floating gate oxide layer substrate. And "the control gate of the semiconductor is located on the upper surface of the insulating dielectric layer." 24. The insulating dielectric layer described in the flash memory tire of item 23 of the patent application is a tunneling oxide layer. The width of the sharp corner described in the flash memory cell & as described in item 23 of the patent application range is about 2. 〇 to 25. Aye. & structure, in which the upper body has a body shape and a cover • A floating gate oxygen containing a sharp angle at both ends, including: a layer of flash memory gate oxide floating layer formed on a semiconductor substrate; An electrode layer is formed on the gate oxide layer, and a hard layer is formed on the floating gate layer; The I w layer is formed on the oxide layer, and the part of the large part is removed Exposed =; =: The fixed curtain layer system is used as the cover twilight, and part of the + chemical layer is removed from the "F sentence dry fragrance essence field" / there is the gasification layer and the hard cover on the hard curtain w Gastric shield Page 16 77 The gas 575943 _ Case No. 91118843 _ month and month __ VI. Patent application scope layer, and exposed part of the floating gate layer; and a floating gate oxidation with sharp corners at both ends The layer is formed by oxidizing a part of the floating gate layer exposed by oxidation. 27. For example, the flash memory in the scope of the patent application No. 26, wherein the width of the sharp angle is about 200 to 250 Angstroms. 28. The flash memory of item 26 of the patent application, wherein the floating gate layer is a doped polycrystalline silicon layer. 2 9. If the flash memory of item 26 of the patent application is applied, wherein the hard mask layer is a nitride layer. 30. The flash memory according to item 26 of the patent application, wherein the width of the oxide layer removed in the part not covered by the hard cover layer is about 20 to 30 angstroms. 31. A semiconductor device including an oxide layer with sharp corners at both ends, comprising: a first oxide layer formed on a semiconductor substrate; a gate layer formed on the first oxide layer; a second oxide Layer formed on the gate layer; a hard mask layer formed on the second oxide layer, wherein the hard mask layer is removed at a portion where the gate is to be defined to expose a portion of the gate layer Second oxidation Page 17 575943 _ Case No. 91118843 _ Month and Day __ VI. Patent application layer, and the hard cover layer is used as the cover, by removing the part that is not covered by the hard cover _ layer, the second An oxide layer and a portion of the second oxide layer directly under the hard mask layer, and a portion of the gate layer is exposed; and a third oxide layer with sharp corners at both ends, The exposed part of the gate layer is formed. 32. The semiconductor device according to item 31 of the application, wherein the width of the above-mentioned tip and corner is about 200 to 250 angstroms. Page 18