JP2007317735A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a gate electrode can be completely embedded, and to provide a manufacturing method of the semiconductor device. <P>SOLUTION: The semiconductor device is provided with a gate electrode 2 formed on a semiconductor substrate 1, the source/drain electrodes 3 provided on the semiconductor substrate 1 on both sides of the gate electrode 2, and an embedding material 4 filled between the source/drain electrodes 3 for embedding the gate electrode 2. In this semiconductor device, height up to the upper end, from the front surface of the semiconductor substrate 1 of each source/drain electrode 3 is set higher than the height, up to the upper end from the front surface of the semiconductor substrate 1 of the gate electrode 2. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a gate electrode and a source / drain electrode are embedded with a filling material, and a manufacturing method thereof.

Conventional semiconductor devices such as low noise GaAs high electron mobility transistors (HEMT)
As shown in the cross-sectional view of FIG. 10, the Mobility Transistor) is provided with a T-type gate electrode 2 on a semiconductor substrate 1, and a source / drain electrode 3 is formed on both sides thereof so as to be lower than the height of the gate electrode 2. All the electrodes are embedded with the embedding material 4. (For example, refer to Patent Document 1).

JP-A-3-85731

  The conventional semiconductor device is configured as described above, and the height of the T-type gate electrode 2 is usually more than twice the height of the source / drain electrodes 3 located on both sides thereof. In the case of embedding with a low-k material such as MSQ (Methyl silsesquioxane) for improving high frequency characteristics of HEMT, for example, the following problems have occurred.

  That is, if the embedding material 4 is thickly applied to completely embed the gate electrode 2, the coating thickness of the embedding material 4 on the source / drain electrode 3 is increased, so that contact hole openings formed on the source / drain electrode 3 are opened. Had become difficult.

  Further, when the embedding material 4 is thinly applied to facilitate the opening of the contact hole, the embedding of each electrode is incomplete, for example, the head of the gate electrode 2 is exposed from the embedding material 4 as shown in FIG. It was.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a semiconductor device in which a gate electrode can be completely embedded and a method for manufacturing the same.

  A semiconductor device according to the present invention is applied between a gate electrode formed on a semiconductor substrate, a source / drain electrode disposed on the semiconductor substrate on both sides of the gate electrode, and the source / drain electrodes. In a semiconductor device including a filling material for embedding a gate electrode, the height of each source / drain electrode from the surface of the semiconductor substrate to the upper end is made higher than the height of the gate electrode from the surface of the semiconductor substrate to the upper end. Is.

The semiconductor device according to the present invention is configured as described above, and the height of the upper end as the structure of the source / drain electrode located on both sides of the gate electrode is formed higher than the height of the upper end of the gate electrode. As a result of the portion sandwiched between the two source / drain electrodes functioning as a reservoir for the filling material, the gate electrode can be completely buried.
In addition, since the thickness of the filling material on the upper portion of the source / drain electrode is reduced, the opening of the contact hole is facilitated.

Embodiment 1 FIG.
Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing the configuration of the first embodiment, and FIG. 2 is a cross-sectional view showing the manufacturing method of the first embodiment in the order of steps.
In these drawings, the same or corresponding parts as those in FIG. 10 are denoted by the same reference numerals.

  As shown in FIG. 1, the semiconductor device according to the first embodiment is provided with a T-type gate electrode 2 on a semiconductor substrate 1, and a source / drain electrode 3 higher than the gate electrode 2 is formed on both sides thereof. In this case, all the electrodes are embedded. That is, the height from the surface of the semiconductor substrate 1 to the upper end of the source / drain electrode 3 is higher than the height from the surface of the semiconductor substrate 1 to the upper end of the gate electrode 2.

A method of manufacturing the semiconductor device having such a configuration will be described with reference to the process diagram of FIG.
First, as shown to (a), the 1st resist pattern 10 is formed on the semiconductor substrate 1, and the opening part 11 is formed in a predetermined position.

  Next, as shown in (b), a second resist pattern 12 is formed on the first resist pattern 10 and an opening for forming a T-type gate electrode 2 at a position corresponding to the opening 11 is formed. Part 13 is formed.

Thereafter, as shown in (c), the T-type gate electrode 2 is formed using the openings 11 and 13 of the first and second resist patterns, and the first and second resist patterns 10 and 12 are removed. To do.
Next, as shown in (d), a third resist pattern 14 is formed on the semiconductor substrate 1 and the gate electrode 2, and openings 15 for the source / drain electrodes 3 are formed on both sides of the gate electrode 2.

  Thereafter, as shown in FIG. 5E, the source / drain electrodes 3 are formed on both sides of the gate electrode 2 using the openings 15. In this case, the height SH from the surface of the semiconductor substrate 1 to the upper end of the source / drain electrode 3 is formed to be higher than the height GH from the surface of the semiconductor substrate 1 to the upper end of the gate electrode 2. It is desirable that SH ≦ 2 × GH and W / SH ≦ 2.

  Next, as shown in (f), a filling material 4 is applied and cured so that the gate electrode 2 and the source / drain electrode 3 are completely buried. Thereafter, a contact hole 16 is formed at a position corresponding to the source / drain electrode 3 of the filling material 4 as shown in (g), and a wiring layer 17 is formed in the contact hole 16 as shown in (h). To do.

  In the compound semiconductor, an AuGe-based material is widely used for the source / drain electrode 3, but in this case, an ohmic alloy process is required. Since the ohmic alloy process has a high temperature of about 380 ° C., it is usually necessary to form the source / drain electrode 3 before forming the gate electrode 2 in order to avoid deterioration of the gate electrode 2. (See the manufacturing method of the second embodiment described later).

On the other hand, when the source / drain electrode 3 is made thick, it becomes difficult to form a lower layer resist pattern for forming the gate electrode 2. Therefore, in the first embodiment, when applied to a source / drain electrode that requires an ohmic alloy process, a high melting point material such as WSi is used for the gate electrode 2 or a non-alloy ohmic electrode is formed. For example, a contact layer (n ⁺ -InGaAs or the like) needs to be formed on the semiconductor substrate side.

  Since the first embodiment is configured as described above, when the filling material 4 is applied, the space between the pair of source / drain electrodes 3 functions as a liquid reservoir, and the head of the gate electrode 2 can be completely buried. it can.

Embodiment 2. FIG.
Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a cross-sectional view showing the configuration of the second embodiment, and FIG. 4 is a cross-sectional view showing the manufacturing method of the second embodiment in the order of steps.
In these drawings, the same or corresponding parts as those in FIG.

  In the semiconductor device according to the second embodiment, as shown in FIG. 3, a T-type gate electrode 2 is provided on a semiconductor substrate 1, normal source / drain electrodes 3 are formed on both sides thereof, and further on the source / drain electrodes 3. The wiring electrodes 5 are stacked so that the height from the surface of the semiconductor substrate 1 to the upper end of the wiring electrode 5 is higher than the height from the surface of the semiconductor substrate 1 to the upper end of the gate electrode 2 so that all the electrodes are embedded by the filling material 4. I have to.

A method of manufacturing the semiconductor device having such a configuration will be described with reference to the process diagram of FIG.
First, as shown in FIG. 2A, a pair of source / drain electrodes 3 is formed on a semiconductor substrate 1 and ohmic alloy is performed at about 380.degree.

Next, as shown in (b), a first resist pattern 10 is formed on each source / drain electrode 3, and an opening 11 is formed between each source / drain electrode 3.
Next, as shown in (c), a second resist pattern 12 is formed on the first resist pattern 10, and an opening for forming the T-type gate electrode 2 at a position corresponding to the opening 11 is formed. Part 13 is formed.

Thereafter, as shown in (d), the T-type gate electrode 2 is formed using the openings 11 and 13 of the first and second resist patterns, and the first and second resist patterns 10 and 12 are removed. To do.
Next, as shown in (e), a third resist pattern 14 is formed on each source / drain electrode 3 and the gate electrode 2, and an opening 15 is formed on each source / drain electrode.

  Thereafter, as shown in (f), the wiring electrode 5 is formed on each source / drain electrode 3 using the opening 15. In this case, the height SH from the surface of the semiconductor substrate 1 to the upper end of the wiring electrode 5 is formed to be higher than the height GH from the surface of the semiconductor substrate 1 to the upper end of the gate electrode 2. It is desirable that SH ≦ 2 × GH and W / SH ≦ 2. The width HW of the wiring electrode 5 is preferably as close as possible to the width SW of the source / drain electrode 3.

  Next, as shown in (g), the filling material 4 is applied and cured so that the gate electrode 2 and each wiring electrode 5 are completely filled. Thereafter, as shown in (h), a contact hole 16 is formed at a position corresponding to each wiring electrode 5 of the filling material 4, and a wiring layer 17 is formed in the contact hole 16 as shown in (i). To do.

  In the second embodiment, the wiring electrode 5 is formed on the normal source / drain electrode 3, and the sum of the height of the source / drain electrode 3 and the wiring electrode 5 is higher than the height of the gate electrode 2. Therefore, as in the first embodiment, when the embedding material 4 is applied, the space between the pair of wiring electrodes 5 functions as a liquid pool, and the head of the gate electrode 2 can be completely embedded.

Embodiment 3 FIG.
Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a cross-sectional view showing the configuration of the third embodiment. In this figure, the same or corresponding parts as those in FIG.

  The semiconductor device according to the third embodiment is a simplified form of the second embodiment, in which a gate electrode 6 is provided on the source / drain electrode 3 instead of the wiring electrode 5 shown in FIG. 3, and the gate electrode 6 is a T-type gate. It is formed simultaneously with the formation of the electrode 2.

  Although the manufacturing process of this semiconductor device is not shown, in FIG. 4C showing the process of the second embodiment, an opening 13 is also formed on the source / drain electrode 3, and in the process of FIG. The gate electrode 6 is also formed on the source / drain electrode 3 simultaneously with the formation of the type gate electrode 2.

  The relationship between the sum SH of the height of the gate electrode 6 and the source / drain electrode 3 and the height GH of the T-type gate electrode 2, the relationship between the width HW of the gate electrode 6 and the width SW of the source / drain electrode 3, etc. Further, the subsequent manufacturing steps are the same as those in (f), (g), (h), and (i) of FIG.

  Since the third embodiment is configured as described above, an effect equivalent to that of the second embodiment can be expected.

Embodiment 4 FIG.
Next, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a cross-sectional view showing the configuration of the fourth embodiment. In this figure, the same or corresponding parts as those in FIG.

  The semiconductor device according to the fourth embodiment is a modification of the second embodiment, in which an insulating film 7 made of SiO or SiN is provided on the source / drain electrode 3 instead of the wiring electrode 5 shown in FIG.

  The manufacturing process of this semiconductor device is substantially the same if the wiring electrode 5 of FIG. In the manufacturing process different from FIG. 4, after the step (h), the insulating film 7 is wet-etched with hydrofluoric acid or the like to form an opening (not shown) reaching the source / drain electrode 3 in the insulating film 7. The process to do is added, and it is the point which leads to the process of (i) after that.

  As the embedding material 4, for example, polyimide or PAE (polyarylene ether), which is an organic low-k material that is not corroded by hydrofluoric acid, can be used.

  Since the fourth embodiment is configured as described above, an effect equivalent to that of the second embodiment can be expected.

Embodiment 5 FIG.
Next, a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a cross-sectional view showing the configuration of the fifth embodiment. In this figure, the same or corresponding parts as those in FIG.

  The semiconductor device according to the fifth embodiment is a modification of the fourth embodiment, in which an organic film 8 such as a resist is laminated on the source / drain electrode 3 instead of the insulating film 7 shown in FIG.

Since the manufacturing process of this semiconductor device is substantially the same manufacturing process if the wiring electrode 5 of FIG. 4 is replaced with an organic film 8 such as a resist, illustration and description thereof are omitted.
The manufacturing process different from FIG. 4 is the same as in the fourth embodiment, after the step (h), the organic film 8 is wet-etched with an organic solvent such as a resist stripping solution so that the source / drain electrodes are formed in the organic film 8. A step of forming an opening (not shown) reaching 3 is added, and then the step (i) is reached.

  As the embedding material 4, for example, HSQ (Hydrogen Silsesquioxane) which is an inorganic low-k material that is not corroded by an organic solvent can be used.

  Since the fifth embodiment is configured as described above, an effect equivalent to that of the second embodiment can be expected.

Embodiment 6 FIG.
Next, a sixth embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a sectional view showing the configuration of the sixth embodiment, and FIG. 9 is a sectional view showing the manufacturing method of the sixth embodiment in the order of steps.
In these drawings, the same or corresponding parts as those in FIG.

  In the semiconductor device according to the sixth embodiment, as shown in FIG. 8, after a lower gate electrode 9 having the same height as the source / drain electrode 3 is formed, a filling material 4A is applied between the source / drain electrode 3 and cured. The source / drain electrodes 3 and the lower gate electrode 9 are cued by etch back, and then the wiring electrodes 5 having the same height are formed on the source / drain electrodes 3 and the lower gate electrode 9, respectively.

A manufacturing process of the semiconductor device having such a configuration will be described with reference to the process diagram of FIG.
First, as shown in (a), a pair of source / drain electrodes 3 is formed on a semiconductor substrate 1, and ohmic alloy is performed at about 380 ° C.

Next, as shown in (b), a first resist pattern 10 is formed on each source / drain electrode 3, and an opening 11 is formed between each source / drain electrode 3.
Next, as shown in FIG. 3C, the lower gate electrode 9 having the same height as the source / drain electrode 3 is formed by the opening 11, and the first resist pattern 10 is removed.

  Thereafter, as shown in (d), the first filling material 4A is applied and cured so as to cover each source / drain electrode 3 and the lower gate electrode 9. Next, as shown in (e), the first burying material 4A is etched back, and cueing is performed so that the source / drain electrodes 3 and the lower gate electrode 9 are exposed from the surface of the first burying material 4A.

  Subsequently, as shown in (f), a second resist pattern 14 is formed on each source / drain electrode 3 and the lower gate electrode 9, and an opening is formed at a position corresponding to each source / drain electrode 3 and the lower gate electrode 9. 15 is formed.

Next, as shown in (g), the wiring electrodes 5 having the same height are formed on the source / drain electrodes 3 and the lower gate electrode 9 through the openings 15, and the second resist pattern 14 is removed.
Thereafter, as shown in (h), the second embedding material 4B is applied and cured so as to cover each wiring electrode 5. Since each wiring electrode 5 has the same height, it is completely embedded.

  Next, as shown in (i), a contact hole 16 is formed at a position corresponding to the wiring electrode 5 on each source / drain electrode 3 of the second filling material 4B, and as shown in (j), the contact hole. A wiring layer 17 is formed on 16 to complete. In the above description, the first burying material 4A and the second burying material 4B are preferably the same material, but they need not be the same.

  The sixth embodiment is configured as described above, and each wiring electrode can be completely embedded by the etch back with respect to the first filling material and the second filling material applied thereon.

It is sectional drawing which shows the structure of Embodiment 1 of this invention. FIG. 5 is a cross-sectional view showing the manufacturing method of Embodiment 1 in the order of steps. It is sectional drawing which shows the structure of Embodiment 2 of this invention. It is sectional drawing which showed the manufacturing method of Embodiment 2 to process order. It is sectional drawing which shows the structure of Embodiment 3 of this invention. It is sectional drawing which shows the structure of Embodiment 4 of this invention. It is sectional drawing which shows the structure of Embodiment 5 of this invention. It is sectional drawing which shows the structure of Embodiment 6 of this invention. It is sectional drawing which showed the manufacturing method of Embodiment 6 in order of the process. It is sectional drawing which shows the structure and problem of the conventional semiconductor device.

Explanation of symbols

1 semiconductor substrate, 2 gate electrode, 3 source / drain electrode, 4 filling material,
5 Wiring electrode, 6 Gate electrode, 7 Insulating film, 8 Organic film, 9 Lower gate electrode, 10 First resist pattern, 11 Opening, 12 Second resist pattern, 13 Opening, 14 Third resist pattern, 15 openings, 16 contact holes, 17 wiring layers.

Claims (12)

  A gate electrode formed on the semiconductor substrate; a source / drain electrode disposed on the semiconductor substrate on both sides of the gate electrode; and a burying material applied between the source / drain electrodes to embed the gate electrode. A semiconductor device comprising: a height of each source / drain electrode from a surface of the semiconductor substrate to an upper end higher than a height of the gate electrode from the surface of the semiconductor substrate to the upper end.   A gate electrode formed on the semiconductor substrate; a source / drain electrode disposed on the semiconductor substrate on both sides of the gate electrode; and a burying material applied between the source / drain electrodes to embed the gate electrode. In the semiconductor device, a wiring electrode is formed on the upper surface of each of the source / drain electrodes, and a height from the surface of the semiconductor substrate to the upper end of the wiring electrode is from the surface of the semiconductor substrate to the upper end of the gate electrode. A semiconductor device characterized by being higher than the height.   A gate electrode formed on the semiconductor substrate; a source / drain electrode disposed on the semiconductor substrate on both sides of the gate electrode; and a burying material applied between the source / drain electrodes to embed the gate electrode. In the semiconductor device, a gate electrode is formed on the upper surface of each source / drain electrode, and the surface of the semiconductor substrate is higher than the height from the surface of the semiconductor substrate to the upper end of the gate electrode located between the source / drain electrodes. A height of the gate electrode formed on each of the source / drain electrodes is increased.   A gate electrode formed on the semiconductor substrate; a source / drain electrode disposed on the semiconductor substrate on both sides of the gate electrode; and a burying material applied between the source / drain electrodes to embed the gate electrode. In the semiconductor device, an insulating layer is stacked on the upper surface of each source / drain electrode, and a height from the surface of the semiconductor substrate to the upper end of the insulating layer is from the surface of the semiconductor substrate to the upper end of the gate electrode. A semiconductor device characterized by being higher than the height.   A gate electrode formed on the semiconductor substrate; a source / drain electrode disposed on the semiconductor substrate on both sides of the gate electrode; and a burying material applied between the source / drain electrodes to embed the gate electrode. In the semiconductor device provided, an organic film is laminated on the upper surface of each source / drain electrode, and a height from the surface of the semiconductor substrate to the upper end of the organic film is from the surface of the semiconductor substrate to the upper end of the gate electrode. A semiconductor device characterized by being higher than the height.   A pair of source / drain electrodes formed on a semiconductor substrate; a lower gate electrode formed on the semiconductor substrate between the source / drain electrodes and leveled with the source / drain electrodes; A first filling material applied between the electrodes, and wiring electrodes having the same height are provided on each of the source / drain electrodes and the lower gate electrode, and each wiring electrode is buried with a second filling material. A semiconductor device characterized by that.   Forming a first resist pattern on the semiconductor substrate and forming an opening at a predetermined position; forming a second resist pattern on the first resist pattern; and opening at a position corresponding to the opening. Forming a portion, forming a gate electrode through the openings of the first and second resist patterns, and removing the first and second resist patterns, on the semiconductor substrate and on the gate electrode Forming a third resist pattern on the gate electrode and forming openings on both sides of the gate electrode; and the height from the surface of the semiconductor substrate to the upper end of the gate electrode by the opening of the third resist pattern. Forming a source / drain electrode higher than the height from the surface of the semiconductor substrate to the upper end; and filling the gate electrode and each source / drain electrode with the half A semiconductor comprising: a step of applying and filling a filling material on a body substrate; a step of forming a contact hole at a position corresponding to each of the source and drain electrodes of the filling material; and a step of forming a wiring layer in the contact hole Device manufacturing method.   Forming a pair of source / drain electrodes on a semiconductor substrate and performing an ohmic alloy; forming a first resist pattern on the semiconductor substrate and the source / drain electrodes; and opening portions between the source / drain electrodes. Forming a second resist pattern on the first resist pattern, forming an opening at a position corresponding to the opening, and opening of the first and second resist patterns Forming a gate electrode by a portion and removing the first and second resist patterns; forming a third resist pattern on each of the source / drain electrodes and the gate electrode; and Forming a wiring electrode on each of the source / drain electrodes by the step of forming an opening in the first resist pattern and the opening of the third resist pattern; A step of making the height from the surface of the semiconductor substrate to the upper end of the line electrode higher than the height from the surface of the semiconductor substrate to the upper end of the gate electrode, and embedding the gate electrode and each wiring electrode A semiconductor including a step of applying and curing a filling material on a semiconductor substrate, a step of forming a contact hole at a position corresponding to each wiring electrode of the filling material, and a step of forming a wiring layer in each contact hole Device manufacturing method.   Forming a pair of source / drain electrodes on the semiconductor substrate and performing ohmic alloy; forming a first resist pattern on the semiconductor substrate and each source / drain electrode; and opening an opening between the source / drain electrodes. Forming a second resist pattern on the first resist pattern, forming openings at positions corresponding to the openings and the source / drain electrodes, and the first and second steps. A gate electrode is formed on and between each source / drain electrode by the opening of the resist pattern, and the height of the gate electrode located between each source / drain electrode from the surface of the semiconductor substrate to the upper end thereof The height from the surface of the semiconductor substrate to the upper end of the gate electrode formed on each source / drain electrode is increased. And a step of removing the first and second resist patterns and a filling material on the semiconductor substrate so as to bury the gate electrode on each source / drain electrode and the gate electrode located between the source / drain electrodes. Applying and curing, forming a contact hole in the filling material at a position corresponding to the gate electrode formed on each source / drain electrode, and forming a wiring layer in each contact hole. A method for manufacturing a semiconductor device.   Forming a pair of source / drain electrodes on a semiconductor substrate and performing an ohmic alloy; forming a first resist pattern on the semiconductor substrate and the source / drain electrodes; and opening portions between the source / drain electrodes. Forming a second resist pattern on the first resist pattern, forming an opening at a position corresponding to the opening, and opening of the first and second resist patterns Forming a gate electrode by a portion and removing the first and second resist patterns; forming a third resist pattern on each of the source / drain electrodes and the gate electrode; and And forming an opening on the source / drain electrodes by the opening of the third resist pattern and forming the openings. A step of making the height from the surface of the semiconductor substrate to the upper end of the layer higher than the height of the gate electrode from the surface of the semiconductor substrate to the upper end, and the semiconductor to embed the gate electrode and each insulating layer A step of applying and curing an embedding material on the substrate, a step of forming an opening at a position corresponding to each of the insulating layers of the embedding material, and etching the insulating layer from the opening of the embedding material. A method for manufacturing a semiconductor device, comprising: forming a contact hole reaching each source / drain electrode; and forming a wiring layer in each contact hole.   Forming a pair of source / drain electrodes on a semiconductor substrate and performing an ohmic alloy; forming a first resist pattern on the semiconductor substrate and the source / drain electrodes; and opening portions between the source / drain electrodes. Forming a second resist pattern on the first resist pattern, forming an opening at a position corresponding to the opening, and opening of the first and second resist patterns Forming a gate electrode by a portion and removing the first and second resist patterns; forming a third resist pattern on each of the source / drain electrodes and the gate electrode; and And forming an opening on the source / drain electrodes by the opening of the third resist pattern and forming the opening. A step of making the height from the surface of the semiconductor substrate to the upper end of the film higher than the height of the gate electrode from the surface of the semiconductor substrate to the upper end; and the semiconductor to embed the gate electrode and each organic film A step of applying and curing a filling material on the substrate; a step of forming an opening at a position corresponding to the organic film of the filling material; and an opening of the filling material by etching the organic film with an organic solvent. A method for manufacturing a semiconductor device, comprising: forming a contact hole from each of the contact drain electrodes to the source drain electrode; and forming a wiring layer in each contact hole. Forming a pair of source / drain electrodes on a semiconductor substrate and performing an ohmic alloy; forming a first resist pattern on the semiconductor substrate and the source / drain electrodes; and opening portions between the source / drain electrodes. Forming a lower gate electrode having the same height as each of the source / drain electrodes through the opening, removing the first resist pattern, and covering the source / drain electrodes and the lower gate electrode. Applying and curing a first burying material, etching back the first burying material to cue each source / drain electrode and lower gate electrode, and above each source / drain electrode and lower gate A second resist pattern is formed on the electrodes and opened at positions corresponding to the source / drain electrodes and the lower gate electrode. Forming a portion, forming a wiring electrode of the same height on each of the source / drain electrodes and the lower gate electrode by the opening, removing the second resist pattern, and covering each of the wiring electrodes A step of applying and curing the second filling material, a step of forming a contact hole at a position corresponding to the wiring electrode on each source / drain electrode of the second filling material, and a wiring layer in each contact hole Forming a semiconductor device.

Images