JP2001176827A - Semiconductor wafer having high planarity, and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain as a whole a high polishing uniformity by chemical mechanical polishing(CMP) in a semiconductor wafer having high planarity, and its manufacturing method. SOLUTION: A surface S of a semiconductor wafer W2, having a high planarity, is polished by a polishing cloth. Its surface S is made flat in the state of its rear surface R being sucked by vacuum by a flat plane H. Also, in the wavinesses of its surface S generated in the state of its rear surface R which is not sucked vacuously by the flat plane H, at least the wavinesses whose periods are smaller than the period capable of being followed by the polishing cloth and the wavinesses whose periods are not smaller than 0.2 mm, are removed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-flatness semiconductor wafer suitable for polishing a mirror-finished wafer surface and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a process of manufacturing a device on a surface of a semiconductor wafer having a mirror-polished surface, an oxide film or the like is formed on the surface, and then the oxide film or the like is removed.
A process of polishing and flattening by MP (Chemical Mechanical Polishing) technology is used. This planarization is an important step required in response to a shallower depth of focus with miniaturization of optical lithography, and is particularly necessary in multi-layer wiring.

In the flattening step by CMP, a polishing cloth is brought into contact with the surface of a mirror-finished wafer and mechanochemical polishing is performed while supplying an alkaline polishing liquid. A processed mirror wafer is used. As shown in FIG. 5 (a), a wafer W0 having a flat surface S side and large and small undulations on the rear surface R was used as the mirror surface wafer. Is the uniformity of the thickness distribution of the wafer, and as shown in FIG. 5B, when the wafer W0 is vacuum-adsorbed on the back surface R side by an exposure apparatus in a photolithography process, the undulation on the back surface R side is increased. There is a problem that the image is transferred to the S side and undulation occurs on the surface, and the exposure accuracy is reduced.

In recent years, as shown in FIG. 6A, large and small undulations are present on the front surface S and the rear surface R, respectively.
That is, a high flatness wafer W1 processed to a high flatness has been developed. This high flatness wafer W1 has a rear surface R
Since the undulation on the side and the undulation on the front surface S are similarly correspondingly uniform in thickness as a whole, as shown in FIG. When vacuum suction is performed, the surface S side can be flattened, and highly accurate exposure can be performed.

[0005]

However, the following problems remain with the above-mentioned conventional mirror-finished wafer. That is, the surface S of the high flatness wafer W1 is
When polishing by MP, as shown in FIG. 7, the elastic deformation of the polishing pad P could not follow various undulations on the surface S, and the polishing amount of the oxide film and the like might vary over the entire wafer. In other words, it has been found that it is difficult to follow the undulation in a certain range of the period, that is, the undulation in the so-called nanotopological region, because the elasticity of the polishing pad by CMP has a limit. In addition, it has been found that the undulation in the nanotopology region mainly appears during acid etching with a mixed acid that is performed to remove distortion or the like in chamfering or lapping of a lapping wafer when manufacturing a mirror-finished wafer. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a high flatness semiconductor wafer capable of obtaining high polishing uniformity over the entire wafer by CMP and a method of manufacturing the same.

[0007]

The present invention has the following features to attain the object mentioned above. That is, the high-flatness semiconductor wafer of the present invention is a high-flatness semiconductor wafer whose front surface is subjected to polishing with a polishing cloth, and the front surface becomes flat while the back surface is vacuum-adsorbed to the flat surface, and the back surface is flattened. Wherein at least the elastic deformation of the polishing cloth is less than the undulation of a period that can be followed and the undulation of a period of 0.2 mm or more is removed among the undulations generated on the surface in a state where the surface is not vacuum-adsorbed to the flat surface. And

In this high flatness semiconductor wafer, the front surface becomes flat while the back surface is vacuum-adsorbed to the flat surface.
A good exposure is obtained in the photolithography process, and at least the elastic deformation of the polishing cloth is smaller than 0.2 mm or more in the period in which the elastic deformation of the polishing cloth can follow the wave generated on the surface in a state where the back surface is not vacuum-sucked to the flat surface. No undulation in the so-called nano-topological region exists because the undulation of the periodicity of the surface has been removed.When polishing the surface, the elastic deformation of the polishing pad can follow the undulation of the surface, and the entire wafer can be polished uniformly. Can be. The reason why the undulation cycle to be removed is 0.2 mm or more is that the undulation cycle is determined from the cycle dependency of the irregularities formed by the ordinary chemical reaction. In the mixed acid treatment, the time during which the generated gas generated by the chemical reaction stays on the wafer surface and the size of the grown gas are determined by the surface tension depending on the liquid composition. This is because the frequency analysis of the surface roughness revealed that the components of the periodic region were determined by mixed acid etching. Further, the nanotopology refers to a synthesis cycle of a swell component and a roughness component formed on the surface after wafer polishing.

Further, in the high flatness semiconductor wafer of the present invention, it is preferable that a cycle of the undulation to be removed is at least 20 mm or less. In this high flatness semiconductor wafer, 0.2 mm to 20 mm
Since the undulation of the cycle up to mm has been removed, not only a two-layer pad which is a polishing cloth combining a hard layer and a soft layer, which are currently generally used, but also a single-layer pad of only a hard layer, There is no undulation with a period in which elastic deformation is difficult to follow, and in such a pad, particularly uniform polishing is possible.

Further, in the high flatness semiconductor wafer of the present invention, it is preferable that the front surface and the back surface can be distinguished. In this high-flatness semiconductor wafer, the front and back surfaces are identifiable, so there is no problem with conventional chucks such as the wrong orientation of the front and back and no malfunction of the sensor. Can be easily introduced. For example, the wafer may be processed so that the surface roughness of the front surface and the back surface is different from each other (the back surface side is processed into relatively rough irregularities), and the front and back surfaces can be detected by the difference in luminance between the front surface and the back surface. .

The high-flatness semiconductor wafer of the present invention is preferably formed by subjecting a wrapped semiconductor wafer to alkaline etching with an alkaline solution, grinding the surface, and further polishing the surface.
The method for producing a high flatness semiconductor wafer of the present invention is a method for producing a high flatness semiconductor wafer whose surface is subjected to polishing with a polishing cloth, wherein the lapping step of lapping the semiconductor wafer and the lapping are performed after the lapping. The semiconductor wafer is etched with an etchant to flatten the front surface with the back surface being vacuum-sucked to a flat surface, and at least the polishing cloth of undulations generated on the front surface when the back surface is not vacuum-sucked to the flat surface. Less than 0.2mm and less than the swell of the period that the elastic deformation of
An etching step of removing waviness of the above cycle, a grinding step of grinding the surface of the semiconductor wafer after the etching step, and a polishing step of polishing the surface of the semiconductor wafer after the grinding step, wherein the etching step is And an alkali etching step of performing alkali etching using an alkaline solution as the etching solution.

In these high-flatness semiconductor wafers and the method of manufacturing the high-flatness semiconductor wafer, the semiconductor wafer is subjected to alkali etching to remove defects previously generated on the wafer surface. Etching using this alkaline solution has a slower etching rate than acid etching and a relatively slow reaction,
The generation of bubbles is small, and the surface of the semiconductor wafer is hardly roughened. As a result, the elastic deformation of the polishing cloth is smaller than the swell of a period that can be followed and swells of a period of 0.2 mm or more,
A so-called non-existent wafer is obtained by removing the undulation of the period of the so-called nanotopological region. Further, the upper limit of the period range of the undulation to be removed is set to at least 20 m.
When m is set, a semiconductor wafer having a surface state suitable for a polishing cloth such as a two-layer pad is obtained. Then, since the surface of the wafer after the alkali etching is ground and then this surface is polished, the surface can be ground before polishing so that the polishing time can be shortened, and the polishing amount can be reduced, and the polishing amount can be reduced. A decrease in flatness can be suppressed as much as possible.

[0013] In the high flatness semiconductor wafer of the present invention, it is preferable that an alkali-etched surface is acid-etched with an acidic solution, and the surface is subjected to the grinding. In the method for manufacturing a high flatness semiconductor wafer according to the present invention, it is preferable that the etching step includes an acid etching step of acid-etching the semiconductor wafer with an acid solution after the alkali etching step.

In these high-flatness semiconductor wafers and the method of manufacturing a high-flatness semiconductor wafer, after the semiconductor wafer is alkali-etched, the wafer is acid-etched with an acidic solution, so that the alkali metal on the wafer surface is removed. , Surface roughness is reduced.

In the method for manufacturing a semiconductor wafer having high flatness according to the present invention, in the alkali etching step, the semiconductor wafer is held by holding a peripheral portion of the vertically placed semiconductor wafer with a holding member and rotating the holding member. It is preferable to perform the etching while constantly rotating in the circumferential direction. In this method of manufacturing a high flatness semiconductor wafer, etching is performed while rotating the holding member in the circumferential direction by rotating the holding member, so that the contact portion between the holding member and the semiconductor wafer constantly moves, and a contact mark remains. Therefore, the etching can be uniformly performed on the peripheral portion.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a high flatness semiconductor wafer and a method of manufacturing the high flatness semiconductor wafer according to the present invention will be described below with reference to FIGS.

The high flatness semiconductor wafer of this embodiment is
As shown in FIG. 1, the surface S is C in the device manufacturing process.
This is a mirror-surface silicon wafer W2 to be subjected to MP (polishing). As shown in FIG. 1B, the silicon wafer W2 has a flat front surface S in a state where the back surface R is vacuum-adsorbed to the flat surface H, and as shown in FIG.
When the back surface R is not vacuum-sucked to the flat surface H, the front surface S
At least, the elastic deformation of the polishing pad of the CMP is smaller than the undulation of a period that can be followed and is 0.2 m.
The undulation with a period of m or more is eliminated. In the silicon wafer W2 of the present embodiment, at least 0.2 m
The swell of a period from m to 20 mm is removed.
Of course, as shown in FIG. 1C, there may be a case where the silicon wafer W2 is 20 mm or more and has no undulation.

FIG. 1A shows the silicon wafer W2.
When the surface S is polished by CMP, as shown in FIG. 2, the polishing cloth P can also be sufficiently elastically deformed along the undulation of the surface S, and the convex and concave portions of the undulation are appropriately pressed and polished. Flattened. On the other hand, in the case of the silicon wafer W2 shown in FIG.

Therefore, since the front surface S of the silicon wafer W2 is flattened while the back surface R is vacuum-adsorbed on the flat surface H, good exposure can be obtained in the photolithography step in the device manufacturing process, and the back surface R can be obtained.
Of the undulations generated on the surface S in a state where the undulations are not vacuum-adsorbed on the flat surface H, the undulations having a period smaller than the period at which the polishing pad P can follow and having a period of 0.2 mm or more are removed. There is no undulation in the topology region, and when polishing the surface S, the polishing cloth P can follow the undulation of the surface, and the entire surface of the wafer W2 can be uniformly polished. In addition, since the waviness having a period of 0.2 mm to 20 mm has been removed in a state where it is not vacuum-sucked, a polishing pad of a two-layer pad in which a hard layer and a soft layer, which are generally used at present, are combined. There is no undulation of a period in which P is difficult to follow, and in the case of the two-layer pad, particularly uniform polishing is possible. In the case of a polishing pad having a hard layer, the silicon wafer W shown in FIG.
2, there is no problem, but even in the case of the silicon wafer W2 shown in FIG. 1A, the undulation of 20 mm or more is deformed and absorbed by Si.

Next, a method of manufacturing the silicon wafer W2 will be described with reference to FIGS.

First, as shown in the flowchart of FIG. 3, the silicon ingot pulled up by the CZ method is
In the slicing step (S101), the wafer is sliced into an 8-inch silicon wafer having a thickness of 860 μm. Next, in the rough chamfering step (S102), the periphery of the sliced wafer is chamfered into a predetermined shape using a chamfering grindstone. As a result, the peripheral portion of the silicon wafer is roughly formed into a predetermined rounded shape (for example, a MOS chamfered shape). In addition, this grinding wheel for rough chamfering has #
Relatively low counts of 500 to # 800 are used.

Next, the chamfered silicon wafer is wrapped in a lapping step (S103). In this lapping step, the silicon wafer is placed between lap plates kept parallel to each other, and a lap liquid, which is a mixture of alumina abrasive grains, a dispersant, and water, is placed between the lap plate and the silicon wafer. Pour in. Then, both sides of the wafer are mechanically ground by rotating and sliding under pressure. The lap amount of the silicon wafer is 40 to 80 in total on both sides of the wafer.
It is about μm.

Next, the outer peripheral portion of the wrapped wafer is finish-chamfered (S104). For this finish chamfering, a high-counter chamfering grindstone of # 1000 to # 3000 is used to remove distortion and the like in rough chamfering. At the same time, the chamfered surface of the silicon wafer is smoothed. After that, the finished chamfered silicon wafer is alkali-etched in an alkali etching step (S105). That is, a silicon wafer is placed in a 45% by weight NaOH alkaline solution (90 ° C.) for 3 to 4 days.
Soak for a minute. As a result, defects on the exposed surface of the silicon wafer are lost. The alkali etching has a lower etching rate than the acid etching, and as a result, less bubbles are generated from the exposed surface of the silicon wafer. Thereby, the undulation of the wafer surface after the alkali etching is reduced.

As shown in FIG. 4, the etching apparatus for performing alkali etching includes an etching tank 1 in which an alkaline solution L is stored, a silicon wafer W held vertically at a peripheral portion thereof, and a silicon wafer W rotated by itself to rotate. A plurality of roller units (holding members) 2 that can rotate the wafer W in the circumferential direction. These rollers 2 are connected to a drive source such as a motor (not shown) and are always rotated in the same direction at a predetermined speed during etching. As described above, since the etching is performed while rotating the roller unit 2 and constantly rotating the silicon wafer W in the circumferential direction, the contact portion between the roller unit 2 and the silicon wafer W constantly moves, and a contact mark may remain. In addition, etching can be performed uniformly even in the peripheral portion.

In this alkaline etching step,
Silicon wafers are free, that is, the back surface is not vacuum-adsorbed to a flat surface, and at least the elastic deformation of the polishing cloth used in CMP is smaller than the waviness of the period that can be followed and is 0.2 mm or more. The swell of the cycle is removed. In the present embodiment, the alkaline etching is performed until the waviness having a cycle in the range of 0.2 mm to 20 mm is removed from the surface.

Next, the silicon wafer after the alkali etching is subjected to acid etching in an acid etching step (S106). Specifically, it is immersed for about 1 minute in a mixed acid (normal temperature to 50 ° C.) in which hydrofluoric acid and nitric acid are mixed. As described above, by performing the acid etching after the alkali etching, the alkali metal on the surface of the wafer can be removed, and the surface roughness of the wafer surface can be improved.

The next light polishing step (S107) for the back surface of the wafer is performed as necessary. This step is
This is a step of slightly polishing the back surface of the wafer. That is,
The back surface of the silicon wafer is polished by about 0.1 μm using free abrasive grains having a particle diameter of 0.05 μm. As a result, the surface roughness of the wafer surface can be further increased. In addition,
Light polishing process for this wafer back surface (S107)
May be performed after the subsequent wafer surface grinding step (S110). By this light polishing step, the brightness of the front and back surfaces of the silicon wafer is different from each other, and the front and back surfaces of the silicon wafer can be identified by the brightness. Here, the luminance is a ratio of the reflectance when the mirror surface of the wafer is set to 100.

Next, a cleaning step (S108) of cleaning the silicon wafer with an RCA-based cleaning liquid is performed. Then, the silicon wafer is subjected to donor killer heat treatment (S
109). After that, the surface of the silicon wafer was changed to a wafer grinding wheel manufactured by Disco Corporation, product name "IF-01-1-4 /
6-B-M01 "(S110). This grinding apparatus has a grinding wheel of high count # 2000. The grinding amount at this time is about 3 to 10 μm. As a result, when the surface of the wafer is polished in a subsequent step, the polishing amount is 5 to 7 μm. Specifically, when the silicon wafer has a thickness of 740 μm, it is ground to about 10 μm. As described above, since the grinding is performed by the grinding wheel having a higher number, the wafer surface relatively flatly etched by the alkaline solution can be ground without so much roughening the wafer surface.

Next, the outer peripheral portion of the silicon wafer whose surface has been ground is subjected to mechanical and chemical polishing on the chamfered surface in a PCR (Polishing Corner Rounding) step (S111). Thereby, the outer peripheral portion (chamfered surface) of the wafer is mirror-finished. Further, the surface of the silicon wafer after the PCR processing is further polished in a polishing step (S112). The amount of polishing is sufficient at 3 to 7 μm to remove damage in the grinding step of S110. For this reason, the polishing amount, which is a problem in the case of further polishing a silicon wafer having a high flatness, is reduced to about 1
It is possible to avoid a region where the flatness is reduced when the thickness exceeds 0 μm. Moreover, since the wafer surface is ground before polishing, the polishing time can be reduced. After that, a cleaning step (S113) is performed. Specifically, RCA cleaning is performed.

Through the above steps, a high-quality silicon wafer W2 having high flatness and capable of being uniformly polished by CMP as a whole is manufactured.

The manufactured silicon wafer W2
For example, the surface undulation is evaluated by the following nanotopology measuring device. This nanotopology measuring apparatus performs measurement by surface observation using a magic mirror and an optical surface roughness meter.

The present invention also includes the following embodiments. In the above embodiment, the cycle of the undulation to be removed is set to 20 mm. However, according to the polishing cloth used in the CMP during the device manufacturing process, that is, according to the cycle of the undulation in which the elastic deformation of the polishing cloth is difficult to follow. What is necessary is just to determine the cycle of the undulation removed.

In the above-described embodiment, an alkaline solution of NaOH is used. However, as another etchant, a high-concentration alkaline solution such as KOH is preferable. This is because, due to the difference in surface tension due to the increase in the viscosity of the solution, the growth of the reaction gas is suppressed, and the shielding effect on the wafer surface is reduced. Furthermore, in the above embodiment, the present invention is applied to a silicon wafer as a semiconductor wafer, but may be applied to a method of manufacturing another semiconductor wafer, for example, a compound semiconductor wafer (such as a gallium / arsenic wafer).

[0034]

According to the high flatness semiconductor wafer of the present invention, the front surface becomes flat while the back surface is vacuum-adsorbed to the flat surface, so that good exposure can be obtained in the photolithography step and the back surface is flat. Since at least the elastic deformation of the polishing cloth is less than the waviness of a period that can be followed and the waviness of a period of 0.2 mm or more is removed among the waviness that occurs on the surface in a state where the surface is not vacuum-adsorbed,
There is no undulation in the nanotopological region, and the elastic deformation of the polishing pad can follow the undulation on the surface. Therefore, high exposure accuracy can be obtained, uniform polishing can be performed by CMP over the entire surface of the wafer, and variations in polishing of an oxide film or the like formed on the surface can be reduced, and the yield of devices can be improved.

According to the method of manufacturing a semiconductor wafer having a high flatness of the present invention, the semiconductor wafer is subjected to alkali etching, so that a slow etching rate and a small number of bubbles are generated, so that a period in which the elastic deformation of the polishing pad can follow can be achieved. Wafers smaller than the undulations and having a period of 0.2 mm or more, that is, the undulations of the period of the nanotopological region are effectively removed. Then, since the surface of the wafer after the alkali etching is ground and then this surface is polished, the surface can be ground before polishing so that the polishing time can be shortened, and the polishing amount can be reduced, and the polishing amount can be reduced. By suppressing the decrease in flatness as much as possible, a wafer with high flatness can be obtained.

[Brief description of the drawings]

FIG. 1 shows a state in which a back surface showing a silicon wafer in one embodiment of a high flatness semiconductor wafer and a method for manufacturing a high flatness semiconductor wafer according to the present invention is not vacuum-adsorbed (a) and is vacuum-adsorbed ( It is a schematic sectional drawing of b) and another example (c) in the state where it is not vacuum-sucked.

FIG. 2 is a fragmentary cross-sectional view showing a silicon wafer whose surface is polished by CMP in one embodiment of the high flatness semiconductor wafer and the method for manufacturing the high flatness semiconductor wafer according to the present invention.

FIG. 3 is a flowchart showing a manufacturing process in one embodiment of a high flatness semiconductor wafer and a method for manufacturing a high flatness semiconductor wafer according to the present invention.

FIG. 4 is a schematic cross-sectional view showing an etching apparatus in an alkali etching step in one embodiment of a high flatness semiconductor wafer and a method for manufacturing a high flatness semiconductor wafer according to the present invention.

FIG. 5 is a schematic cross-sectional view showing a silicon wafer in a conventional example of a high flatness semiconductor wafer and a method of manufacturing a high flatness semiconductor wafer according to the present invention, in which a back surface is not vacuum-sucked and vacuum-sucked; It is.

FIG. 6 is a schematic view showing a state in which a back surface of a silicon wafer in another conventional example of a high flatness semiconductor wafer and a method of manufacturing a high flatness semiconductor wafer according to the present invention is not vacuum-sucked and is vacuum-sucked; It is sectional drawing.

FIG. 7 is a cross-sectional view of a principal part showing a silicon wafer whose surface is polished by CMP in another conventional example of the high flatness semiconductor wafer and the method of manufacturing the high flatness semiconductor wafer according to the present invention.

[Explanation of symbols]

 S103 Lapping step S105 Alkali etching S106 Acid etching S110 Grinding step S112 Polishing step S Silicon wafer surface P Polishing cloth R Silicon wafer back surface W2 Silicon wafer (semiconductor wafer)

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kazunari Takaishi 1-297 Kitabukuro-cho, Omiya-shi, Saitama Mitsubishi Materials Silicon Research Center F-term (reference) 5F043 AA02 BB02 BB27 DD07 DD16 DD30 EE04 EE08 EE35 FF07

Claims (9)

[Claims] 1. A high-flatness semiconductor wafer having a front surface to be polished by a polishing cloth, wherein the front surface is flattened while the back surface is vacuum-sucked to a flat surface, and the back surface is vacuum-sucked to a flat surface. At least the elastic deformation of the polishing cloth is less than the undulation of a period that can be followed and 0.2 m among undulations generated on the surface in a state where the undulation is not performed.
A high-flatness semiconductor wafer, wherein undulations with a period of m or more are removed. 2. The high flatness semiconductor wafer according to claim 1, wherein a period of the undulations to be removed is at least 20 mm or less. 3. The high flatness semiconductor wafer according to claim 1, wherein the front surface and the back surface are identifiable. 4. The high flatness semiconductor wafer according to claim 3, wherein the wrapped semiconductor wafer is formed by alkali etching with an alkaline solution, grinding the surface, and polishing the surface. High flatness semiconductor wafer. 5. The high-flatness semiconductor wafer according to claim 4, wherein said alkali-etched surface is acid-etched with an acidic solution and said surface is ground. 6. A method for producing a high flatness semiconductor wafer, the surface of which is subjected to polishing with a polishing cloth, comprising: a lapping step of lapping the semiconductor wafer; and etching the semiconductor wafer with an etchant after the lapping. The surface becomes flat when the back surface is vacuum-sucked to the flat surface, and at least the waviness that occurs on the surface when the back surface is not vacuum-sucked to the flat surface, at least the period in which the elastic deformation of the polishing cloth can follow. An etching step of removing undulations having a period smaller than 0.2 mm or more; a grinding step of grinding the surface of the semiconductor wafer after the etching step; and a polishing step of polishing the surface of the semiconductor wafer after the grinding step. The etching step comprises an alkali using an alkaline solution as the etching solution. High flatness semiconductor wafer manufacturing method which is characterized in that it comprises an alkali etching step of etching. 7. The method of manufacturing a high flatness semiconductor wafer according to claim 6, wherein in the etching step, a period of the undulation to be removed is at least 20 mm or less. Method. 8. The method for manufacturing a high flatness semiconductor wafer according to claim 6, wherein the etching step includes an acid etching step of acid-etching the semiconductor wafer with an acid solution after the alkali etching step. A method for producing a high flatness semiconductor wafer, comprising: 9. The method of manufacturing a high flatness semiconductor wafer according to claim 6, wherein the alkali etching step holds a peripheral portion of the vertically placed semiconductor wafer with a holding member, and A method for manufacturing a high flatness semiconductor wafer, characterized in that the etching is performed while the holding member is rotated and the semiconductor wafer is constantly rotated in the circumferential direction.