JP2001156074A - Method for heat treating silicon wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a wafer which is free from an aggregate of point defects, develops an oxygen deposit nucleus, and exhibits an IG effect with a heat treatment in a device manufacturing step. SOLUTION: It is assumed that a region adjacent to a region I having inter- lattice silicon type point defects predominantly contained therein, belongs to a perfect region P having no aggregate of point defects therein, and has an inter-lattice silicon concentration less than a lowest level capable of forming an interstitical dislocation, is denoted by PI. It is also assumed that a region which is adjacent to a region V having air void type point defects dominantly present therein, belongs to the region P, and has an air void concentration not larger than a level capable of forming COP or FPD, is denoted by PV. Then a wafer including a mixed region of the regions PV and PI and having an oxygen concentration of 0.8×1018 to 1.4×1018 atoms/cm3 (old ASTM) is held in an atmosphere of a nitrogen, argon, hydrogen or oxygen gas or a mixture gas thereof at a temperature of 600-850 deg.C for 30-90 minutes or at a temperature of 600-850 deg.C for 120-250 minutes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides an intrinsic gettering (IG) effect on a silicon wafer formed by the Czochralski method (hereinafter, referred to as CZ method) free of point defect aggregates. It relates to a heat treatment method. More specifically, fully express oxygen precipitation nuclei,
The present invention relates to a method for heat-treating a silicon wafer that exhibits an IG effect in a heat treatment in a device manufacturing process.

[0002]

2. Description of the Related Art In recent years, in the process of manufacturing a semiconductor integrated circuit, an oxidation-induced stacking fault (hereinafter referred to as OSF) is a cause of lowering the yield.
That. ) Nuclei of oxygen precipitates and microcrystalline particles (Crystal Originated Particl
e, hereinafter referred to as COP. ) Or interstitial dislocations (Int
erstitial-type Large Dislocation, hereinafter referred to as LD. ). OSF introduces minute defects serving as nuclei during crystal growth, becomes apparent in a thermal oxidation step or the like when manufacturing a semiconductor device, and causes defects such as an increase in leak current of the manufactured device. Also COP
Are pits caused by crystals that appear on the wafer surface when the mirror-polished silicon wafer is washed with a mixed solution of ammonia and hydrogen peroxide. When this wafer is measured with a particle counter, these pits are also detected as light scattering defects together with the original particles. This C
OP is an electrical characteristic, for example, a time-dependent dielectric breakdown characteristic (Time Dependent dielectric Breakdown, TDD) of an oxide film.
B), oxide film breakdown voltage characteristics (Time Zero Dielectric Breakdo
wn, TZDB) and the like. Also COP
Is present on the wafer surface, a step is generated in a device wiring process, which may cause disconnection. This also causes a leak and the like in the element isolation portion, and lowers the product yield. Furthermore, LD is also called a dislocation cluster,
Alternatively, when a silicon wafer having this defect is immersed in a selective etching solution containing hydrofluoric acid as a main component, a pit is generated, and thus the silicon wafer is also called a dislocation pit. This LD also causes deterioration of electrical characteristics such as leak characteristics and isolation characteristics.

[0003] From the above, OSF, CO, etc. can be obtained from a silicon wafer used for manufacturing a semiconductor integrated circuit.
There is a need to reduce P and LD. A defect-free silicon wafer having no OSF, COP and LD is disclosed in JP-A-11-1393. This defect-free silicon wafer has a perfect region [P] when a perfect region in which no aggregate of vacancy type point defects and no aggregate of interstitial silicon type point defects are present in a silicon single crystal ingot is defined as [P]. P] is a silicon wafer cut from the ingot. The perfect region [P] is located between the region [I] where interstitial silicon type point defects predominantly exist and the region [V] where vacancy type point defects predominantly exist in the silicon single crystal ingot. Intervene. This perfect area [P]
In the silicon wafer made of, the pulling speed of the ingot is V (mm / min), and the temperature gradient in the vertical direction of the ingot near the interface between the silicon melt and the ingot is G.
(° C./mm), V / G (mm ² / min · ° C.) is determined so that the OSF generated in a ring shape during the thermal oxidation treatment disappears at the center of the wafer. .
On the other hand, some of the semiconductor device manufacturers include OSF, CO
Some manufacturers seek silicon wafers that do not have P and LD, but also have the ability to getter metal contamination from device processing. If the wafer does not have sufficient gettering ability, contamination with metal in the device process causes junction leakage, device operation failure due to trap levels due to metal impurities, and the like, thereby lowering product yield.

[0004]

However, a silicon wafer cut from the ingot consisting of the perfect region [P] does not have an OSF, a COP and an LD. Oxygen precipitation does not occur, so that the IG effect may not be sufficiently obtained. An object of the present invention is to provide a mixed region of the region [P _V ] and the region [P _I ] with an oxygen concentration of 0.8 × 10 ^{18 to} 1.4 × 10 ¹⁸ atoms / cm.
^{3 Even} silicon wafers cut from (old ASTM) ingots, in addition to the absence of point defect aggregates, fully express oxygen precipitation nuclei and have an IG effect by heat treatment in the device manufacturing process. An object of the present invention is to provide a heat treatment method for a silicon wafer that is effective. Another object of the present invention is to provide a heat treatment method for a silicon wafer which does not require an oxygen donor killer treatment step.

[0005]

The invention according to claim 1 is
The region where interstitial silicon type point defects predominantly exist in a silicon single crystal ingot is [I], the region where vacancy type point defects predominantly exist is [V], and the interstitial silicon type point defects are Assuming that [P] is a perfect region in which no aggregates and no void type point defects are present, heat treatment of a silicon wafer having no point defect aggregates cut out from the ingot formed of the perfect region [P] Is the way. The characteristic configuration is such that a region adjacent to the region [I] and belonging to the perfect region [P] and having a lower interstitial silicon concentration lower than the minimum interstitial silicon concentration at which interstitial dislocations can be formed is [P _I ], and the region [V [P _V ] is a mixed region of the above-mentioned region [P _V ] and the region [P _I ], which is adjacent to the perfect region [P] and has a vacancy concentration below the vacancy concentration capable of forming COP or FPD. And oxygen concentration of 0.8 × 1
0 ^{18 to} 1.4 × 10 ¹⁸ atoms / cm ³ (old AST
M), a silicon single crystal ingot is pulled up, and a silicon wafer cut out of the ingot is placed in a nitrogen, argon, hydrogen, oxygen or mixed gas atmosphere thereof for 60 hours.
Hold at 0-850 ° C. for 30-90 minutes, or 600
850 ° C. for 120 to 250 minutes.

In the invention according to the first aspect, the oxygen concentration of the ingot is 0.8 × 10 ^{18 to} 1.4 × 10 ¹⁸ atoms /.
cm ³ (old ASTM), and when the silicon wafer is composed of a mixed region of the region [P _V ] and the region [P _I ], the silicon wafer cut out from the ingot is heat-treated under the above conditions. Oxygen precipitate nuclei also appear in the region [P _I ] where oxygen precipitate nuclei are not introduced during crystal growth, and at the same time, the density of the oxygen precipitate nuclei increases in the region [P _V ] where oxygen precipitate nuclei are introduced during crystal growth. Therefore, when a wafer subjected to the above heat treatment is subjected to heat treatment in a device manufacturing process of a semiconductor device maker, the oxygen precipitate nucleus becomes an oxygen precipitate (Bulk Micro Defect, hereinafter referred to as BMDD).
That. ), And even if the wafer is a mixed region of the region [P _V ] and the region [P _I ], the IG effect is obtained over the entire surface of the wafer.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The silicon wafer of the present invention has a C
After the ingot is pulled up from the silicon melt in the hot zone furnace by the Z method with a predetermined pulling speed profile based on Voronkov's theory, the ingot is sliced. Generally, when a silicon single crystal ingot is pulled up from a silicon melt in a hot zone furnace by the CZ method, point defects and agglomerates: Defects). Point defects have two general forms: vacancy type point defects and interstitial silicon type point defects. A vacancy-type point defect is one in which one silicon atom has separated from one of the normal positions in the silicon crystal lattice. Such holes become hole type point defects. On the other hand, if an atom is found at a position (interstitial site) other than the lattice point of the silicon crystal, this becomes an interstitial silicon point defect.

[0008] Point defects are generally formed at the interface between the silicon melt (molten silicon) and the ingot (solid silicon). However, by continuously pulling up the ingot, the portion that was the contact surface starts to cool down with pulling up. During cooling, vacancy-type point defects or interstitial silicon-type point defects merge with each other by diffusion to form vacancy agglomerates or interstitial agglomerates. Is formed. In other words, the aggregate is a three-dimensional structure generated due to the merging of point defects. Aggregates of vacancy-type point defects are LSTDs (Laser Scattering Tomograms) in addition to the COPs described above.
An agglomerate of interstitial silicon-type point defects includes a defect called an LD, which includes a defect called an aph defect or an FPD (Flow Pattern Defects). FPD stands for Secco etching (HF: K ₂ C) for a silicon wafer prepared by slicing an ingot for 30 minutes.
_{r 2 O 7 (0.15mol / l} ) = 2: a source of trace exhibiting a unique flow pattern which appears when a by etching) and the first mixture, the LSTD, when irradiated with infrared rays in the silicon single crystal Is a source that has a refractive index different from that of silicon and generates scattered light.

In order to grow a high-purity ingot having a small number of defects, Bornkov's theory states that the pulling speed of the ingot is V (mm / min) and the temperature gradient in the ingot near the interface between the ingot and the silicon melt is G. (° C./mm) means controlling V / G (mm ² / min · ° C.). In this theory, as shown in FIG. 1, V / G is set on the horizontal axis, and the vacancy type point defect concentration and the interstitial silicon type point defect concentration are set on the same vertical axis, and the V / G and the point defect concentration are compared. The relationship is represented graphically, explaining that the boundary between the vacancy region and the interstitial silicon region is determined by V / G. More specifically, when the V / G ratio is higher than the critical point, an ingot in which the vacancy-type point defect concentration is dominant is formed, while the V / G ratio is formed.
When the ratio is lower than the critical point, an ingot in which the interstitial silicon type point defect concentration is dominant is formed. In FIG. 1, [I] indicates a region ((V / G) ₁ or less) where an interstitial silicon type point defect is dominant and an interstitial silicon type point defect exists.
[V] is a region ((V / G) ₂ where the vacancy type point defect in the ingot is dominant and the vacancy type point defect aggregate exists.
[P] indicates a perfect region ((V / G) ₁ to (V / G) ₂ ) where no aggregate of vacancy type point defects and no aggregate of interstitial silicon type point defects exist. In the region [V] adjacent to the region [P], the region [OS
F] ((V / G) ₂ to (V / G) ₃ ).

The perfect area [P] is further classified into an area [P _I ] and an area [P _V ]. [P _I ] is V / G
The ratio is from (V / G) ₁ to the critical point,
[P _V ] is a region where the V / G ratio is from the critical point to the above (V / G) ₂ . That is, [P _I ] is a region adjacent to the region [I] and having an interstitial silicon type point defect concentration lower than the lowest interstitial silicon type point defect concentration capable of forming an interstitial dislocation, and [P _V] ] Is a region adjacent to the region [V] and having a vacancy-type point defect concentration lower than the lowest vacancy-type point defect concentration capable of forming an OSF. The predetermined pull rate profile of the present invention is such that when the ingot is pulled from the silicon melt in a hot zone furnace, the ratio of the pull rate to the temperature gradient (V / G) reduces the generation of interstitial silicon-type point defect aggregates. The first critical ratio ((V / G) ₁ ) or more, which limits the agglomerates of vacancy-type point defects to a region in the center of the ingot where vacancy-type point defects predominantly exist. It is determined so as to be maintained at 2 critical ratio ((V / G) ₂ ) or less.

The pulling speed profile is determined by simulating the reference ingot in the axial direction experimentally or by combining these techniques, based on the above-mentioned Bornkov theory by simulation. That is, this determination is made by, after the simulation, slicing the ingot sliced in the axial direction in the transverse direction, confirming it in the wafer state, and repeating the simulation. For the simulation, a plurality of kinds of pulling speeds are determined within a predetermined range, and a plurality of reference ingots are grown. As shown in FIG. 2, the pulling speed profile for the simulation is from a high pulling speed (a) such as 1.2 mm / min to a low pulling speed (c) of 0.5 mm / min and again a high pulling speed (d). It is adjusted to. The low pull rate may be 0.4 mm / min or less, and the change in pull rates (b) and (d) is preferably linear. A plurality of reference ingots pulled at different speeds are separately sliced in the axial direction. The optimal V / G is determined from the correlation of the results of the axial slicing, wafer verification and simulation, followed by the determination of the optimal pulling speed profile and the production of the ingot. The actual pulling speed profile will depend on many variables including but not limited to the desired ingot diameter, the particular hot zone furnace used and the quality of the silicon melt.

FIG. 3 shows the fact that a sectional view of the ingot when V / G is continuously reduced by gradually lowering the pulling speed is shown. FIG. 3 shows a region [V] in which vacancy type point defects predominantly exist in the ingot, a region [I] in which interstitial silicon type point defects predominantly exist, and a vacancy type point defect. The perfect regions where no aggregates of the above-mentioned and aggregates of interstitial silicon type point defects are present are indicated as [P], respectively. As described above, the perfect area [P] is further classified into an area [P _I ] and an area [P _V ]. The region [P _V ] is a region where vacancy type point defects which do not form an aggregate exist in the perfect region [P], and the region [P _I ] is an interstitial silicon type which does not form an aggregate in the perfect region [P]. This is an area where a point defect exists. As shown in FIG. 3, the axial position P of the ingot
₁ includes a region where vacancy-type point defects predominantly exist in the center. Position P ₃ includes the ring area and the central perfect area that exists dominantly interstitial silicon type point defects. The position P ₂ is a perfect region because there are no aggregates of vacancy-type point defects at the center and no aggregates of interstitial silicon-type point defects at the edges related to the present invention.

As is apparent from FIG. 3, the wafer W ₁ corresponding to the position P ₁ includes a region in which vacancy type point defects are predominantly present in the center. The wafer W ₃ corresponding to the position P ₃ is
It includes a ring in which interstitial silicon type point defects predominantly exist and a central perfect region. The wafer W ₂ corresponding to the position P ₂ is the wafer according to the present invention, and has no void-type point defect aggregates in the center and no interstitial silicon-type point defect aggregates at the edge portion. This is a perfect area in which the area [P _V ] and the area [P _I ] are mixed. A small area (V / G in FIG. 1) in contact with the perfect area of the area where the vacancy type point defect is predominantly present.
₂ to (V / G) ₃ ) is a region where neither COP nor LD occurs in the wafer surface. However, this silicon wafer W
_{On the} other hand, according to the conventional OSF revealing heat treatment, heat treatment is performed in an oxygen atmosphere at a temperature of 1000 ° C. ± 30 ° C. for 2 to 5 hours, and subsequently at 1130 ° C. ± 30 ° C. for 1 to 16 hours. This produces OSF. As shown in FIG. 4A,
OSF in the vicinity of 1/2 of the radius of the wafer in the wafer W ₁
Rings occur. COP tends to appear in a region surrounded by the OSF ring and in which vacancy-type point defects are predominantly present.

Incidentally, aggregates of point defects such as COP and LD may have different values of detection sensitivity and detection lower limit depending on the detection method. Therefore, in the present specification, "there is no aggregate of point defects" means the product of the observation area and the etching allowance by an optical microscope after subjecting a mirror-finished silicon single crystal to non-stirring seco etching. When observed as an inspection volume, one agglomerate of flow pattern (vacancy type defect) and dislocation cluster (interstitial silicon type point defect) has one defect per 1 × 10 ⁻³ cm ³ of inspection volume. The lower limit of detection (1 × 10 ³ / cm ³ )
Means that the number of point defect aggregates is equal to or less than the lower limit of detection.

The silicon wafer of the present invention is a wafer W ₂ mentioned above, a plan view is shown in Figure 4B. The wafer W ₂ has an oxygen concentration of 0.8 × 10 ^{18 to} 1.4 × 10 ¹⁸ atoms / s in order to generate oxygen precipitation nuclei of a desired density or more on the wafer W ₂ by the heat treatment of the present invention.
cm ³ (old ASTM).

[0016] will now be described heat treatment of the silicon wafer W _2. This heat treatment is a nitrogen wafer W _2, argon, hydrogen, oxygen or a mixed gas atmosphere thereof, 6
Hold at 00-850 ° C. for 30-90 minutes or 60
It is carried out by holding at 0 to 850 ° C for 120 to 250 minutes. The heating is preferably performed by introducing the wafer into a heat treatment furnace maintained at 600 to 850 ° C. at a rate of 50 to 100 ° C./min. When the holding temperature is less than 600 ° C. or the holding time is less than 30 minutes, the number of oxygen precipitation nuclei does not increase sufficiently, and the IG effect is required when heat treatment is performed in a device manufacturing process of a semiconductor device manufacturer. BMD
The density cannot be obtained. When the holding temperature exceeds 850 ° C., the density of oxygen precipitation nuclei in the region [P _I ] is low, so that the BMD density required for exhibiting the IG effect when heat treatment is performed in the device manufacturing process cannot be obtained. Holding temperature is 600-8
If the holding temperature is more than 90 minutes and less than 120 minutes at 50 ° C., the amount of interstitial type point defects accompanying the formation of oxygen precipitation nuclei is excessive, thereby suppressing the precipitation amount of oxygen precipitation nuclei. If the holding time is longer than 250 minutes, the productivity is reduced.

The condition of this heat treatment is such that a chemical vapor deposition method (CVD method, Chemical Vapor Deposition
The method is included in the heat treatment conditions (holding temperature 650 ° C. ± 30 ° C., holding time 5 to 300 minutes) when forming the polysilicon layer by the method, so that the CVD method is used to form the polysilicon layer on the back surface of the wafer. The object of the present invention can be achieved by forming a polysilicon layer if the heat treatment is performed in accordance with the heat treatment condition according to 1. At this time, the thickness of the polysilicon layer is 0.1 to 2.0 μm. By forming the polysilicon layer on the back surface of the wafer, oxygen precipitation nuclei are further increased near the back surface of the wafer in contact with the polysilicon layer. The form of this wafer may be such that the polysilicon layer may be left as it is, or an acid etching solution obtained by diluting a mixed acid of hydrofluoric acid and nitric acid with water or acetic acid, or an alkali etching solution obtained by diluting KOH or NaOH in water. To remove the polysilicon layer. Further, by performing the heat treatment, the oxygen donor killer treatment in the wafer process becomes unnecessary.

[0018]

Next, examples of the present invention will be described together with comparative examples. <Example 1> Diameter 8 using a silicon single crystal pulling apparatus
An inch of boron (B) doped p-type silicon ingot was pulled up. This ingot has a straight body length of 1200 mm, a crystal orientation of (100), and a resistivity of about 10
Ωcm, oxygen concentration is 1.0 × 10 ¹⁸ atoms / cm ³
(Old ASTM). Ingot is V when pulling
While reducing / G of 0.24mm ² / min ° C. 0.18 mm ² / minute ° C. until continuously grown two under the same conditions.
One of the ingots cuts the center of the ingot in the pulling direction as shown in FIG. 3 and checks the position of each area.
Cut silicon wafer W ₂ at the position corresponding the another one for P ₂ in Figure 3, was used as a sample. In this example, the wafer serving as a sample has a region [P _V ] at the center, a region [P _I ] around the region, and further has a region [P _V ] around the wafer W shown in FIG. 4B. ₂ This wafer W ₂ cut out from the ingot and polished to a mirror surface was treated under nitrogen atmosphere for 6 hours.
A heat treatment was performed at 50 ° C. for 30 minutes.

[0019] The heat treatment temperature of <Example 2> Example 1 cut out from the same ingot and mirror-polished wafer W ₂ 65
Heat treatment was performed in the same manner as in Example 1 except that the temperature was set to 0 ° C. and the holding time was set to 90 minutes. <Example 3> Example 1 the heat treatment temperature of the wafer W ₂ was cut polished from the same ingot as a 650 ° C., except that the retention time was 210 minutes, was heat-treated in the same manner as in Example 1. <Example 4> Example 1 the heat treatment temperature of the wafer W ₂ was cut polished from the same ingot as a 750 ° C., except that the retention time was 60 minutes, was heat-treated in the same manner as in Example 1.

<Embodiment 5> The heat treatment temperature of the wafer W ₂ cut out from the same ingot as in Embodiment 1 and mirror-polished is set to 75.
Heat treatment was performed in the same manner as in Example 1 except that the temperature was set to 0 ° C. and the holding time was set to 90 minutes. <Example 6> heat treatment temperature 850 ° C. Example 1 and the wafer W ₂ was cut polished from the same ingot, except that the retention time was 30 minutes, and heat-treated in the same manner as in Example 1. <Example 7> Example 1 the heat treatment temperature of the wafer W ₂ was cut polished from the same ingot as a 850 ° C., except that the retention time was 120 minutes, was heat-treated in the same manner as in Example 1.

[0021] was not subjected to the heat treatment of the wafer W _2, which was cut mirror-polished from the same ingot and <Comparative Example 1> Example 1. <Comparative Example 2> Example 1 the heat treatment temperature of the wafer W ₂ was cut polished from the same ingot as a 650 ° C., except that the retention time was 100 minutes, and heat-treated in the same manner as in Example 1. <Comparative Example 3> Example 1 the heat treatment temperature of the wafer W ₂ was cut polished from the same ingot as a 750 ° C., except that the retention time was 20 minutes, it was heat-treated in the same manner as in Example 1. <Comparative Example 4> heat treatment temperature 800 ° C. Example 1 and the wafer W ₂ was cut polished from the same ingot, except that the retention time was 100 minutes, and heat-treated in the same manner as in Example 1.

<Comparative Evaluation> Examples 1 to 7 and Comparative Examples 1 to
4 wafer W_Two4 pieces each, and these 4 pieces of way
C W_TwoMetal elements such as Fe, Cr, Ni and Cu
Each of the four types of solutions is dropped separately and spin-coated
By doing, the entire surface of the four wafers is Fe,
Forcibly contaminated with Cr, Ni and Cu. All contaminated
Wafer W _TwoAfter heat treatment at 900 ° C. for 2 hours,
0.5 hours at 0 ° C and 1.5 hours at 800 ° C
Each metal element diffuses into the bulk of the wafer.
I let you. Heat treatment after this contamination is performed by semiconductor device manufacturers.
Corresponds to the heat treatment in the device manufacturing process. Contaminated metal
In order to confirm the IG effect of
Etching only about 2 μm thick with a etching solution
The presence or absence of haze was observed below. Examples 1 to 7 and Comparative Example
Table 1 shows the presence or absence of haze of Nos. 1 to 4. Examples
FIG. 5 shows an optical microscope photograph of Comparative Example 1, and FIG.
The truth is shown in FIG. 5A and 6A show Fe contamination.
1/4 of the wafers of Example 1 and Comparative Example 1
Shown respectively. Similarly, FIG. 5B and FIG. 6B show Cr contamination,
5C and 6C show Ni contamination, and FIGS. 5D and 6D show Cu contamination.
1/4 of the contaminated wafers of Example 1 and Comparative Example 1
Shown respectively.

[0023]

[Table 1]

As is clear from Table 1, FIGS. 5 and 6,
Comparative Example 1-4 [P _IHaze only
Appeared. This is because of the wafers under the heat treatment conditions of Comparative Examples 1-4.
Oxygen precipitation nucleus density is low.
This is probably because the IG effect was not exhibited. Against this
In the wafers of Examples 1 to 7, haze did not appear,
[P_V] And area [P_I] Oxygen precipitation nucleation density over the entire surface
It has a high degree and has an IG effect.

[0025]

As described above, according to the heat treatment method of the present invention, the heat treatment method comprises a mixed region of the region [P _V ] and the region [P _I ] and has an oxygen concentration of 0.8 × 10 ^{18 to} 1.4. × 10 ¹⁸ at
oms / cm ³ (former ASTM) silicon wafer is kept at 600 to 850 ° C. for 30 to 90 minutes in an atmosphere of nitrogen, argon, hydrogen, oxygen or a mixed gas thereof, or 120 to 250 at 600 to 850 ° C. By keeping the minute amount, an oxygen precipitate nucleus having a desired density or more is formed in the region [P _I ] in addition to the absence of the point defect aggregate. The IG effect can be exhibited by performing the heat treatment in the device manufacturing process of the semiconductor device maker on the wafer after the heat treatment. Further, by performing the heat treatment of the present invention, there is also an advantage that the oxygen donor killer treatment conventionally performed becomes unnecessary.

[Brief description of the drawings]

FIG. 1 is a diagram based on Bornkov's theory showing that when the V / G ratio is above the critical point, a vacancy-rich ingot is formed, and when the V / G ratio is below the critical point, an interstitial silicon-rich ingot is formed. .

FIG. 2 is a characteristic diagram showing a change in pulling speed for determining a desired pulling speed profile.

FIG. 3 is a schematic diagram of an X-ray topography showing a region where holes of a reference ingot are predominantly present, a region where interstitial silicon is predominantly present, and a perfect region according to the present invention.

4A is a wafer W ₁ showing a situation in which an OSF ring appears on a silicon wafer W ₁ corresponding to a position P ₁ in FIG.
FIG. Plan view of a silicon wafer W ₂ corresponding to the position P ₂ of the B Figure 3. The figure which shows the situation in which an OSF ring appears.

[5] causes the wafer W ₂ of Example 1 is metal contamination, optical micrograph showing the presence or absence of haze after being diffused into the bulk metal.

FIG. 6 is an optical microscope photograph showing the presence or absence of haze after the wafer W ₂ of Comparative Example 1 was contaminated with metal and the metal was diffused into the bulk.

[Procedure amendment]

[Submission Date] November 26, 1999 (1999.11.
26)

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] Fig. 5

[Correction method] Change

[Correction contents]

FIG. 5

[Procedure amendment 2]

[Document name to be amended] Drawing

[Correction target item name] Fig. 6

[Correction method] Change

[Correction contents]

FIG. 6 ────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] October 31, 2000 (2000.10.
31)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Brief description of drawings

[Correction method] Change

[Correction contents]

[Brief description of the drawings]

FIG. 1 is a diagram based on Bornkov's theory showing that when the V / G ratio is above the critical point, a vacancy-rich ingot is formed, and when the V / G ratio is below the critical point, an interstitial silicon-rich ingot is formed. .

FIG. 2 is a characteristic diagram showing a change in pulling speed for determining a desired pulling speed profile.

FIG. 3 is a schematic diagram of an X-ray topography showing a region where holes of a reference ingot are predominantly present, a region where interstitial silicon is predominantly present, and a perfect region according to the present invention.

4A is a wafer W ₁ showing a situation in which an OSF ring appears on a silicon wafer W ₁ corresponding to a position P ₁ in FIG.
FIG. Plan view of a silicon wafer W ₂ corresponding to the position P ₂ of the B Figure 3.

[5] causes the wafer W ₂ of Example 1 is metal contamination, optical micrograph showing the presence or absence of haze after being diffused into the bulk metal.

FIG. 6 is an optical microscope photograph showing the presence or absence of haze after the wafer W ₂ of Comparative Example 1 was contaminated with metal and the metal was diffused into the bulk.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4G077 AA02 AB01 BA04 CF10 FE02 FE03 FE11 5F053 AA12 DD01 FF04 GG01 PP03 PP20 RR03 RR04

Claims (2)

[Claims] A region where interstitial silicon type point defects predominantly exist in a silicon single crystal ingot is [I], a region where vacancy type point defects predominantly exist is [V], When a perfect region in which no aggregate of silicon-type point defects and no aggregate of void-type point defects are present is defined as [P], the aggregate of point defects cut out from the ingot including the perfect region [P] is A heat treatment method for a silicon wafer that does not exist, wherein a region adjacent to the region [I] and belonging to the perfect region [P] and having a minimum interstitial silicon concentration below which the interstitial dislocations can be formed is defined as [P _I ]. When a region adjacent to the region [V] and belonging to the perfect region [P] and having a vacancy concentration below the vacancy concentration capable of forming a COP or FPD is [P _V ], the region [P _V ] and the region [P _I ] Region and the oxygen concentration is 0.8 × 10 ^{18 to} 1.4 × 10 ¹⁸ atoms
/ Cm ³ (former ASTM), a silicon single crystal ingot is pulled up, and a silicon wafer cut out from the ingot is heated at 600 to 850 ° C. for 30 to 90 minutes in an atmosphere of nitrogen, argon, hydrogen, oxygen or a mixed gas thereof. A heat treatment method for a silicon wafer, wherein the heat treatment is performed at 600 to 850 ° C. for 120 to 250 minutes. 2. The heat treatment method according to claim 1, wherein the heat treatment is performed by forming a polysilicon layer on the back surface of the silicon wafer by a chemical vapor deposition method.