JP2001155495A - Probe test device and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a probe test device and its method which can easily analyze a main cause of fail bit by obtaining information of fail bit for each step in which a different test pattern is given to a semiconductor device such as a semiconductor memory and the like. SOLUTION: This device is provided with a test pattern generating section generating a test pattern consisting of plural steps, a test pattern applying section, a test deciding section, an address conversion section, and plural expansion fail memory section storing pass/fail map information consisting of plural steps converted by the address conversion section distributing for each step.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a probe test apparatus for performing an electrical function test of a semiconductor memory device such as an LSI and a method thereof.

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open No. 7-22156 is known as a prior art of the probe test apparatus.
The FBM for the semiconductor memory described in this prior art
(Fail Bit Map: Fail bitmap)
Is the total probe test result. That is, the probe test result is Pass / Fail information of each bit composed of total OR information.

[0003]

However, in the above-mentioned prior art, it is necessary to obtain pass / fail information when a different test pattern is applied to the semiconductor memory for each step. Was not taken into account.

[0004] An object of the present invention is to solve the above problems.
An object of the present invention is to provide a probe test apparatus and method for acquiring fail bit information at each step of applying a different test pattern to a semiconductor device such as a semiconductor memory, and easily analyzing the cause of the fail bit. is there.

[0005]

In order to achieve the above object, the present invention provides a test for generating a test pattern including a plurality of different steps based on test conditions set for a semiconductor device to be tested. A pattern generation unit, and a test pattern including a plurality of steps generated by the test pattern generation unit is input to the semiconductor device,
A test pattern application unit for outputting a test result consisting of a plurality of steps based on the input; and a plurality of steps for comparing a characteristic value output from the pattern application unit as a test result consisting of a plurality of steps with an expected value. A test determination unit for obtaining pass / fail information, and an address conversion for performing address conversion on the pass / fail information including a plurality of steps determined by the test determination unit and outputting pass / fail map information including a plurality of steps Department and
A probe test apparatus comprising: a plurality of extended fail memory units that store pass / fail map information composed of a plurality of steps converted by the address conversion unit for each step and store the information.

Further, the present invention is characterized in that the probe test apparatus further comprises a display device for displaying pass / fail map information for each step stored in each of the plurality of extended fail memory units. I do. Also,
The present invention is characterized in that the probe test apparatus further includes a storage unit for storing a test name, a test date, and a set test condition at that time for the semiconductor device to be tested. Further, the present invention, in the probe test apparatus, further includes a storage unit for storing a test name, a test date, and a set test condition at that time for the semiconductor device to be tested, and stored in the storage unit. A test name, a test date, and a test condition at that time are displayed on the display device.

The present invention also provides a test pattern generating step for generating a test pattern including a plurality of different steps based on test conditions set for a semiconductor device to be tested, and a test pattern generating step for generating the test pattern. A test pattern application process of inputting a test pattern including a plurality of steps to the semiconductor device and outputting a test result including a plurality of steps based on the input, and a test result including a plurality of steps in the pattern application process. A test determining step of comparing the output characteristic value with an expected value to obtain pass / fail information including a plurality of steps;
An address conversion step of performing address conversion on the path / failure information composed of a plurality of steps determined in the test determination step and outputting pass / fail map information composed of a plurality of steps, and the address conversion step is performed in the address conversion step. A storing process of distributing pass / fail map information including a plurality of steps for each step and storing the information in each of the plurality of extended fail memory units; and a storing process for each of the steps stored in each of the plurality of extended fail memory units in the storing process. A display step of displaying pass / fail map information using a display device.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a probe test apparatus according to the present invention will be described with reference to the drawings.

First, a first embodiment of the probe test apparatus according to the present invention will be described with reference to FIGS. The first embodiment according to the present invention includes a test pattern generation unit 2 with a step number, a pattern application unit 3,
A test determination unit 4, an address conversion unit 5, a step number distribution unit 6, a fail memory unit 7 having a main fail memory unit 7a and a plurality of extended fail memory units 7b, and a CPU 8 for controlling the above units; As shown in FIG. 3, a display device 24 for outputting, an input device 23 for inputting various information, and a tester 1 to which CPUs 20 and 22 for controlling the display device 24 and the input device 23 are connected.

The test pattern generator 2 with a step number is formed of a test pattern of a plurality of steps different for each step number (for example, a test signal of a step as a step number 1 is formed from a write signal sequence of "1", The test pattern of the step as step number 2 is formed from a write signal string of “0”, and the test pattern of the step as step number 3 is formed from a write signal string of “1”, and the step as step number 4 Is generated from a write signal sequence of “0” as the test pattern of “.”, And the test name, test date, test condition, and the like at that time are stored in the storage device 21. Note that various test conditions are stored in the storage device 21 in advance as a test condition table. Therefore, various test conditions stored in the storage device 21 are displayed on the display device 24 by the EWS 20 or the like, and the test conditions can be selected in accordance with the test target on the screen, and the test conditions corresponding to the selected test conditions can be selected. In the form, the test name and the test date can be stored and set in the storage device 21 or the memory unit of the test pattern generation unit with step numbers. Accordingly, the test pattern with step number generation unit 2 can generate a test pattern for each step number based on the test conditions selected as described above.

The pattern applying unit 3 applies a test pattern of a plurality of steps different for each step number generated by the test pattern generating unit 2 with a step number to the DUT.
(Device Under Test: a semiconductor memory (for example, DRAM, SRA
M, FLASH, etc.)) Write (apply) to 10, DU
From T10, a step test result is read for each step number (for example, a signal string of “1” is read as step number 1, a signal string of “0” is read as step number 2, and a signal string of “0” is read as step number 3. The reading is performed by reading out a signal sequence of “1” as step number 4).

The test judging section 4 reads out a test pattern of a plurality of steps, which is different for each step number generated by the test pattern generating section 2 with the step number, and reads and measures the test pattern for each step number from the pattern applying section 3. The pass bit (good bit) and the fail bit (defective bit) are determined by comparing the test result of the step including the signal sequence to be performed, and are output as a pass / fail signal sequence.

The address conversion unit 5 outputs a pass / step of a step output from the test determination unit 4 for each step number.
For example, an address in the semiconductor memory is assigned to the fail signal sequence based on the design information (arrangement information, size information, etc.) of the semiconductor memory, and the pass / step of each step number is assigned.
It is configured to output file map information (data). The step number allocating unit 6 is a path / fail map information (data) of a step to which an address obtained from the address converting unit 5 for each step number is assigned.
Are arranged for each step number.

The fail memory unit 7 has extended fail memory units 7b1 to 7b for storing pass / fail map information of the steps assigned to each step number by the step number assigning unit 6 in association with the step numbers.
4 and a predetermined step for the pass / fail map information of the step for each step number stored in each of the extended fail memory sections 7b1 to 7b4 is an operation between the numbers, for example, when the fail bit is set to “1”. A main fail memory section 7a for storing total pass / fail map information obtained by taking a logical sum.

Next, a probe test apparatus according to a second embodiment of the present invention will be described with reference to FIGS. The difference between the second embodiment according to the present invention and the first embodiment is that the test pattern generation unit 2 with step numbers, the pattern application unit 3, the test determination unit 4, Tester 1 with address translation unit 5
The step number distribution unit 6, the fail memory unit 7, and the CPU 8 for controlling each unit and the output device 24 such as the input device 23 and the display device are connected to the tester 1 via the network 25 and the like. EW done
S (Engineering workstation) 20 or PC
(PC) 22 and the like. Incidentally, the fail memory unit 7 may be provided in the storage device 21. As described above, the fail memory unit 7 including the plurality of extended fail memory units 7b1 to 7b4 corresponding to the number of the step numbers is connected to the EWS 20 or the like.
At 0 or the like, the cause of the failure is analyzed based on the pass / fail bitmap information for each step number and the test pattern information for each step number in which test conditions are added. Accordingly, the test pattern with a step number generation unit 2 may be provided in the EWS 20 or the like, and may be configured to provide the test pattern for each step generated from the EWS 20 to the tester 1 via the network 25. By doing so, it is not necessary to obtain test pattern information for each step number in which test conditions are added from the tester 1 via the network 25.

FIG. 3 shows a system configuration of a probe test apparatus according to the present invention. That is, the system configuration of the probe test apparatus according to the present invention includes a tester 1, a DUT 10,
A storage device (may be configured to include the fail memory unit 7) 21, an EWS 20, a PC 22, an input device 23 used for selecting and confirming test conditions, and the like are stored in the extended fail memory units 7b1 to 7b. An output device 24, such as a display device for displaying and outputting the pass / fail bitmap information for each of the step numbers, is connected by a network 25.

Next, a DUT according to the present invention (semiconductor memory which is a semiconductor device: for example, DRAM, SRAM, FLA)
SH etc.) for the probe test for 10
This will be described with reference to FIG. That is, it is assumed that various test conditions for the DUT 10 have been input and stored in the storage device 21 in advance. First, when performing a probe test on a certain DUT 10, a test name (test number),
The test date and DUT (semiconductor memory) number, lot number, product type, etc.
Alternatively, it is input to the EWS 20. The tester 1 or the EWS 20 reads out from the database of various test conditions stored in the storage device 21 and displays it on the display device 24. The program creator looks at the displayed various test conditions and inputs the optimum one to the input device. By using the test name 23, the test name is entered in the memory unit of the test pattern generating unit 2 provided with the tester 1 or the EWS 20 in association with the test name (step S
41). The main computer that constitutes the test pattern generation unit 2 with a step number has a test pattern of a step in which a step number is inserted (given) for each step based on a measurement tool (for example, FBM) according to the selected test condition. (For example, a test pattern as a step number 1 is formed from a write signal string of “1”, a test pattern as a step number 2 is formed from a write signal string as “0”, and a test pattern as a step number 3 Is formed from a write signal string of “1”, and a test pattern as step number 4 is formed from a write signal string of “0” (Step S42), and the pattern applying section 3
Send to

Next, the pattern applying section 3 provided in the tester 1 inputs (writes) the waveform of the test pattern for each received step number to the device under test (DUT) 10 under the test name (write) ( Step S43).
Then, the pattern applying unit 3 reads the measurement result for each step number (for example, reads a signal string of “1” as step number 1, reads a signal string of “0” as step number 2, and reads “0” as step number 3. (Step S4), and reads out the signal sequence "1" as the step number 4.
4). Next, the test determination unit 4 provided in the tester 1
In the test name, for each step number, the measurement result obtained from the pattern applying unit 3 is compared with the expected value based on the test pattern in the above step, and data on the pass / fail of the test is obtained (step S45). This is used as the test result for the test name (step S46).

Next, the address conversion unit 5 provided in the tester 1 applies, for example, a semiconductor memory to the test result (pass / fail signal sequence) obtained from the test determination unit 4 for each step number in the test name. Is converted into an address on the semiconductor memory based on the design information of
Output. Then, the step number allocating unit 6 provided in the tester 1 or the EWS 20, etc., converts the test result (path) converted into an address on the semiconductor memory by the address converting unit 5 for each step number in the test name. / Fail map data) according to the step numbers, and each of the extended fail memory units 7
The data is stored and stored in b1 to b4 (step S48).
As described above, the processing of steps S44 to S48 for the test name is repeated until the final step number is obtained in step S49, so that the test consisting of the pass / fail map data whose address has been converted for each step number up to the final step number Results (for example, FIG. 6 (a)
Shown in ) Is stored in each of the extended fail memory units 7b1 to 7b4. In this way, by preparing the memory of the fail result hierarchically, it is possible to acquire the pass / fail information of each step number.

The above test is performed for a plurality of DUs to be tested.
Performed on T10, in a state where a test name is given, a plurality of test results composed of pass / fail map data address-converted for each test object and for each step number over a plurality of test objects. Are stored in the extended fail memory section group. In one extended fail memory unit group, test results composed of pass / fail map data of which address is converted for each step number of one test object are stored. Naturally, the test names (test numbers), test dates, and test conditions at that time for the plurality of test objects are stored in the storage device 21 or the memory unit in the tester 1 in the storage device 21 or the internal memory unit. Will be.

Next, FIGS. 5 to 7 show the failure analysis performed by the CPU 8 based on the test result including the pass / fail map data stored in each of the plurality of extended fail memory groups for a plurality of test names. It will be described using FIG. That is, as shown in FIG. 5, first, based on the input signal of the already-tested list display from the input device 23, the CPU 8 causes the storage device 21 connected to the tester 1 or the internal memory unit to store the data in FIG. Is displayed on the display device 24, including a test name (test number), a test date, test conditions, and the like shown in (1) (step S51). The failure analyzer looks at the displayed list of already-tested tests, and clicks on the test name (test number) to be analyzed based on the date of the test and the contents of the test conditions using the input device 23. (Step S52), and the selected test name is input to the CPU 8. Then, the CPU 8 outputs a test result for each step number from the extended fail memory unit group corresponding to the selected test name and displays the result on the display device 24 (step S53). As a result, a pass / fail map for each step number shown in FIG. 6A is obtained for the selected test name. As shown in FIG. 6A, the test result of step number 1 (for example, when “1” is written and “1” is read) and the test result of step number 2 (for example, “0”
Is written and “0” is read)
The test result of step number 3 (for example, when “1” is written and “0” is read) and the test result of step number 4 (for example, when “0” is written and “1” is read) fail. It can be seen that the addresses of the bits are different. Therefore, by comparing the test pattern for each step number with the test result (FBM: fail bit map) for each step number, it is possible to determine the cause of the fail bit.

Next, in step S54, the CPU 8 performs an operation between desired step numbers, for example, a logical OR of fail bits. Then, the CPU 8 determines in step S5
In 5, when the calculation result between the desired step numbers is displayed on the display device 24, for example, a fail bit map shown in FIG. 6B is obtained. FIG. 6B shows a case where the logical sum (OR) of the fail bits is obtained over all the step numbers. As is clear from FIG. 6B, a fail bit map in which a fail bit has occurred in any of the step numbers is obtained. However, from now on, only the total test is known, making it difficult to determine the cause of the failure bit. This is because it is not possible to correspond to the test pattern for each step number.

Further, in order to cope with the manufacturing process, the CPU 8 in the EWS 20, the PC 22, or the like is provided with a foreign substance and defect map data obtained from the defect inspection apparatus such as a foreign substance inspection apparatus and a wiring pattern via the network 25, for example. The degree of coincidence within the allowable range of positional deviation is determined by comparing with the fail bit data for each of the step numbers, and the determined degree of coincidence is displayed on the display device 24 to determine the process factor that has become a fail bit. Can be determined.

[0024]

According to the present invention, fail bit information is obtained for each step of giving a different test pattern to a semiconductor device such as a semiconductor memory, and the cause of the fail bit can be easily analyzed. .

[Brief description of the drawings]

FIG. 1 is a functional configuration diagram showing a first embodiment of a probe test apparatus according to the present invention.

FIG. 2 is a functional configuration diagram showing a probe test apparatus according to a second embodiment of the present invention.

FIG. 3 is a schematic configuration diagram illustrating a system configuration of a probe test apparatus according to the present invention.

FIG. 4 is a diagram showing a test processing flow for storing and storing test results in an extended fail memory unit for each step number.

FIG. 5 is a diagram showing a flow of performing a failure analysis using test results stored and stored in an extended fail memory unit for each step number.

FIG. 6 is a diagram showing a test result (fail bit map) for each step number and a total fail result when all logical sums are obtained;

FIG. 7 is a diagram showing a list of already tested tests.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Tester, 2 ... Test pattern generation part with step number, 3 ... Pattern application part, 4 ... Test determination part, 5 ... Address conversion part, 6 ... Step number distribution part, 7 ... Fail memory part, 7a ... Main fail memory Part, 7b, 7
b1 to 7b4: Extended fail memory unit, 8: CPU, 1
0: DUT, 20: EWS (engineering workstation), 21: storage device, 22: PC (personal computer), 23: input device, 24: output device (display device).

Claims (5)

[Claims] A test pattern generation unit configured to generate a test pattern including a plurality of different steps based on test conditions set for a semiconductor device to be tested; and a plurality of test patterns generated by the test pattern generation unit. A test pattern application unit that inputs a test pattern consisting of steps to the semiconductor device and outputs a test result consisting of a plurality of steps based on the input; and a characteristic output from the pattern application unit as a test result consisting of a plurality of steps. A test determining unit that obtains pass / fail information including a plurality of steps by comparing a value with an expected value; and performs a plurality of address conversions on the pass / fail information including a plurality of steps determined by the test determining unit. An address translator for outputting pass / fail map information comprising steps, A probe test apparatus, comprising: a plurality of extended fail memory units that store converted pass / fail map information including a plurality of steps for each step. 2. A display device for displaying pass / fail map information for each step stored in each of the plurality of extended fail memory units.
The probe test device according to 1. 3. The probe test according to claim 1, further comprising a storage unit for storing a test name, a test date, and a set test condition at that time for the semiconductor device to be tested. apparatus. 4. A storage unit for storing a test name, a test date, and a set test condition at that time for the semiconductor device to be tested, wherein the test name stored in the storage unit is stored.
The probe test apparatus according to claim 2, wherein a test date and a test condition at that time are displayed on the display device. 5. A test pattern generating step for generating a test pattern comprising a plurality of different steps based on test conditions set for a semiconductor device to be tested, and a plurality of test patterns generated in the test pattern generating step. A test pattern applying step of inputting a test pattern comprising steps to the semiconductor device and outputting a test result comprising a plurality of steps based on the input; and a characteristic outputted as a test result comprising a plurality of steps in the pattern applying step. A test determination process for obtaining pass / fail information including a plurality of steps by comparing the value with an expected value; and performing a plurality of address conversions on the pass / fail information including a plurality of steps determined in the test determination process. An address conversion step of outputting pass / fail map information comprising a step; A storage step of distributing pass / fail map information comprising a plurality of steps converted in the address conversion step and storing the information in each of the plurality of extended fail memory sections; and storing each of the plurality of extended fail memory sections in the storing step. Displaying the pass / fail map information for each step stored in the display device using a display device.