JP2001142414A - Manufacturing method of electro-optical device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of an electro-optical device such as a liquid crystal device which is high in contrast and bright in display by reducing the alignment irregularities of electrochemical substance due to a step difference of a substrate surface and the alignment irregularities of the electro-optical substance due to a transverse electric field. SOLUTION: In the electro-optical device, a resist mask is formed on a TFT array substrate 10, and thereafter, an etching is performed in an etching gas environment containing oxygen, thereby, the resist mask is subjected to the etching and, at the same time, the surface of TFT array substrate 10 is subjected to the etching. As a result, a recessed part 201 which has a side surface part 202 which is a tapered surface is formed on the TFT array substrate 10 and, therefore, the region where data lines 6a are formed is flattened. Also, since in the TFT array substrate 10, a projecting part 301 which has a side surface part 302 which is a tapered surface is formed, in this region, a liquid crystal layer is made thin and the longitudinal electric field is strengthened, and the effect of the transverse electric field is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing an electro-optical device such as a liquid crystal device. More specifically, the present invention relates to a technique for manufacturing an electro-optical device such as an active matrix drive type liquid crystal device in which pixel electrodes are formed in a matrix.

[0002]

2. Description of the Related Art Generally, an electro-optical device such as a liquid crystal device has an electro-optical material such as a liquid crystal sandwiched between a pair of substrates.
The orientation state of the electro-optic material is defined by the properties of the electro-optic material and the orientation film formed on the surface of the substrate on the electro-optic material side. Therefore, if there is a step on the surface of the pixel electrode under the alignment film or on the surface of the interlayer insulating film that is the ground below the pixel electrode, and if there is a step on the surface of the alignment film due to this step, this step will be lost. Depending on the degree, poor alignment (disclination) occurs in the electro-optical material. When such an orientation defect occurs, it is difficult to drive the electro-optical material satisfactorily in this portion, and the contrast ratio is reduced due to light leakage of the electro-optical device.

However, in the case of a TFT active matrix driving type electro-optical device, various wirings such as scanning lines, data lines, and capacitance lines, and TFTs for controlling switching of pixel electrodes are provided on a TFT array substrate. Because it is formed in the
A step is inevitably generated on the surface of the alignment film depending on the existence of these wirings and elements.

Therefore, conventionally, a region on the substrate where such a level difference occurs corresponds to a gap between adjacent pixel electrodes, and is called a black mask or a black matrix provided on a counter substrate or a TFT array substrate. The region where such a step occurs due to the light-shielding film,
By covering the gap between the pixel electrodes, the electro-optic material part that produces goodness due to this step is not visible.
Alternatively, it does not contribute to display light.

Conventionally, such various wirings and TFs
In order not to generate a step itself due to the presence of T, an interlayer insulating film below the pixel electrode is made of, for example, an organic SOG (Spin On Gl).
A technique of flattening the ground below the pixel electrode by using a flattening film such as an ass) film has also been developed.

On the other hand, in this type of electro-optical device, in order to prevent deterioration of the electro-optical material due to application of a DC voltage and to prevent crosstalk and flicker in a displayed image, the potential polarity applied to each pixel electrode is regulated in a predetermined manner. The inversion drive method of inversion is adopted. In this inversion driving method, during the display corresponding to the image signal of one frame or field, the pixel electrodes arranged in the odd rows are driven at the positive potential with reference to the potential of the counter electrode, and the pixel electrodes arranged in the even rows are driven. The arrayed pixel electrodes are driven at a negative potential with reference to the potential of the counter electrode, and during the subsequent display corresponding to the image signal of the next frame or field, the pixels arranged in the even rows are reversed. The electrodes are driven at a positive potential and the pixel electrodes arranged in odd rows are driven at a negative potential. In this method, a method of inverting the polarity of such a potential in a frame or field cycle for each row while driving pixel electrodes in the same row with the same polarity potential is referred to as a 1H inversion driving method. Has been used as an inversion driving method which enables relatively high-quality image display. A method of inverting the polarity of such a potential in a frame or field cycle for each column while driving pixel electrodes in the same column with the same polarity potential is 1S.
This method is called an inversion drive method, and this method is also used as an inversion drive method that is relatively easy to control and enables high-quality image display.

[0007]

However, according to the technique of covering the step with the light-shielding film, the opening area of the pixel becomes narrow according to the area of the area having the step. For this reason, it is difficult to satisfy the basic requirement in the technical field of this type of electro-optical device of increasing the aperture ratio of pixels and displaying a brighter image in a limited image display area. In particular, the number of wires and the number of TFTs per unit area increase with the miniaturization of the pixel pitch for performing high-definition image display.
Due to a certain limit in miniaturization of the image, the proportion of the area having a step in the image display area becomes relatively high. , It gets worse.

On the other hand, according to the above-described technique of flattening the interlayer insulating film below the pixel electrode, no major problem occurs when adjacent pixel electrodes have the same polarity on the TFT array substrate. Like the 1H inversion driving method and the 1S inversion driving method, these voltages (that is, the voltages applied to the pixel electrodes adjacent to each other in the column direction in the 1H inversion driving method,
In the 1S inversion driving method, there is a problem when the phases of voltages (applied to the pixel electrodes adjacent to each other in the row direction) have opposite polarities. That is, when the interlayer insulating film below the pixel electrode is flattened, the distance between the pixel electrode and the counter electrode becomes wider near the edge of the pixel electrode located above the wiring or the TFT than when the flattening is not performed. There is a problem that a lateral electric field (that is, an electric field parallel to the substrate surface or an oblique electric field including a component parallel to the substrate surface) generated between adjacent pixel electrodes relatively increases. When such a horizontal electric field is applied to an electro-optical material in which a vertical electric field (ie, an electric field in a direction perpendicular to the substrate surface) between the pixel electrode and the counter electrode facing each other is assumed to be applied. , Poor alignment of the electro-optical material occurs,
It is said that light leakage or the like occurs in this portion and the contrast ratio is reduced.

On the other hand, it is possible to cover a region where a horizontal electric field is generated with a light-shielding film. However, in this case, there is a problem that an opening region of a pixel is narrowed in accordance with a width of a region where a horizontal electric field is generated. Occurs. In particular, such a horizontal electric field increases as the distance between adjacent pixel electrodes decreases due to the miniaturization of the pixel pitch. Therefore, these problems become more serious as the electro-optical device becomes finer. I will.

[0010] In view of the above problems, an object of the present invention is to provide:
High contrast and bright display can be achieved by reducing the poor orientation of the electro-optic material due to the step on the surface of the substrate facing the electro-optic material such as liquid crystal and the poor orientation of the electro-optic material due to the lateral electric field. To provide a method of manufacturing an electro-optical device such as a liquid crystal device.

[0011]

In order to solve the above-mentioned problems, the present invention provides a first substrate and a second substrate which face each other with an electro-optical material interposed therebetween, and a plurality of pixels provided on the first substrate. An electrode, and a method of manufacturing an electro-optical device having an opposing electrode provided on the second substrate facing the pixel electrode, wherein the unevenness is formed on a base surface located below the pixel electrode. Among the boundary regions between the pixel electrodes, the layer thickness of the electro-optical material in a pair of boundary regions opposed to each other across the pixel electrode is determined by the thickness of the electro-optical material in another pair of boundary regions opposed to each other across the pixel electrode. In forming the unevenness while making the layer thinner than the layer thickness, the mask is formed on the surface of the base surface while etching is performed on the base surface while removing the mask by etching. And performing.

In the present invention, the plurality of pixel electrodes include:
There may be a first pixel electrode group for inversion driving at a first period and a second pixel electrode group for inversion driving at a second period complementary to the first period. . In this case, in the boundary region between the pixel electrodes, the layer thickness of the electro-optical material in the boundary region between the pixel electrode belonging to the first pixel electrode group and the pixel electrode belonging to the second pixel electrode group. Is thinner than a boundary region between pixel electrodes belonging to the same pixel electrode group.

According to the present invention, adjacent pixel electrodes are driven on the same substrate by drive voltages of opposite polarities at each time during inversion drive, and are driven by drive voltages of mutually identical polarities at each time during inversion drive. And adjacent pixel electrodes are present. These two types exist, for example, in an electro-optical device such as a matrix drive type liquid crystal device employing an inversion drive system such as the above-described 1H inversion drive system or 1S inversion drive system.

Here, in the present invention, the layer thickness of the electro-optical material on the peripheral region where the pixel electrodes belonging to the first pixel electrode group and the pixel electrodes belonging to the second pixel electrode group are adjacent to each other is the same. The pixel electrodes belonging to the group are formed to be thinner than the layer thickness of the electro-optical material on the adjacent peripheral region. For example, the ground below the pixel electrode on the first substrate is
In a region facing the gap between the pixel electrodes driven by the potentials of the opposite polarities, the unevenness is raised in a bank-like manner by the unevenness, and the pixel electrode is positioned such that the edge of the pixel electrode is located on the bank-like portion of the base surface. Are located. Accordingly, the distance between the vicinity of the edge of the pixel electrode located on the bank-like portion and the counter electrode is relatively shorter than other flat portions according to the height of the bank-like portion (irregularities). . Therefore, the vertical electric field generated between the pixel electrode and the counter electrode in the bank-like portion can be increased according to the distance thus shortened.

As described above, in the region where the horizontal electric field is generated, the vertical electric field can be made relatively strong with respect to the horizontal electric field by changing the layer thickness of the electro-optical material. Can be reduced. In addition, since a light-shielding film for hiding a portion of the electro-optical material having poor alignment can be made small, the aperture ratio of each pixel can be increased without causing image defects such as light leakage.

Further, in the region opposed to the gap between the adjacent pixel electrodes driven by the driving voltages of the same polarity at each time at the time of the inversion driving, the influence of the lateral electric field is small or there is no influence. By forming irregularities on the ground below the pixel electrode, the alignment film can be flattened, and adverse effects due to steps on the surface of the pixel electrode can be reduced.

Therefore, according to the present invention, the contrast ratio is high, and the bright and high quality is achieved by comprehensively reducing the poor orientation of the electro-optical material due to the lateral electric field and the poor orientation of the electro-optical material due to the step. Can be displayed.

Further, in the present invention, irregularities are formed on the underlying surface by etching the underlying surface while removing the mask by etching. Therefore, the region not covered by the mask is etched first, and the region covered by the end of the mask is etched shallowly as the etching of the mask proceeds. For this reason,
According to the present invention, the edge portion of the unevenness has a gentle shape like a tapered surface. Therefore, even if a wiring or the like passes over such unevenness, disconnection does not occur. Also, a gentle shape may be obtained by removing a small amount of the edge portion of the unevenness by wet etching.

In the present invention, it is preferable to use a multi-tiered mask as the mask. When a mask having such a structure is used, the etching depth can be changed in each of a region where a mask is not formed, a region where a mask is thin, and a region where a mask is thick. Therefore, the surface of the pixel electrode can be flattened in accordance with the state of the steps on the upper layer side and the lower layer side, and conversely, a predetermined height can be provided on the pixel electrode surface.

In forming such a mask, for example, after forming a lower layer side mask, an upper layer side mask may be laminated on the lower layer side mask in a different pattern from the lower layer side mask.

In this case, it is preferable that one of the lower layer side mask and the upper layer side mask is formed of a positive photoresist and the other mask is formed of a negative photoresist. That is, it is preferable that the lower layer mask and the upper layer mask are formed from different types of photoresist. With this configuration, when forming the upper mask, the solvent does not deteriorate the lower mask.

In the present invention, when a resist mask is formed as the mask and the base surface is etched through the mask, it is preferable to perform dry etching using, for example, an etching gas containing oxygen. With this configuration, the base surface can be etched while etching the resist mask with oxygen in the etching gas.

In the present invention, the base surface may be, for example,
This is the surface of the first substrate. Further, the base surface may be a surface of an insulating film such as a base insulating film or an interlayer insulating film formed on a surface side of the first substrate.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. In each of the following embodiments, the electro-optical device of the present invention is applied to a liquid crystal device.

First Embodiment (Overall Configuration) FIG. 1 shows an equivalent circuit of various elements, wirings, etc. in a plurality of pixels formed in a matrix forming an image display area of the electro-optical device of the present embodiment. is there. FIG.
FIG. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which electric data lines, scanning lines, pixel electrodes, and the like shown in FIG. 1 are formed in the electro-optical device of the present embodiment. FIG. 3 is an explanatory diagram showing, in the boundary region between the pixels shown in FIG. 2, a region in which a concave portion is formed on a base surface located below a pixel electrode, with hatching obliquely to the right. FIG. 4 is an explanatory diagram showing, in the boundary region between the pixels shown in FIG. 2, a region in which a convex portion is formed on a base surface located below a pixel electrode, with hatching diagonally downward to the right. 5 is a sectional view taken along the line AA ′ of FIG. 2, FIG. 6 is a sectional view taken along the line BB ′ of FIG.
FIG. 3 is a sectional view taken along the line CC ′ of FIG. 2. FIG. 8 is an explanatory diagram showing a relationship between a potential polarity in each pixel electrode and a region where a lateral electric field is generated in an electro-optical device employing a 1H inversion driving method. FIGS. 9A to 9C are explanatory diagrams each showing a state of alignment of liquid crystal molecules when a TN liquid crystal is used. In each of the drawings, the scale of each layer and each member is different in order to make each layer and each member have a size recognizable in the drawings.

In FIG. 1, a plurality of pixels formed in a matrix and constituting an image display area of the electro-optical device according to the present embodiment include a pixel electrode 9a and a TFT 30 for controlling the pixel electrode 9a. And a data line 6a to which an image signal is supplied is connected to the TF
It is electrically connected to the source of T30. Data line 6
The image signals S1, S2,..., Sn to be written to a may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 6a for each group. Also, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are applied to the scanning line 3a in a pulsed manner in this order at a predetermined timing. It is configured. The pixel electrode 9a is electrically connected to the drain of the TFT 30. By closing the switch of the TFT 30, which is a switching element, for a certain period, the image signals S1, S2,... Write at a predetermined timing. The image signals S1, S2,..., Sn of a predetermined level written in the liquid crystal as an example of the electro-optical material via the pixel electrode 9a are transmitted between the pixel electrode 9a and a counter electrode (described later) formed on a counter substrate (described later). For a certain period. The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gray scale display. In the normally white mode, the incident light cannot pass through the liquid crystal portion according to the applied voltage. In the normally black mode, the incident light passes through the liquid crystal portion according to the applied voltage. Light having a contrast according to the image signal is emitted from the electro-optical device as a whole. Here, in order to prevent the held image signal from leaking, the storage capacitor 7 is connected in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode.
0 is added.

In this embodiment, the driving is performed by using the 1H inversion driving method described later with reference to FIG. As a result, it is possible to perform image display with reduced flicker occurring in the frame or field cycle and particularly reduced vertical crosstalk while avoiding deterioration of the liquid crystal due to the application of the DC voltage.

In FIG. 2, a plurality of transparent pixel electrodes 9 are arranged in a matrix on a TFT array substrate of an electro-optical device.
a (the outline is indicated by a dotted line portion 9a ′), and the data line 6a, the scanning line 3a, and the capacitor line 3b are provided along the vertical and horizontal boundaries of the pixel electrode 9a. The data line 6a is electrically connected via a contact hole 5 to a source region described later in the semiconductor layer 1a made of, for example, a polysilicon film. The pixel electrode 9a is electrically connected to a drain region described later in the semiconductor layer 1a via the contact hole 8. In addition, the channel region 1 of the semiconductor layer 1a, which is indicated by a hatched region falling rightward in FIG.
The scanning line 3a is arranged so as to face a ′, and the scanning line 3a functions as a gate electrode. As described above, pixel switching TFTs 30 in which the scanning lines 3a are opposed to each other as gate electrodes in the channel region 1a 'are provided at intersections of the scanning lines 3a and the data lines 6a.

The capacitance line 3b has a main line extending substantially linearly along the scanning line 3a, and a protruding portion protruding upward in the drawing along the data line 6a from a position intersecting the data line 6a.

As will be described later in detail, in the present embodiment, as shown in FIG. 3, a region along each data line 6a (a region shown by oblique lines rising to the right in FIG. 3) on the TFT array substrate. , A plurality of stripe-shaped concave portions 201 are provided. Thus, a flattening process is performed on the data line 6a. Further, in the present embodiment, as shown in FIG. 4, on the TFT array substrate, a region where each scanning line 3a, each capacitance line 3b, and each TFT 30 are formed in a region sandwiched by the data lines 6a. (Fig. 4
The region shaded in the middle and lower right) is the pixel electrode 9a
There are provided a plurality of convex portions 301 higher than the region where is formed.

In FIG. 5, the electro-optical device has a transparent T
It includes an FT array substrate 10 and a transparent counter substrate 20 disposed opposite to the FT array substrate 10. The TFT array substrate 10
For example, a quartz substrate, a glass substrate, a silicon substrate,
The opposite substrate 20 is made of, for example, a glass substrate or a quartz substrate. The pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film 16 on which a predetermined alignment process such as a rubbing process is performed is provided above the pixel electrode 9a. The pixel electrode 9a is made of, for example, a transparent conductive thin film such as an ITO (Indium Tin Oxide) film. The alignment film 16 is made of, for example, an organic thin film such as a polyimide thin film.

On the other hand, a counter electrode 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 on which a predetermined alignment process such as a rubbing process is performed is provided below the counter electrode 21. I have. The counter electrode 21 is made of, for example, a transparent conductive thin film such as an ITO film. The alignment film 22 is made of an organic thin film such as a polyimide thin film.

Each pixel electrode 9 is provided on the TFT array substrate 10.
A pixel switching TFT 30 that controls switching of each pixel electrode 9a is provided at a position adjacent to the pixel electrode 9a.

The opposing substrate 20 is further provided with a light shielding film 23 generally called a black mask or a black matrix in a non-opening region of each pixel. For this reason,
The incident light from the side of the counter substrate 20 is a pixel switching TF.
It does not enter the channel region 1a ', the low concentration source region 1b, and the low concentration drain region 1c of the semiconductor layer 1a at T30. Further, the light shielding film 23 improves the contrast,
It has a function of preventing color mixture of color materials when a color filter is formed. In the present embodiment, the light-shielding data line 6a made of aluminum or the like is used to shield a portion of the non-opening area of each pixel along the data line 6a, so that the data line 6a of the opening area of each pixel is light-shielded. May be defined, or the non-opening area along the data line 6a may be redundantly or solely used for the counter substrate 20.
May be configured to shield light with the light-shielding film 23 provided in the device.

In the electro-optical device thus configured, a space between the TFT array substrate 10 and the opposing substrate 20 where the pixel electrode 9a and the opposing electrode 21 face each other is surrounded by a sealing material described later. A liquid crystal, which is an example of an electro-optical material, is sealed in the space, and a liquid crystal layer 50 is formed. The liquid crystal layer 50 assumes a predetermined alignment state by the alignment films 16 and 22 when no electric field is applied from the pixel electrode 9a. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several kinds of nematic liquid crystals are mixed. The sealing material is T
An adhesive made of, for example, a photo-curing resin or a thermosetting resin for bonding the FT array substrate 10 and the counter substrate 20 around the periphery thereof, and a glass fiber or a glass fiber for setting a distance between both substrates to a predetermined value. Gap material such as glass beads is mixed.

Further, a base insulating film 12 is provided between the TFT array substrate 10 and the plurality of pixel switching TFTs 30.
Is provided. The base insulating film 12 is formed on the entire surface of the TFT array substrate 10 to prevent deterioration of the characteristics of the pixel switching TFT 30 due to roughness at the time of polishing the surface of the TFT array substrate 10 or contamination remaining after washing. Having. The base insulating film 12 is made of, for example, NS.
It is made of a highly insulating glass such as G (non-doped silicate glass), PSG (phosphosilicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), a silicon oxide film, a silicon nitride film, or the like.

In this embodiment, the semiconductor layer 1a extends from the high-concentration drain region 1e to form a first storage capacitor electrode 1f, and a part of the capacitor line 3b facing the first storage capacitor electrode 1f serves as a second storage capacitor electrode. The insulating thin film 2 including the film is connected to the scanning line 3a.
The storage capacitor 70 is formed by extending from a position facing the substrate and forming a dielectric film sandwiched between these electrodes.

The pixel switching TFT 30 is an LDD
(Lightly Doped Drain) structure and scanning line 3
a, a channel region 1a 'of a semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a, an insulating thin film 2 including a gate insulating film for insulating the scanning line 3a from the semiconductor layer 1a, a data line 6a, and a semiconductor layer 1a low concentration source region 1
b and a low-concentration drain region 1c, a high-concentration source region 1d of the semiconductor layer 1a, and a high-concentration drain region 1e. A plurality of pixel electrodes 9 are provided in the high-concentration drain region 1e.
A corresponding one of the “a” is connected via a contact hole 8. On the scanning line 3a and the capacitor line 3b, a first interlayer insulating film 4 having a contact hole 5 leading to the high-concentration source region 1d and a contact hole 8 leading to the high-concentration drain region 1e is formed. I have. Further, a second interlayer insulating film 7 having a contact hole 8 to the high-concentration drain region 1e is formed on the data line 6a and the first interlayer insulating film 4. The above-described pixel electrode 9a is provided on the upper surface of the second interlayer insulating film 7 configured as described above.

In this embodiment, the pixel switching TFT 30 has an LDD structure, but may have an offset structure in which impurity ions are not implanted into the low-concentration source region 1b and the low-concentration drain region 1c. A self-aligned TFT in which impurity ions are implanted at a high concentration using the gate electrode formed as a part of the gate electrode 3a as a mask to form high-concentration source and drain regions in a self-aligned manner may be used. In the present embodiment, the gate switching TFT 30 has a single gate structure in which only one gate electrode is disposed between the high-concentration source region 1d and the high-concentration drain region 1e, but two or more gate electrodes are provided between them. It may be arranged. When a TFT is formed with a dual gate or a triple gate or more as described above, a leak current at a junction between a channel and a source / drain region can be prevented, and a current in an off state can be reduced.

As shown in FIG. 6, a data line 6a is provided in a non-opening area of each pixel located in a gap between pixel electrodes 9a adjacent to each other on the left and right in FIG. The portion along the data line 6a in the outline of the opening region is defined, and light leakage in the non-opening region is prevented by the data line 6a. The data line 6
A storage capacitor 70 is formed under the line a by using a portion of the capacitance line 3b protruding below the data line 6a from the main line, thereby effectively utilizing the non-opening region.

(Measures for Steps and Transverse Electric Field) As shown in FIGS. 3 and 6, in this embodiment, the TFT array substrate 1
A plurality of recesses 201 are provided in the region along each data line 6 a including each data line 6 a and each TFT 30 on 0.

In the present embodiment, the concave portion 201 is formed on the surface of the TFT array substrate 10 (underlying surface in the present embodiment) in the lower layer side of the pixel electrode 9a.
Is reflected on the surface of the interlayer insulating film 7, so that the data line 6a and the TFT 30 are subjected to a flattening process. The side surface portion 202 of the concave portion 201 has a tapered surface, and this tapered surface is also reflected on the surface of the interlayer insulating film 7.

As shown in FIG. 7, a scanning line 3a and a capacitance line 3b are provided in a non-opening area of each pixel located in a gap between vertically adjacent pixel electrodes 9a in FIG. The light-shielding film 23 provided at 20 defines a portion of the contour of the opening area of each pixel along the scanning line 3a, and the light-shielding film 23 prevents light leakage in the non-opening area.

In this embodiment, the scanning lines 3a and the capacitance lines 3
The recess 201 is not formed in the region along the line b. In the region where the scanning line 3a and the capacitance line 3b pass, a protrusion 301 is formed between the pixel electrodes 9a so as to protrude like a bank. In the present embodiment, the edge of the pixel electrode 9a is formed on the projection 301.

In the present embodiment, the protrusion 301 is also formed on the surface of the TFT array substrate 10 (underlying surface in the present embodiment) in the lower layer side of the pixel electrode 9a.
Since 01 is reflected on the surface of the interlayer insulating film 7, the thickness of the liquid crystal layer 50 in this region is reduced. Further, the side surface portion 302 of the convex portion 301 has a tapered surface, and this tapered surface is also reflected on the surface of the interlayer insulating film 7.

Referring to FIG. 8, 1 employed in this embodiment will be described.
The relationship between the potential polarity of the adjacent pixel electrode 9a and the region where the horizontal electric field is generated in the H inversion driving method will be described.

As shown in FIG. 8A, during the period of displaying the image signal of the n-th field or frame (where n is a natural number), the liquid crystal driving potential indicated by + or-for each pixel electrode 9a. Are not inverted, and the pixel electrodes 9a are driven with the same polarity for each row. Thereafter, as shown in FIG. 8B, when displaying the image signal of the (n + 1) th field or one frame, the potential polarity of the liquid crystal driving potential in each pixel electrode 9a is inverted, and the (n + 1) th field or one frame of the one frame is displayed. During the period when the image signal is displayed,
The polarity of the liquid crystal drive potential indicated by + or-is not inverted for each pixel electrode 9a, and the pixel electrodes 9a are driven with the same polarity for each row. Then, the states shown in FIGS. 8A and 8B are repeated at a cycle of one field or one frame, and the driving by the 1H inversion driving method in the present embodiment is performed. As a result, according to the present embodiment, image display with reduced crosstalk and flicker can be performed while avoiding deterioration of the liquid crystal due to the application of the DC voltage. Note that the 1H inversion driving method is advantageous in that there is almost no vertical crosstalk as compared with the 1S inversion driving method.

As can be seen from FIGS. 8A and 8B, in the 1H inversion driving method, the horizontal electric field generation region C1 always has a gap between the pixel electrodes 9a adjacent in the vertical direction (Y direction). It will be near.

Therefore, in the present embodiment, as shown in FIGS. 3 and 7, a convex portion 301 is formed in a region along the scanning line 3a, and the vicinity of the edge of the pixel electrode 9a disposed on the convex portion 301 is formed. To increase the vertical electric field. That is, as shown in FIG. 7, the distance d1 between the vicinity of the edge of the pixel electrode 9 a disposed on the protrusion 301 and the counter electrode 21 is reduced by the step (height) of the protrusion 301.

On the other hand, as shown in FIG. 6, the data line 6a is subjected to a flattening process by the concave portion 201, and the concave portion 201 allows the vicinity of the edge of the pixel electrode 9a and the counter electrode 21 to be formed. The distance d2 between them is substantially equal to the distance D between the pixel electrode 9a and the counter electrode 21 in the central region occupying most of the pixel electrode 9a.

Here, the distance d2 between the vicinity of the edge of the pixel electrode 9a in the flattened portion and the counter electrode 21 is defined by the following formula: d2 + 300 nm ≧ substantially above the center of the pixel electrode 9a. The relationship indicated by D is established. That is, in a region where a horizontal electric field is not generated, if a step of 300 nm or more occurs between the liquid crystal cell gap D and the liquid crystal, a light leakage may occur.

By configuring the electro-optical device in this way, the vertical electric field between the pixel electrode 9a and the counter electrode 21 can be increased in the horizontal electric field generation region C1 shown in FIG. Further, in FIG. 7, even if the distance d1 is reduced, the gap W between the adjacent pixel electrodes 9a is reduced.
Since 1 is constant, the magnitude of the transverse electric field that increases as the gap W1 becomes narrower is also constant. Therefore, the vertical electric field can be locally strengthened more than the horizontal electric field in the horizontal electric field generation region C1 shown in FIG. 8, and as a result, the vertical electric field becomes more dominant. This makes it possible to prevent the alignment defect of the liquid crystal in C1.

As shown in FIG. 6, since the data line 6a is subjected to a flattening process, the occurrence of defective alignment of the liquid crystal due to the step due to the data line 6a and the like is reduced in this portion. It is possible. Here, since the flattening process is performed, the vertical electric field is not strengthened by reducing the distance d2 between the pixel electrode 9a and the counter electrode 21, but in this portion, as shown in FIG. No horizontal electric field is generated between the pixel electrodes 9a adjacent to each other. Therefore, in this portion, the alignment state of the liquid crystal can be extremely improved by the flattening treatment without taking measures against the lateral electric field.

As described above, according to the present embodiment, 1H
Paying attention to the characteristics of the horizontal electric field generated in the inversion driving method, by arranging the edge of the pixel electrode 9a on the convex portion 301 in the horizontal electric field generation region C1, the vertical electric field is strengthened, thereby reducing the adverse effect due to the horizontal electric field. At the same time, in a region where a horizontal electric field does not occur, the flattening is performed, thereby reducing the adverse effect due to the step on the surface of the pixel electrode 9a. In this way, by reducing the defective alignment of the liquid crystal due to the lateral electric field and the defective alignment of the liquid crystal due to the step, the light shielding film 23 for hiding the defective alignment of the liquid crystal can be small. Therefore, it is possible to increase the aperture ratio of each pixel without causing image quality defects such as light leakage (and the like), and finally, it becomes possible to display a bright image with a high contrast ratio and high quality.

Further, according to the present embodiment, the side surfaces 302 and 202 of the convex portion 301 and the concave portion 201 formed for comprehensively reducing the liquid crystal alignment defect due to the lateral electric field and the liquid crystal alignment defect due to the step. Has a tapered surface, so that even if the wiring passes over these convex portions 301 and concave portions 201, no disconnection occurs in the wiring.

According to the study of the present inventor, the thickness of the liquid crystal layer 50 maintains the light resistance at a certain level, does not make the injection process of the liquid crystal 50 difficult, and the liquid crystal molecules are formed by the application of an electric field during operation. In order to work well,
A certain layer thickness (for example, about 3 μm according to the current technology) is required. On the other hand, the gap W1 (see FIG. 7) between the adjacent pixel electrodes 9a is
a and shorter than the distance d1 between the counter electrode 21 (ie, W
It has been found that when 1 <d1), the adverse effect due to the lateral electric field starts to appear. Therefore, if the layer thickness D (see FIGS. 6 and 7) of the liquid crystal layer 50 is simply reduced as a whole in order to increase the aperture ratio of the fine pitch pixels, it becomes difficult to control the liquid crystal layer thickness. The light resistance may be reduced, the injection process may be difficult, and the liquid crystal molecules may malfunction. Conversely, in order to increase the aperture ratio of fine pitch pixels, the liquid crystal layer 5
If the gap W1 between the pixel electrodes 9a adjacent to each other is simply narrowed without reducing the value of 0, the horizontal electric field becomes larger than the vertical electric field, and thus the poor alignment of the liquid crystal due to the horizontal electric field becomes apparent. Considering the characteristics of such a liquid crystal device, the layer thickness d1 of the liquid crystal layer 50 (for example, 1.
The thickness of the liquid crystal layer 50 is reduced in the other region occupying most of the pixel electrode 9a.
Is not narrowed, the layer thickness D in the light transmission region of the liquid crystal layer 50 can be sufficiently ensured (for example, about 3 μm), and the gap between the adjacent pixel electrodes 9a can be increased while the lateral electric field is not relatively increased. The configuration in which W1 is narrowed is very effective in increasing the aperture ratio of pixels with fine pitches and increasing the definition of a display image.

In this embodiment, in particular, in FIG. 7, the pixel electrodes 9a are preferably arranged in a plane so as to satisfy the relationship expressed by the following expression: 0.5D <W1. This is because the liquid crystal layer thickness D is equal to the distance W1 between the pixel electrodes 9a.
If the control is not performed twice or more, poor alignment of the liquid crystal due to the lateral electric field becomes apparent.

Further, the convex portion 301 is formed so as to satisfy the following relationship: d1 + 300 nm (nanometer) ≦ D. That is, if the protrusion 301 is raised to a level difference of 300 nm or more, the vertical electric field in this region can be made larger than the horizontal electric field to such an extent that the adverse effect due to the horizontal electric field does not actually surface.

Further, in order to increase the aperture ratio of the fine pitch pixels and increase the definition of the display image, the gap W1 or the gap W
It is effective to make the gap W1 as small as possible. However, in order to prevent the adverse effect of the lateral electric field from becoming apparent, the gap W1
Cannot be reduced. Here, setting the gap W1 small until W1 ≒ d1 is most effective for increasing the aperture ratio of pixels with fine pitch without deteriorating image quality.

Further, in the present embodiment, it is preferable that the edge of the pixel electrode 9a is located at the edge in the width direction of the longitudinally extending upper surface of the protrusion 301. With this configuration, the peripheral portion within the pixel electrode 9a and the counter electrode 21
Can be shortened by making maximum use of the height of the convex portion 301. At the same time, the width W1 between adjacent pixel electrodes 9a where a horizontal electric field is generated can be reduced by making the best use of the width of the upper surface of the protrusion 301. Thus, the vertical electric field can be strengthened relative to the horizontal electric field in the horizontal electric field generation region C1 by utilizing the shape of the convex portion 301 very efficiently.

Here, as shown in FIG. 9B, in the present embodiment, preferably, the liquid crystal layer 50 is formed of a TN (Twisted Nemati).
c) It is composed of liquid crystal, and the side surface of the projection 301 is tapered. Moreover, it is preferable that the inclination direction of the pretilt angle θ of the TN liquid crystal on the TFT array substrate 10 and the inclination direction of the taper be matched.

That is, as shown in FIG. 9 (a), the liquid crystal molecules 50a of the TN liquid crystal have the respective liquid crystal molecules 5a when no voltage is applied.
0a is basically in a state substantially parallel to the substrate surface,
In addition, in the state where the liquid crystal molecules are oriented so as to be gradually twisted from the TFT array substrate 10 toward the opposing substrate 20 and a voltage is applied,
As indicated by arrows, each liquid crystal molecule 50a is aligned so as to rise vertically from the substrate surface. Therefore, FIG.
As shown in (b), if the side surface of the convex portion 301 is tapered, and if the inclination direction of the pretilt angle θ of the TN liquid crystal and the inclination direction of the taper are aligned, the convex portion 301 and the counter substrate are aligned. 20 and the liquid crystal layer thickness d
1 gradually decreases along the side surface, but the liquid crystal layer thickness D
, A good liquid crystal alignment state close to the case where is constant is obtained. That is, it is possible to suppress as much as possible the liquid crystal alignment defect caused by the step caused by the presence of the convex portion 301 which reduces the liquid crystal alignment defect caused by the lateral electric field. If the inclination direction of the pretilt angle θ of the TN liquid crystal and the inclination direction of the taper are not aligned as shown in FIG. 9C, other liquid crystal molecules may be located between the convex portion 301 and the counter substrate 20. Liquid crystal molecules 50b rising in the direction opposite to the direction of 50a are generated in the vicinity of the convex portion 301, thereby causing a liquid crystal alignment defect in which the alignment state is discontinuous. Therefore, such a region is preferably hidden by forming a light shielding film on the opposing substrate 20 or the TFT array substrate 10.

(Manufacturing Process) Next, a manufacturing process of the TFT array substrate constituting the electro-optical device having the above configuration will be described with reference to FIGS.

FIGS. 10A to 10E respectively show the TFT array substrate 10 used in the electro-optical device according to the present embodiment.
11A to 11C are process cross-sectional views illustrating a method of manufacturing the semiconductor device of FIG.
11E is a process cross-sectional view illustrating a process performed after the process illustrated in FIGS. 10A to 10E in manufacturing the electro-optical device of the embodiment. 10 and 11
6 is a cross-sectional view taken along the line BB ′ of FIG. 2 and FIG.
Are shown corresponding to the CC ′ cross section of FIG.

First, as shown in FIG. 10A, a TFT array substrate 10 such as a quartz substrate, a hard glass substrate, or a silicon substrate is prepared, and a lower resist mask 501 is formed on the surface thereof by using photolithography. Form. The lower resist mask 501 is formed on the data line 6a.
A region along which the concave portion 201 is to be formed is an opening portion 502.

Next, as shown in FIG. 10B, the lower resist mask 501 is formed by using a photolithography technique.
The upper resist mask 505 having a pattern different from that of the lower resist mask 501 is formed on the surface of. The resist mask 505 is formed in a region where the projection 301 is to be formed along the scanning line 3a and the capacitance line 3b.

As a result, on the surface of the TFT array substrate 10, a resist mask 50 in which a lower resist mask 501 and an upper resist mask 505 are stacked in two stages.
8 are formed. Here, the lower resist mask 501
One of the upper and lower resist masks 505 is formed of a positive photoresist, and the other is formed of a negative photoresist.
When the mask is made of a photoresist having completely different properties as described above, when the upper resist mask 505 is formed, the lower resist mask 50 is formed by the solvent or the like.
1 can be prevented from deteriorating.

Next, as shown in FIG. 10C, dry etching is performed on the TFT array substrate 10 via the resist mask 508. At this time, oxygen is contained in the etching gas. As a result, the TFT array substrate 10 is etched from a region where the resist mask 508 is not formed. Further, as the etching proceeds, the resist mask 508 is also etched by oxygen in the etching gas. As a result, the mask 5
8 becomes thinner, and the end 509 of the resist mask 508 recedes. Therefore, the resist mask 5
After the thin portion (the portion where only the lower resist mask 501 is formed) of the resist mask 508 is removed by etching, as shown in FIG.
The surface of the TFT array substrate 10 covered with the thin portion is also etched. Further, the end portion 509 of the resist mask 508 recedes, thereby forming the resist mask 50.
The portion covered by the end 509 of 8 is tapered and etched. Therefore, as shown in FIG. 10E, the side surface portion 202 of the concave portion 201 has a three tapered surface.

On the other hand, the thick portion of the resist mask 508 (the region having a two-layer structure of the lower resist mask 501 and the upper resist mask 505) is not etched until the end of the etching. However, the mask 58
The end 5 of the upper-layer resist mask 505 is
06 (see FIG. 10 (c))
After the lower resist mask 501 is removed by etching, etching is performed by retreating the end 506 of the upper resist mask 505. Therefore, as shown in FIG. 10E, the side surface portion 302 of the convex portion 301 has a tapered surface.

When etching is performed in this manner, as can be seen by comparing FIGS. 10B and 11A, the surface of the TFT array substrate 10 is covered with the resist mask 508 from the beginning. The recessed portion 201 having a tapered side surface portion 202 is formed in the region where no portion is present. Also,
A region covered with a thick portion of the resist mask 508 (a region having a two-layer structure of the lower resist mask 501 and the upper resist mask 505) has a side surface portion 302.
A convex portion 301 having a tapered surface is formed. On the contrary,
The area covered with the thin portion of the resist mask 508 (the portion where only the lower resist mask 501 is formed) is a portion having a substrate thickness between the concave portion 201 and the convex portion 301.

Next, as shown in FIG. 11B, the scanning lines 3a are formed on the TFT array substrate 10 by using a thin film forming technique.
And the capacitance line 3b. In parallel with this, the TFT 30 and the storage capacitor 70 shown in FIG. 3 are formed.

More specifically, the concave portion 201 and the convex portion 30
For example, on the TFT array substrate 10 after forming 1
TEOS (tetra-ethyl-ortho-silicate) gas, TEB (tetra-ethyl-borate) gas, TMOP (tetra-methyl
NSG, PS using oxyfoslate) gas
G, BSG, BPSG or other silicate glass film, silicon nitride film, silicon oxide film, etc.
A base insulating film 12 having a thickness of 0 to 2000 nm is formed. next,
An amorphous silicon film is formed on the base insulating film 12 by low-pressure CVD or the like, and an annealing process is performed to grow a polysilicon film in a solid phase. Alternatively, a polysilicon film is directly formed by a low pressure CVD method or the like without passing through the amorphous silicon film. Next, a semiconductor layer 1a having a predetermined pattern including the first storage capacitor electrode 1f as shown in FIG. 2 is formed by subjecting the polysilicon film to a photolithography step, an etching step and the like. Next, the TF shown in FIG.
An insulating thin film 2 including a dielectric film for forming a storage capacitor is formed together with the gate insulating film of T30. As a result, the semiconductor layer 1a
Has a thickness of about 30 to 150 nm, preferably about 3 nm.
The thickness of the insulating thin film 2 is about 2 to 50 nm.
0-150 nm thickness, preferably about 30-100 nm
Of thickness. Next, a polysilicon film is deposited to a thickness of about 100 to 500 nm by a low pressure CVD method or the like.
After the polysilicon film is made conductive by thermally diffusing (phosphorus), the scanning lines 3a and the capacitor lines 3b having a predetermined pattern as shown in FIG. 2 are formed by a photolithography process, an etching process, or the like. Note that the scanning line 3a and the capacitance line 3b
May be formed of a metal alloy film such as a refractory metal or a metal silicide, or may be a multilayer wiring in combination with a polysilicon film or the like. Next, by doping impurity ions in two steps of low concentration and high concentration, the low concentration source region 1b, the low concentration drain region 1c, and the high concentration source region 1c are doped.
The pixel switching TFT 30 having the LDD structure, including d and the high-concentration drain region 1e, is formed.

Incidentally, in the step shown in FIG.
The TFTs constituting the peripheral circuits such as the data line driving circuit and the scanning line driving circuit composed of the TFTs may be formed in the peripheral portion on the TFT array substrate 10.

Next, as shown in FIG.
a, a capacitor line 3b, an NSG, a PSG, a BSG, a NSG, a PSG, a
An interlayer insulating film 4 made of a silicate glass film such as BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. The interlayer insulating film 4 has a thickness of, for example, about 1000 to 2000 nm. Note that, in parallel with or before or after this thermal baking, an annealing process at about 1000 ° C. may be performed to activate the semiconductor layer 1a. Then, a contact hole 5 for electrically connecting the data line 6a shown in FIG. 3 to the high concentration source region 1d of the semiconductor layer 1a is formed in the first interlayer insulating film 4.
And a hole is formed in the insulating thin film 2, and the scanning line 3 a and the capacitor line 3
A contact hole for connecting b to a wiring (not shown) in the peripheral region of the substrate can also be formed in the same step as the contact hole 5. Subsequently, a low-resistance metal film such as aluminum or a metal silicide film is formed on the first interlayer insulating film 4 by a sputtering process or the like by about 100 to 100 nm.
After being deposited to a thickness of 500 nm, a data line 6a is formed by a photolithography process, an etching process, or the like.

Next, as shown in FIG. 11D, a second interlayer insulating film 7 is formed on the data line 6a. Further, as shown in FIG. 3, the pixel electrode 9a and the high-concentration drain region 1e
Is formed by dry etching such as reactive ion etching or reactive ion beam etching or wet etching. Subsequently, a transparent conductive thin film such as an ITO film is formed on the second interlayer insulating
The pixel electrode 9a is deposited to a thickness of 200 nm, and is further formed by a photolithography process, an etching process, and the like. When the electro-optical device is used as a reflection type, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as aluminum.

As described above, according to the manufacturing method of the present embodiment, the data lines 6a are formed by digging the recesses 201 in the TFT array substrate 10, and the data lines 6a are subjected to the flattening process and the scanning lines 3a are formed. In addition, the flattening process is not performed on the capacitor line 3b, and the convex portion 301 actively raises the volume. Therefore, in a region where no lateral electric field is generated, the concave portion 2 is formed.
01 reduces liquid crystal alignment defects caused by steps,
In a region where a horizontal electric field is generated, the convex portion 301 can reduce defective liquid crystal alignment due to the horizontal electric field.

In this embodiment, the resist mask 5
08 is formed in a two-stage structure of a lower resist mask 501 and an upper resist mask 505, and the resist mask 508 is used to etch the surface of the TFT array substrate 10 so that the side portions 202 and 302 are formed.
Are formed as a concave portion 201 and a convex portion 301 having a tapered surface. Therefore, even if wires are passed over the concave portion 201 and the convex portion 301, these wires do not break.

[Second Embodiment] FIGS. 12 to 14 show the configuration of an electro-optical device according to a second embodiment of the present invention.
This will be described with reference to FIG.

FIG. 12 is a cross-sectional view of the electro-optical device according to the present embodiment when cut at a position corresponding to the line AA ′ in FIG. 2, and FIG. 13 is a line BB ′ in FIG. FIG. 14 is a cross-sectional view corresponding to a cut at a position corresponding to FIG.
FIG. 3 is a cross-sectional view corresponding to a section taken along a line corresponding to line CC ′ in FIG. 2. In the electro-optical device according to the first embodiment, the concave portion 201 and the convex portion 301 are formed on the surface of the TFT array substrate 10, but the electro-optical device according to the present embodiment includes This is an example in which a concave portion 201 and a convex portion 301 are formed on the surface of a base insulating film 12. Other configurations are the same between the electro-optical device according to the first embodiment and the electro-optical device according to the present embodiment. Therefore, corresponding parts are denoted by the same reference numerals and description thereof will be omitted.

Also in the electro-optical device according to the present embodiment, as shown in FIGS. 3, 12, and 13, the data lines 6a and the regions along the data lines 6a including the TFTs 30 are formed on the TFT array substrate 10. A plurality of recesses 201 are provided.

However, in this embodiment, the recess 201
Are formed on the surface of the underlying insulating film 12 (the underlying surface in the present embodiment) in the lower layer side of the pixel electrode 9a, and the concave portions 201 are reflected on the surface of the interlayer insulating film 7, so that the data lines 6a Is subjected to a flattening process.
The side surface portion 202 of the concave portion 201 has a tapered surface, and this tapered surface is also reflected on the surface of the interlayer insulating film 7.

Also in this embodiment, as shown in FIGS. 4, 12, and 14, no recess 201 is formed in the region along the scanning line 3a and the capacitance line 3b, and the scanning line 3a
In the region where the capacitor line 3b passes, a convex portion 301 that rises like a bank is formed between the pixel electrodes 9a.

In this embodiment, the projection 301 is also formed on the surface of the underlying insulating film 12 (the underlying surface in the present embodiment) in the lower layer side of the pixel electrode 9a. , The thickness of the liquid crystal layer 50 in this region is reduced. Further, the side surface portion 302 of the convex portion 301 has a tapered surface, and this tapered surface is also reflected on the surface of the interlayer insulating film 7.

In the electro-optical device configured as described above, 1
Paying attention to the characteristics of the horizontal electric field generated in the H inversion driving method, in the horizontal electric field generation region C1, by arranging the edge of the pixel electrode 9a on the convex portion 301, the vertical electric field is strengthened, so that the adverse effect due to the horizontal electric field is reduced. Can be reduced. In a region where a horizontal electric field does not occur, the same effect as in the first embodiment can be obtained, for example, by performing flattening by the concave portion 201, thereby reducing an adverse effect due to a step on the surface of the pixel electrode 9a.

The T used in the electro-optical device having such a configuration is described below.
The manufacturing process of the FT array substrate will be described with reference to FIG.

In this embodiment, as shown in FIG. 15A, first, a TFT array substrate 10 such as a quartz substrate, a hard glass substrate, or a silicon substrate is prepared, and a base insulating film 12 is formed on the surface thereof.

Next, as shown in FIG. 15B, a lower resist mask 501 is formed on the surface of the base insulating film 12. The lower resist mask 501 is formed on the data line 6a.
A region along which the concave portion 201 is to be formed is an opening portion 502. Next, an upper resist mask 505 is formed on the surface of the lower resist mask 501. The resist mask 505 is formed in a region where the projection 301 is to be formed along the scanning line 3a and the capacitance line 3b. as a result,
On the surface of the TFT array substrate 10, a resist mask 508 in which a lower resist mask 501 and an upper resist mask 505 are stacked in two steps is formed.

Next, dry etching is performed on the surface of base insulating film 12 through resist mask 508.
At this time, oxygen is contained in the etching gas.
As a result, the surface of the base insulating film 12 is
08 is etched from the region where it is not formed. Further, as the etching proceeds, the resist mask 508 is also etched. As a result, the mask 58 becomes thinner, and the edge 5 of the resist mask 508 becomes thinner.
09 retreats. Therefore, after the thin portion (the portion on which only the lower-layer resist mask 501 is formed) of the resist mask 508 is removed by etching, the surface of the base insulating film 12 covered with the thin portion of the resist mask 508 also changes. Etched. When the end 509 of the resist mask 508 recedes, the portion covered by the end 509 of the resist mask 508 becomes a tapered surface and is etched. Therefore, the recess 201
Has a three tapered surface.

On the other hand, the thick portion of the resist mask 508 (the region having a two-layer structure of the lower resist mask 501 and the upper resist mask 505) is not etched until the end of the etching. However, the mask 58
The end 5 of the upper-layer resist mask 505 is
06, the lower resist mask 5
After 01 is removed by etching, etching is performed by retreating the end 506 of the upper resist mask 505. Therefore, the side surface portion 302 of the convex portion 301 has a three tapered surface.

When the etching is performed in this manner, as can be seen by comparing FIGS. 15B and 15C, the surface of the base insulating film 12 is covered with the resist mask 508 from the beginning. The area where there was no
A concave portion 201 having a tapered surface 2 is formed. Further, the thick portion of the resist mask 508 (the lower resist mask 50
In a region covered with the two-layer structure of the first and upper resist masks 505), a convex portion 301 having a tapered side surface portion 302 is formed. Further, a region covered with a thin portion of the resist mask 508 (a portion where only the lower layer resist mask 501 is formed) is a portion where the base insulating film 12 has a film thickness between the concave portion 201 and the convex portion 301. Becomes

Thereafter, basically, FIGS.
Steps similar to those described with reference to (d) are performed, and a description thereof will be omitted.

Third Embodiment Each of the first and second embodiments is an example of an electro-optical device employing the 1H inversion drive system. However, as in this embodiment, the 1S inversion drive system is employed. The present invention may be applied to an electro-optical device.

FIG. 16 is an explanatory diagram showing the relationship between the potential polarity of each pixel electrode and the region where a horizontal electric field is generated in the electro-optical device employing the 1S inversion driving method.

In the electro-optical device employing the 1S inversion driving method, as shown in FIG. 16A, during the period of displaying the image signal of the nth (where n is a natural number) field or frame, the pixel The polarity of the liquid crystal drive potential indicated by + or-is not inverted for each electrode 9a, and the pixel electrode 9a is driven with the same polarity for each column. Thereafter, as shown in FIG. 16B, when displaying the image signal of the (n + 1) th field or one frame, the polarity of the liquid crystal driving potential in each pixel electrode 9a is inverted, and the (n + 1) th field or one frame of the one frame is displayed. During the period in which the image signal is displayed, the polarity of the liquid crystal drive potential indicated by + or-is not inverted for each pixel electrode 9a, and the pixel electrode 9a is driven with the same polarity for each column.
Then, the states shown in FIGS. 16A and 16B are repeated at a cycle of one field or one frame, and the driving by the 1S inversion driving method in the present embodiment is performed. Therefore, image display with reduced crosstalk and flicker can be performed while avoiding deterioration of the liquid crystal due to the application of the DC voltage.

In the electro-optical device employing such a 1S inversion driving method, as can be seen from FIGS. 16A and 16B, the horizontal electric field generation region C2 is always in the horizontal direction (X
(Direction) is a boundary region between the pixel electrodes 9a adjacent to each other.
Therefore, in the electro-optical device employing the 1S inversion driving method, although not shown, the TFT described with reference to FIG. 2 is opposite to the electro-optical device employing the 1H inversion driving method.
On the array substrate 10, a protrusion may be formed in a region along each data line 6a. In addition, a concave portion may be formed in a region along the scanning line 3a and the capacitance line 3b to flatten this region.

In manufacturing the electro-optical device having such a structure, unevenness is formed on the lower layer side of the pixel electrode 9a. This method is described with reference to FIG. Since the process described with reference to 15 may be applied as it is, the description is omitted.

Fourth Embodiment FIGS. 17A to 17C are cross-sectional views of an electro-optical device showing another problem of the present invention, and cross-sectional views of an electro-optical device of a fourth embodiment of the present invention. And FIG. 7 is a process cross-sectional view illustrating a method for manufacturing the electro-optical device.

In the above first to third embodiments, FIG.
As shown in (a), the surface of the region where the capacitor line 3b is formed (the region where the storage capacitor 70 is formed) has a larger surface area than the surface of the region where the scanning line 3a has been formed. It is easy to get higher by the thickness.

Even in such a case, as shown in FIG. 17B, the capacitance line 3 on the surface of the TFT array substrate 10 is removed.
b is formed on the convex portion 3 on which the scanning line 3a is formed.
If the height is made one step lower than that of 01, useless irregularities can be prevented from being formed on the surface.

In forming such a concavo-convex structure, for example, as shown in FIG. 17C, an intermediate resist mask 5 is provided between the lower resist mask 501 and the upper resist mask 505 in the resist mask 508.
07 is added, and these resist masks 501 and 50 are added.
7, 505 presence / absence (difference in thickness of resist mask 508)
Accordingly, as shown in FIG. 17B, predetermined irregularities may be formed on the surface of the TFT array substrate 10. The other configuration is the same as that of the first embodiment, and the description is omitted.

[Fifth Embodiment] FIG. 18 shows a fifth embodiment of the present invention.
FIG. 2 is a cross-sectional view of the electro-optical device according to the embodiment.

As shown in FIG. 18, the area of the surface of the TFT array substrate 10 where the capacitance line 3b is formed is set to a sufficiently lower area than the projection 301 where the scanning line 3a is formed. A structure in which the capacitance line 3b is formed at a position lower than the scanning line 3a may be employed. Such a structure can also be easily formed by forming a resist mask on the surface of the TFT array substrate 10 and selectively etching the surface of the TFT array substrate 10 by utilizing the presence or absence of the resist mask or the difference in thickness. realizable. The other configuration is the same as that of the first embodiment, and the description is omitted.

[Other Embodiments] In each of the embodiments described above, the concave portion 201 and the convex portion 30 are provided below the pixel electrode.
1 are used, so that a multi-stage resist mask 508 is used. However, if only the concave portion 201 is formed, only the lower resist mask 501 is formed, and if only the convex portion 301 is formed, the upper resist mask is formed. Only 505 needs to be formed. In such an embodiment as well, if an etching gas containing oxygen is used at the time of dry etching, the side portions 202 and 302 have tapered concave portions 201 and convex portions 30.
1 can be formed.

In each of the above embodiments, the data line driving circuit 101 and the scanning line driving circuit 104 are formed on the TFT array substrate 10, but instead, for example, on a TAB (Tape Automated bonding) substrate. May be electrically and mechanically connected to the drive LSI mounted on the TFT array substrate via an anisotropic conductive film provided on the periphery of the TFT array substrate 10. On the side of the opposite substrate 20 on which the projected light is incident and on the side of the TFT array substrate 10 where the emitted light is emitted, for example, operation modes such as TN mode, VA mode, PDLC (Polymer Dispersed Liquid Crystal) mode, A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to the normally white mode / normally black mode.

Since the electro-optical device in each of the embodiments described above is applied to a projector, three electro-optical devices are used as RGB light valves, and each light valve has an RGB color separation. The light of each color decomposed via the dichroic mirror for light is incident as projection light. Therefore, in each embodiment, the opposing substrate 20 is not provided with a color filter. However, among the regions where the light-shielding film 23 is not formed, an RGB color filter may be formed on the counter substrate 20 together with the protective film in a predetermined region facing the pixel electrode 9a. In this way, the electro-optical device in each embodiment can be applied to a direct-view or reflective color electro-optical device other than the liquid crystal projector.

Further, in each of the above embodiments, the TFT
TFT 3 for pixel switching on array substrate 10
A light-shielding film made of, for example, a high-melting-point metal may also be provided at a position facing 0 (that is, below the TFT). If a light-shielding film is also provided below the TFT 30 as described above, one optical system is configured by combining the back surface reflection (return light) from the TFT array substrate 10 side and a plurality of liquid crystal devices via a prism or the like. In this case, it is possible to prevent a projection light portion or the like that penetrates through a prism or the like from another liquid crystal device from being incident on the TFT 30 of the liquid crystal device.

Further, micro lenses may be formed on the opposing substrate 20 so that one micro lens corresponds to one pixel. Alternatively, it is also possible to form a color filter layer with a color resist or the like under the pixel electrode 9a facing the RGB on the TFT array substrate 10. With this configuration, a bright electro-optical device can be realized by improving the efficiency of collecting incident light. Furthermore, a dichroic filter that produces RGB colors using light interference may be formed by depositing a number of interference layers having different refractive indexes on the counter substrate 20. According to the counter substrate with the dichroic filter, a brighter color electro-optical device can be realized.

The present invention is not limited to the above-described embodiments, but can be appropriately modified without departing from the spirit or spirit of the invention which can be read from the claims and the entire specification. Such an electro-optical device manufacturing method or electro-optical device is also included in the technical scope of the present invention.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit of various elements, wiring, and the like provided in a plurality of pixels in a matrix forming an image display area in an electro-optical device according to a first embodiment of the present invention.

FIG. 2 shows a data line,
FIG. 3 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which scanning lines, pixel electrodes, and the like are formed.

FIG. 3 is an explanatory diagram showing a region where a concave portion is formed in a base surface located below a pixel electrode in a boundary region between pixels shown in FIG.

FIG. 4 is an explanatory diagram showing, in the boundary region between pixels shown in FIG. 2, a region in which a convex portion is formed on a base surface located below a pixel electrode, with diagonally downward slanted lines;

FIG. 5 is a sectional view taken along line A-A 'of FIG.

FIG. 6 is a sectional view taken along line B-B 'of FIG.

FIG. 7 is a sectional view taken along line C-C 'of FIG.

FIGS. 8A and 8B are explanatory diagrams showing a relationship between a potential polarity in each pixel electrode and a region where a lateral electric field is generated in an electro-optical device employing a 1H inversion driving method.

FIGS. 9A to 9C are explanatory diagrams showing states of alignment of liquid crystal molecules when a TN liquid crystal is used.

FIGS. 10A to 10E are process cross-sectional views illustrating a method of manufacturing the electro-optical device according to the first embodiment.

FIGS. 11A to 11E are process cross-sectional views illustrating respective steps performed subsequent to the steps illustrated in FIGS. 10A to 10E when manufacturing the electro-optical device according to the first embodiment; It is.

FIG. 12 shows an electro-optical device according to a second embodiment of the present invention;
3 is a cross-sectional view when cut at a position corresponding to line AA ′ of FIG.

FIG. 13 shows an electro-optical device according to a second embodiment of the present invention;
FIG. 7 is a cross-sectional view when cut at a position corresponding to line BB ′ of FIG.

FIG. 14 shows an electro-optical device according to a second embodiment of the present invention;
5 is a cross-sectional view when cut at a position corresponding to line CC ′ of FIG.

FIGS. 15A to 15C are process cross-sectional views illustrating a method of manufacturing an electro-optical device according to a second embodiment of the invention.

FIGS. 16A and 16B are explanatory diagrams showing a relationship between a potential polarity in each pixel electrode and a region where a lateral electric field occurs in an electro-optical device employing a 1S inversion driving method.

FIGS. 17A to 17C are a cross-sectional view of an electro-optical device showing another problem of the present invention, a cross-sectional view of an electro-optical device according to a fourth embodiment of the present invention, and FIGS. It is a process sectional view showing a manufacturing method.

FIG. 18 is a sectional view of an electro-optical device according to a fifth embodiment of the invention.

[Explanation of symbols]

 Reference Signs List 1a Semiconductor layer 1a 'Channel region 1b Low-concentration source region 1c Low-concentration drain region 1d High-concentration source region 1e High-concentration drain region 1f First storage capacitor electrode 2 Insulating thin film 3a Scanning line 3b Capacity line 4 First interlayer insulating film 5 Contact Hole 6a Data line 7 Second interlayer insulating film 8 Contact hole 9a Pixel electrode 10 TFT array substrate 12 Base insulating film 16 Alignment film 20 Counter substrate 21 Counter electrode 22 Alignment film 23 Light shielding film 30 TFT 50 Liquid crystal layer 50a Liquid crystal molecule 70 Storage capacitance 201 concave part 202 concave part side part 301 convex part 302 convex part side part 501 lower layer side resist mask 502 lower layer side resist mask opening 505 upper layer side resist mask 506 upper layer side resist mask end 507 intermediate resist mask 508 resist mask 509 register The end of the mask

 ────────────────────────────────────────────────── ─── Continuing on the front page F term (reference) 2H090 HA04 HB04X HD02 HD03 HD14 JA03 JA05 JB02 JB04 JC03 KA05 LA01 LA04 MA02 2H092 JA25 JA46 JB05 JB23 JB24 JB32 JB33 JB56 JB58 KB22 KB25 MA18 MA20 NA04 PA4 QA07 A10 BAA CA25 EA05 GB10 5F110 AA06 AA18 AA30 BB01 DD02 DD03 DD05 DD12 DD13 DD14 EE04 EE05 EE09 EE28 EE45 FF23 GG02 GG13 GG25 GG47 HK07 HM14 HM15 NN02 NN22 NN23 NN24 QQ04 QQ05 QQ11

Claims (8)

[Claims] A first substrate and a second substrate that face each other with an electro-optical material interposed therebetween; a plurality of pixel electrodes provided on the first substrate; and a plurality of pixel electrodes that face the pixel electrodes and are disposed on the second substrate. In the method for manufacturing an electro-optical device having a counter electrode provided, by forming irregularities on a base surface located below the pixel electrode, the pixel electrode is formed in a boundary region between the pixel electrodes. The layer thickness of the electro-optical material in a pair of boundary regions opposed to each other is thinner than the layer thickness of the electro-optical material in another pair of boundary regions opposed to each other across the pixel electrode, and the unevenness is formed. In this case, after forming a mask on the surface of the base surface, etching is performed on the base surface while removing the mask by etching. 2. The pixel electrode according to claim 1, wherein the plurality of pixel electrodes are inverted at a first period and are inverted at a second period complementary to the first period. And a second pixel electrode group to be driven. In a boundary area between the pixel electrodes, a pixel electrode belonging to the first pixel electrode group and a pixel electrode belonging to the second pixel electrode group are formed. A method of manufacturing an electro-optical device, wherein a layer thickness of the electro-optical material in a boundary region is smaller than a boundary region between pixel electrodes belonging to the same pixel electrode group. 3. The method of manufacturing an electro-optical device according to claim 1, wherein a mask stacked in multiple stages is used as the mask. 4. The method according to claim 3, wherein, when forming the mask, after forming the lower layer side mask, forming the upper layer side mask on the lower layer side mask in a different pattern from the lower layer side mask. A method for manufacturing an electro-optical device. 5. The method according to claim 4, wherein one of the lower mask and the upper mask is formed of a positive photoresist, and the other resist mask is formed of a negative photoresist. Of manufacturing an electro-optical device. 6. The method according to claim 1, wherein
While forming a resist mask as the mask,
A method of manufacturing an electro-optical device, comprising: performing dry etching using an etching gas containing oxygen when etching the base surface through the mask. 7. The method according to claim 1, wherein
The method of manufacturing an electro-optical device, wherein the base surface is a surface of the first substrate. 8. The method according to claim 1, wherein
The method of manufacturing an electro-optical device according to claim 1, wherein the base surface is a surface of an insulating film formed on a front side of the first substrate.