JP2001129206A - Pachinko game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cause a pay-out control device to accurately receive, without reception errors, a prize-ball command transmitted from a main control device and use an interruption NMI terminal both for interruption by the reception of the prize-ball command and for data backup during a power outage. SOLUTION: A gate circuit 6 is provided which outputs a signal when there is either a strobe signal transmitted according to the prize-ball command or a voltage drop signal transmitted from a source voltage monitoring circuit 7 according to the drop of voltage at a power supply. The output terminal of the gate circuit 6 is connected to the NMI terminal of the pay-out control device 3 to input the strobe signal and the voltage drop signal to the respective input ports of the pay-out control device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a payout control device that receives a prize ball command transmitted from a main control device that performs overall control of a pachinko game and controls payout of a designated number of prize balls. The present invention relates to a pachinko game machine provided with a pachinko game machine.

[0002]

2. Description of the Related Art A main control device (main CPU) for performing overall control of a pachinko game, and a payout control device (sub-CPU for payout control) connected only to one-way communication from the main CPU are provided. When receiving the prize ball command (the number of prize balls to be paid out) transmitted from the main control device,
2. Description of the Related Art A pachinko gaming machine that controls the payout of a prize ball to a ball discharge device based on a prize ball command is known.

[0003] The communication of the prize ball command between the main CPU and the sub CPU is performed from the main CPU to the sub CPU by one.
This is performed by transmitting a bit control signal, that is, a strobe signal (STB signal) and a 2-byte winning command (command data) of one command. Main C
The control signal line transmitted from the PU is
It is connected to an NT (maskable interrupt) terminal. A control signal transmitted from the main CPU causes the sub CPU to
An NT interrupt is generated, and the sub CPU receives the prize ball command in the INT interrupt processing.

On the other hand, the sub CPU uses a built-in timer interrupt to control a stepping motor for paying out prize balls. As described above, when the INT interrupt and the built-in timer interrupt are used, an external input / output port (for example, Z80 PIO) for externally providing a vector address of the INT interrupt must be connected to the sub CPU. However, if the external input / output port is
When connected to the PU, the priority of the interrupt of the control signal related to the prize ball command is set lower than the interrupt for controlling the stepping motor for the prize ball payout according to the specification of the sub CPU. When a prize ball command is transmitted from the main control device during the interrupt process by the interrupt for controlling the stepping motor, the sub C
There is a problem that the PU cannot receive the prize ball command, the prize ball corresponding to the prize ball command is not paid out, and the payout cannot be performed accurately.

[0005] The above-mentioned sub CPU is provided with an NMI terminal (non-maskable interrupt terminal) in addition to the INT terminal. The NMI interrupt has a higher priority than the INT interrupt. The NMI interrupt is
It is supposed that interrupt enable / disable cannot be set on a program like a T interrupt.

On the other hand, if the operating power supply of the payout control device is cut off for some reason, data (payout) such as necessary data during payout processing of the prize ball and received and stored prize ball commands (command payout number). All data in the RAM of the control device will be lost. The present applicant has previously responded to the occurrence of the power-off state by responding to the RAM of the payout control device.
A pachinko gaming machine that backs up data by writing all the data stored in a ROM to a writable ROM has been proposed as Japanese Patent Application No. 11-197091.

[0007] The pachinko gaming machine disclosed in Japanese Patent Application No. Hei 11-197091 monitors an operating voltage by a voltage monitoring IC. When the operating voltage drops due to, for example, a power cut, the voltage monitoring IC issues a voltage drop signal. The data is input to the device, and the payout control device backs up the data accordingly. Note that the voltage drop signal output from the voltage monitoring IC is input to the INT terminal of the payout control device, and the payout control device backs up data by INT interrupt processing.

[0008]

SUMMARY OF THE INVENTION It is an object of the present invention to enable a payout control device to accurately receive a prize ball command transmitted from a main control device without receiving a mistake, and to provide an NMI terminal for interruption. The present invention is to provide a pachinko gaming machine capable of sharing a prize ball command reception interrupt and an interrupt for backing up data when power is turned off.

[0009]

According to the present invention, there is provided a pachinko gaming machine comprising: a prize ball command transmitted from a main control device for performing overall control of a pachinko game; and a strobe signal transmitted in accordance with the prize ball command. In a pachinko game machine equipped with a payout control device for receiving a designated number of payouts and controlling payout of a prize ball, a power supply voltage monitoring circuit for outputting a voltage drop signal in accordance with a voltage drop of a power supply, and the strobe signal And a gate circuit that outputs a signal when there is one of the voltage drop signal and an output terminal of the gate circuit is connected to an NMI terminal of the payout control device, and the strobe signal and the voltage drop signal are provided. Are respectively input to the input ports of the payout control device.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a main part of a control system of an embodiment related to transmission and reception of a prize ball command between a main control device 1 and a payout control device 3 provided in a pachinko gaming machine of the present embodiment.

A main control device 1 for performing overall control of a pachinko game is mounted on a main control board 2. The payout control device 3 for controlling the payout of the prize ball includes a prize ball control board 4.
It is installed in. Main controller 1 and payout controller 3
Is connected so that only one-way communication from the main control device 1 to the payout control device 3 is possible. A winning detection signal from various winning detecting means (not shown) is input to the main control device 1. The main control device 1 outputs a prize ball command corresponding to the number of payouts determined in advance according to the type of the prize detection signal (for example, a prize detection signal of a prize detection switch for detecting a prize to a prize port set to five payout ports) A prize ball command instructing to dispense five prize balls in response to the dispense control device 3
Send to

The payout control device 3 includes a sub-CPU for controlling the payout of a prize ball, a ROM storing each control program executed by the sub-CPU, a RAM capable of reading and writing data as needed, and a main control device 1. And a microcontroller in which a built-in I / O port 5 for receiving the award ball command transmitted from the PC and an internal bus (including a data bus) are provided in one chip. The illustration of a specific internal configuration of the payout control device 3 is omitted.

The control command transmitted from the main control device 1 to the payout control device 3 is composed of a 1-bit STB signal (strobe signal) and a 1-command 2-byte prize ball command (data for instructing the number of payouts). ing. The prize ball command is issued by the main controller 1 as the command payout number 1
The command payout number is set in units of one within a range of 15 to the command payout number. Therefore, the content of the prize ball command is any one of the command payout numbers in the range of 1 to 15. The prize ball command transmitted from the main control device 1 is connected to the built-in I / O port 5 of the payout control device 3.

Although not shown in FIG. 1, a ball discharge device for paying out prize balls is connected to the payout control device 3 via a driver. An operation control for dispensing is performed. A discharge ball sensor for detecting a prize ball paid out from the ball discharge device is connected through an input port.

FIG. 2 is a block diagram showing a circuit configuration relating to reception of a prize ball command and backup of data mounted on the prize ball control board 4. As shown in FIG. 2, the STB signal transmitted from the main control device 1 is a signal line L
1 through D1 of the built-in I / O port 5 of the payout control device 3
Input to the terminal. The STB signal is also input to a 1B terminal (input terminal) of an AND gate 6 (an AND gate is one mode of a gate circuit) through a signal line L2.

The power supply voltage monitoring IC 7 outputs a voltage reduction signal (reset signal) from its RST terminal when the operating voltage is reduced due to, for example, a power failure. The voltage drop signal output from the power supply voltage monitoring IC 7 is input to the D0 terminal of the built-in I / O port 5 of the payout control device 3 through the signal line L3. The voltage drop signal is also input to the 1A terminal (input terminal) of the AND gate 6 through the signal line L4.

The 1Y terminal (output terminal) of the AND gate 6 is connected to the XN of the payout control device 3 through a signal line L5.
It is connected to the MI terminal (non-maskable interrupt terminal), and is configured so that the output signal of the AND gate 6 is input to the XNMI terminal of the payout control device 3.

Further, a voltage drop signal output from the power supply voltage monitoring IC 7 is supplied to a delay circuit 8 through a signal line L6.
And the output signal of the delay circuit 8 is a signal line L7
Is input to the XSRST terminal (system reset terminal) of the payout control device 3 through the control unit.

The payout control device 3 is connected to a ROM 9 to which data can be written. The writable ROM 9 is constituted by, for example, an EEPROM. All the data stored in the RAM (not shown) of the payout control device 3 are written and stored in the ROM 9 in response to the occurrence of power interruption, and a flag indicating that the data has been backed up is written. .

In FIG. 2, the STB signal is active at a low level. The voltage drop signal is active at a low level. XNMI terminal and XSR
The first character "X" at the ST terminal indicates that the signal is negative logic.

The payout control device 3, AND gate 6, pressure monitoring IC 7 with power supply, delay circuit 8, and writable ROM 9 are mounted on the prize ball control board 4.

FIG. 3 is a time chart showing a transmission timing of a control command related to the payout of the prize ball transmitted from the main control device 1 to the payout control device 3. The control command is composed of one command and two bytes.
Each byte is transmitted twice. The command payout number (any one of 1 to 15) is determined by the command data 1 and the command data 2 shown in FIG.

The receiving operation of the prize ball command in the payout control device 3 of the embodiment configured as described above and the backup of the data when the power is cut off will be described. In FIG. 2, when the input of the XNMI terminal goes low, the payout control device 3 generates an NMI interrupt (non-maskable interrupt), and in the NMI interrupt processing, receives the prize ball command and backs up data in the event of a power failure. Is performed. In addition, the payout control device 3 determines whether the interruption is related to the reception of the prize ball command or the interruption related to the power cutoff by D0.
The determination is made based on the input of the terminal D1.

FIG. 4 is a table showing the relationship between the levels of the terminals of the AND gate 6, the D1, D0 and XNMI terminals of the payout controller 3 and the states of the prize ball command and the occurrence of power interruption. FIG. FIG. 5 is a flowchart of the NMI interruption process performed by the payout control device 3.

First, the reception of the award ball command will be described. Since the STB signal is active at a low level and the voltage drop signal is active at a low level, the output of the AND gate 6 is at a high level.

A prize ball command (FIG. 3)
When the command data 1) is transmitted, the STB signal changes from high level to low level, and 1B of the AND gate 6
It is input to the terminal and the D1 terminal of the payout control device 3, respectively. When the input of the 1B terminal goes low, the AND gate 6 outputs a low level to the 1Y terminal. As a result, the low level is input to the XNMI terminal of the payout control device 3. In the payout control device 3, when a low level is input to the XNMI terminal, an NMI interrupt occurs, and the NMI interrupt process is started. In addition, the STB signal is transmitted to D1 of the payout control device 3.
By being input to the terminal, a low level is input to the D1 terminal of the payout control device 3.

In the NMI interrupt process, the payout control device 3 sequentially determines whether or not the input of the D0 terminal is at a low level and whether or not the input of the D1 terminal is at a low level (steps S01 to S02). When the input of the D0 terminal is at a high level and the input of the D1 terminal is at a low level,
The payout control device 3 determines that the step S01 is false and determines that the step S02 is true, that is, determines that the interruption is due to the winning ball command, and performs the receiving process of the winning ball command (step S03). In addition, as shown in FIG.
Since the command data 1 is transmitted separately, the command data 1 transmitted for the first time shown in FIG. 3 is received.

As shown in FIG. 3, when the STB signal switches from the low level to the high level, the transmission of the command data 1 ends. The payout control device 3 once ends the NMI interrupt processing. Next, when the command data 2 is transmitted from the main control device 1, the STB signal changes from the high level to the low level again, and the payout control device 3 executes the XNM.
When a low level is input to the I terminal, an NMI interrupt occurs, and the NMI interrupt process is started.

When the input of the D0 terminal is at the high level and the input of the D1 terminal is at the low level in the NMI interrupt processing, the payout control device 3 determines that the interrupt is due to the prize ball command, and in step S03, the payout command is output. The reception processing is performed, and the command data 2 transmitted for the second time shown in FIG. 3 is received. When the STB signal switches from the low level to the high level, transmission of the command data 2 ends. When the payout control device 3 finishes receiving the command data 1 and the command data 2 in the prize ball command receiving process,
The command payout number determined by the contents of the command data 1 and the command data 2 is stored in a predetermined area of the RAM.

Next, the backup of all data in the RAM when a power failure occurs will be described. When the power supply is cut off (when the power supply voltage drops), the output of the RST terminal of the power supply voltage monitoring IC goes low. That is,
The power supply voltage monitoring IC 7 outputs a voltage drop signal.

The voltage drop signal is supplied to the 1A of the AND gate 6.
The terminal, the D0 terminal of the payout control device 3 and the delay circuit 8 are input to the terminal. When the input of the 1A terminal becomes low level, the AND gate 6 outputs a low level to the 1Y terminal,
As a result, a low level is input to the XNMI terminal of the payout control device 3. In the payout control device 3, when a low level is input to the XNMI terminal, an NMI interrupt occurs, and the NMI
Interrupt processing starts. When the voltage drop signal is input to the D0 terminal of the payout control device 3, a low level is input to the D0 terminal of the payout control device 3.

The payout control device 3 determines whether or not the input to the D0 terminal is at a low level in the NMI interrupt processing (step S01). If the input to the D0 terminal is at a low level, the payout control device 3 determines that step S01 is true. That is, it is determined that the power is turned off, and a backup process is performed (step S0).
4). The payout control device 3 uses the RAM in the backup process.
Is written and stored in the writable ROM 9, and a flag indicating that the data has been backed up is written. After the completion of the backup process, the payout control device 3 is in a standby state until the system is reset.

On the other hand, when the power supply voltage signal (low level) is input to the delay circuit 8, it is output from the delay circuit 8 after the elapse of the delay time set by the circuit, and the XS
Input to the RST terminal. XSRS in the payout control device 3
When the input of the T terminal becomes low level, a system reset is performed. After the power is restored, the payout control device 3
If a flag indicating that the data has been backed up is written in the writable ROM 9, all data stored in the writable ROM 9 is transferred to the RAM, and the system is restored to the system state at the time of power failure. .

In the embodiment, when an interrupt due to a prize ball command input to the XNMI terminal and an interrupt due to the occurrence of power interruption (two interrupts) occur at the same time, an interrupt due to the prize ball command is generated, and the prize ball command is generated. If an NMI interrupt occurs due to a power supply interruption during the reception processing, the backup processing due to the power supply interruption has priority in the NMI interrupt processing. That is, as shown in the flowchart of FIG. 5, it is determined whether or not the input of the D0 terminal is at a low level in the NMI interrupt processing (see step S01).
(See step S02), so that the backup process due to the occurrence of an interrupt due to the occurrence of power interruption due to the input of a power-down signal has priority. Will be

When an NMI interrupt occurs,
It is unlikely that both the D0 terminal and the D1 terminal become high level. Therefore, in the flowchart of FIG. 5, the process returns without performing any processing.

As described above, in the present embodiment, the payout control device 3 generates an NMI interrupt by the STB signal transmitted from the main control device 1 and receives the prize ball command during the NMI interrupt process. Since the payout control device 3 interrupts the process and receives the prize ball command with the highest priority even while the payout control device 3 is performing other processes, the reception error occurs as compared with the case where the prize ball command is received in the INT interrupt process. The prize ball command can be received accurately without any change.

When a power failure occurs, a power supply voltage monitoring IC
Since the payout control device 3 generates an NMI interrupt by the voltage drop signal transmitted from the CPU 7 and performs the data backup of the RAM during the NMI interrupt process, the data in the RAM can be reliably backed up when the power supply is cut off.

A gate circuit (AND gate 6) for outputting a signal when either the STB signal of the award ball command or the voltage drop signal is present is provided, and the output terminal of the gate circuit is connected to the NMI terminal of the payout control device 3. Connected, the STB signal and the voltage drop signal are respectively connected to the input ports of the payout control device 3, and the payout control device 3 determines whether or not the voltage drop signal is input during the NMI interrupt processing, and When there is an input, the data of the RAM is backed up. On the other hand, when there is no input of the voltage drop signal, the presence or absence of the input of the STB signal is determined.
Since the prize ball command is received, a backup processing means for determining whether or not a voltage drop signal is input during the NMI interrupt processing and backing up data in the RAM when the voltage drop signal is input, and an NMI interrupt Since it is configured to include a prize ball command reception processing means for determining whether or not the STB signal of the prize ball command is input during the processing and receiving the prize ball command when the STB signal is present), N
The MI terminal can be shared by an interrupt for receiving a prize ball command and an interrupt for backing up data when the power is turned off.

Since the backup processing means is activated prior to the activation of the prize ball command reception processing means, even when the prize ball command reception processing is in progress, the interruption due to the occurrence of power interruption occurs even during the prize ball command reception processing. The backup process of the data in the RAM can be reliably performed.

In the embodiment, the AND gate 6 is shown as one mode of the gate circuit. However, the gate circuit is not limited to the AND gate, and the signal is output when either the strobe signal or the voltage drop signal is present. And outputs the signal to the NMI terminal of the payout control device 3.

In the above-described embodiment, a description will be given assuming that the main control device and the payout control device provided in the pachinko game machine are configured to receive an accurate payout signal (prize ball command). But
The external control device enables the external control device to accurately receive an external device control command for the external control device between the main control device and the external control device (for example, a display control device or a voice control device) without receiving a mistake. In order to be able to share the terminal between the external device control command reception interrupt and the data backup interrupt when the power is turned off,
An external control that receives an external device control command transmitted from a main control device that performs overall control of a pachinko game and a strobe signal that is transmitted in accordance with the external device control command and performs a specified external device control In a pachinko game machine, a power supply voltage monitoring circuit that outputs a voltage drop signal in response to a voltage drop of a power supply, and a gate circuit that outputs a signal when there is one of the strobe signal and the voltage drop signal Wherein an output terminal of the gate circuit is connected to an NMI terminal of the external control device, and the strobe signal and the voltage drop signal are input to input ports of the external control device, respectively. And a sub-controller that receives an external device control command from a main CPU of a main control device provided in the pachinko gaming machine. The NMI pin PU may be configured to be shared by the reception interrupt and the interrupt for data backup during power failure of the external device control commands.

[0042]

According to the pachinko gaming machine of the present invention, when there is one of the strobe signal relating to the prize ball command transmitted from the main control device and the voltage drop signal transmitted from the power supply voltage monitoring circuit. , The gate circuit outputs a signal and supplies the signal to the NMI terminal of the payout control device, the payout control device generates an NMI interrupt, and the payout control device
In the interrupt processing, either the reception of the prize ball command or the backup of data at the time of power failure occurs, depending on whether a strobe signal and a voltage drop signal are input to the input ports, respectively. The payout control device can accurately receive the transmitted prize ball command without receiving errors, and furthermore, the NMI terminal for the interrupt can be used as a prize ball command reception interrupt and a data backup interrupt when the power is turned off. Can be shared.

[Brief description of the drawings]

FIG. 1 is a block diagram of a main part of a control system of an embodiment related to transmission and reception of a prize ball command between a main control device and a payout control device provided in a pachinko gaming machine of the present embodiment.

FIG. 2 is a block diagram showing a circuit configuration related to receiving a prize ball command and backing up data mounted on a prize ball control board.

FIG. 3 is a time chart showing a transmission timing of a control command related to payout of a prize ball transmitted from the main control device to the payout control device.

FIG. 4 is a diagram showing, in a tabular form, a relationship between level states of an AND gate terminal, a D1 terminal, a D0 terminal, and an XNMI terminal of the payout control device, and a prize ball command and a power-off occurrence state in the embodiment.

FIG. 5 is a flowchart of an NMI interrupt process performed by the payout control device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 main control device 2 main control board 3 payout control device 4 winning ball control board 5 I / O port 6 AND gate (gate circuit) 7 power supply voltage monitoring IC (power supply voltage monitoring circuit) 8 delay circuit 9 writable ROM L1 signal Line L2 Signal line L3 Signal line L4 Signal line L5 Signal line L6 Signal line

Claims (1)

[Claims] 1. A prize ball having a designated payout number by receiving a prize ball command transmitted from a main control device for performing overall control of a pachinko game and a strobe signal transmitted in accordance with the prize ball command. In a pachinko game machine equipped with a payout control device that performs payout control, there is a power supply voltage monitoring circuit that outputs a voltage drop signal in accordance with a voltage drop of a power supply, and one of the strobe signal and the voltage drop signal. A gate circuit for outputting a signal in the case, an output terminal of the gate circuit is connected to an NMI terminal of the payout control device, and the strobe signal and the voltage drop signal are respectively input to input ports of the payout control device. A pachinko game machine characterized by the following.