JP2023094037A - game machine - Google Patents

Abstract

To prevent malfunction of a CPU before shifting to a user mode.SOLUTION: A buffer IC is provided in front of an RX0 terminal of a CPU, and an input signal from the outside is inputted to the RX0 terminal via the buffer IC. An inverter is provided between an XRSTO terminal of a CPU and a G terminal of the buffer IC. Since a low-level signal is outputted from the XRSTO terminal and is inverted by the inverter, and a high-level signal is inputted to the G terminal and an output terminal of the buffer IC becomes a high impedance during a security mode, a high-level signal is inputted from VCC to the RX0 terminal via a pull-up resistor. Since a fixed (high-level) signal is always inputted to the RX0 terminal regardless of presence of absence of an input signal from the outside during input of a high-level signal to the G terminal of the buffer IC in this manner, a state in which an input signal level does not change can be maintained, thus preventing malfunction of the CPU in advance.SELECTED DRAWING: Figure 3

Description

The present invention relates to a gaming machine that executes games.

Conventionally, a game control microcomputer (hereinafter referred to as a "chip") enters a security mode when the power is turned on, executes a security check, and when it is determined that there is no problem, shifts to a user mode and executes a game. is known (see Patent Document 1, for example).

JP 2009-89966 A

By the way, depending on the model number of the chip, if an unintended signal is input from the outside while the security check is being executed, the CPU may freeze or otherwise malfunction, or the CPU may stop operating. Therefore, in order to stably execute a game in a gaming machine employing such a chip, measures are required to prevent malfunction of the CPU before shifting to the user mode.

Accordingly, an object of the present invention is to provide a technique for preventing malfunction of the CPU before shifting to the user mode.

The present invention employs the following solutions to solve the above problems. It should be noted that the following solutions and words in parentheses are merely examples, and the present invention is not limited to these. Further, the present invention can be an invention that includes at least one of the invention-specifying matters shown in the following means for solving the problem. Furthermore, each of the matters specifying the invention shown in the following solutions can be converted into a higher-level concept by adding elements that limit the matters specifying the invention, or by deleting elements that limit the matters specifying the invention. .

[First technical feature: hardware measures]
Solution A1: The game machine of this solution means has a CPU and storage means, and when a system reset occurs, the CPU performs a security check before executing the user program stored in the storage means. A gaming machine comprising control means for executing the security check, wherein the control means masks an input signal from the outside of the control means and outputs the signal to the CPU during execution of the security check.

The gaming machine of this solving means has the following configuration.
(1) A control means (a main control board or a frame control board, a control board in which the problematic chip is adopted. For example, a main control board) is provided. The control means has a CPU (main control CPU) and storage means (built-in ROM). before transition) to perform security checks (to transition to security mode).

(2) The control means of (1) above masks an input signal from the outside of the control means (for example, the frame control board) and outputs it to the CPU while the security check is being executed (during the security mode).

According to this solution, even if a signal is input from the outside of the control means during execution of the security check, the input signal is masked before being input to the input signal receiving terminal of the CPU. can be prevented from being input to the CPU as it is, and the level of the input signal to the input signal receiving terminal can be maintained constant (unchanged state). It is possible to prevent malfunction of the CPU.

Solution A2: In the game machine of the present solution means, in the above-described solution means, the control means further includes a control circuit to which the input signal from the outside is input, and the control circuit is during execution of the security check. A signal of a predetermined level is input to a predetermined terminal, and while the signal of the predetermined level is input to the predetermined terminal, no signal is output to the CPU regardless of the level of the input signal from the outside. It is a game machine that

In this solution, the following features are added.
(3) The control means of (2) further has a control circuit (buffer IC) to which an input signal from the outside is input.
(4) In the control circuit of (3) above, a signal of a predetermined level (for example, high level) is input to a predetermined terminal (enable terminal, G terminal) during execution of the security check. While a signal of a predetermined level is input to a predetermined terminal, the output terminal of the control circuit becomes high impedance. Therefore, during execution of the security check, the control circuit sends a signal to the CPU regardless of the level of the input signal from the outside. does not output

According to this solution, an input signal from the outside is input to the CPU through the control circuit, but the control circuit does not output a signal to the CPU during the security check regardless of the level of the input signal from the outside. Since a signal of a constant level is always input to the input signal receiving terminal of the CPU from the positive power supply (VCC) via the up resistor, the level of the input signal to the input signal receiving terminal can be kept unchanged. It is possible to prevent the CPU from malfunctioning during execution of the security check.

[Second technical feature: Countermeasures from the aspect of software]
Solution Means B1: The gaming machine of this solution means executes a security check when a system reset occurs, executes a user program after the security check is completed, prepares the initial state, and then outputs the first information. Two-way communication between first control means for turning on a first signal indicating that transmission is permitted and turning off said first signal when occurrence of a reset factor is detected, and said first control means is possible, a security check is executed when a system reset occurs, a user program is executed after the security check is completed, and transmission of the second information is permitted after preparing the initial state. and second control means for turning on a second signal and turning off said second signal upon detection of occurrence of a reset factor, wherein said first control means controls said second signal while said second signal is off. 2. A game characterized in that the second information is not transmitted to the control means, and the second control means does not transmit the first information to the first control means while the first signal is off. machine.

The gaming machine of this solving means has the following configuration.
(1) A first control means (main control board) is provided. The first control means executes a security check (shifts to a security mode) when a system reset occurs, executes a user program (shifts to a user mode) after the security check is completed, and restores an initial state. , and turns on the first signal (main command permission signal) that indicates permission to transmit the first information (main command), while detecting the occurrence of a reset factor (for example, power failure, WDT timeout, etc.) Then the first signal is turned off.

(2) A second control means (frame control board) is provided. The second control means is capable of two-way communication with the first control means of (1) above, and executes a security check (shifts to security mode) when a system reset occurs, A second signal (frame command permission signal) indicating permission to transmit the second information (frame command) after the user program is executed (shifted to user mode) after the security check is completed and the initial state is prepared. is turned on, and the second signal is turned off when the occurrence of a reset factor (for example, power failure, WDT timeout, etc.) is detected.

According to this solution means, the second control means does not transmit the first information to the first control means until the first signal is turned on after the security check is completed in the first control means. Since the first control means does not transmit the second information to the second control means until the second signal is turned on after the security check is completed in the means, the first control means receives the first information before shifting to the user mode. Since the second control means does not receive the second information, it is possible to prevent the CPUs of the first control means and the second control means from malfunctioning during execution of the security check.

[Third technical feature: Countermeasures in terms of types of resets]
Solution C1: The game machine of this solution has a CPU and storage means, and when a system reset occurs, the CPU shifts to a user mode in which the user program stored in the storage means is executed. a control means for shifting to a security mode in which a security check is performed before a user reset occurs, and shifting to the user mode without shifting to the security mode when a user reset occurs; This gaming machine is characterized in that, when an internal reset factor occurs, a user reset is generated based on a value set in a predetermined area of the storage means, and the game machine shifts to a user mode.

The gaming machine of this solving means has the following configuration.
(1) A control means (a main control board or a frame control board, a control board in which the problematic chip is adopted. For example, a main control board) is provided. The control means has a CPU (main control CPU) and storage means (built-in ROM). When a system reset occurs, the CPU shifts to a user mode in which the user program stored in the storage means is executed. In contrast to the security mode in which the security check is performed before the user reset occurs, the user mode is entered without entering the security mode.

(2) When an internal reset factor including timeout of the watchdog timer occurs during the user mode, the control means of (1) above sets a value set in a predetermined area (reset setting area of the program management area) of the storage means. A user reset is generated to shift to the user mode.

According to this solution, if an internal reset factor occurs during the user mode, the system directly shifts to the user mode without going through the security mode, so the security check is not executed. Since no signal is input from the outside, it is possible to prevent the CPU from malfunctioning during execution of the security check.

According to the present invention, it is possible to prevent malfunction of the CPU before shifting to the user mode.

It is a block diagram of a management game machine. It is a circuit diagram showing a simplified circuit mounted on a main control board. FIG. 4 is a diagram for explaining the flow of signals during security mode; FIG. 4 is a diagram for explaining the flow of signals during user mode; 4 is a timing chart showing the flow of processing executed by the main control CPU and the frame control CPU after power-on and the timing thereof; It is a figure explaining a user reset. It is a block diagram of a normal gaming machine that is not a managed gaming machine.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram of a managed game machine.
The management game machine 100 includes a management game machine game board 10 and a management game machine frame 20, circulates a certain number of game balls within the single machine, and supplies game balls to be used in games and to players. This is an enclosed game machine that does not require direct payout. The managed gaming machine 100 can be played by connecting to a dedicated unit (IC card unit) dedicated to the managed gaming machine.

The management game machine game board 10 includes a game board (acrylic board), a pattern display device (special pattern display device, normal pattern display device), a winning/ball passage detection mechanism (various switches), a windmill, a game nail, and other effects. Equipment (movable body for presentation, liquid crystal display, information display device, speaker, lamp), award display device, device for changing the falling direction (movable member, lid member), etc. are provided.

The management game machine frame 20 includes a game ball, a launching device, a power supply device, a ball polishing device, a game ball circulation device, a display device for the number of game balls, a glass plate, a night monitoring device, other production devices, an iron ball detection device, a front Equipped with decorations, counting switches, etc.

In the management game machine 100, the front decoration of the management game machine frame 20 can be opened. When the front decoration is opened, the front decoration and the glass plate are opened, and the management game machine game board 10 arranged behind the glass plate is exposed.

[Overview of management machines]
The outline of the managed gaming machine is as follows.
(1) The management gaming machine 100 belongs to the same category as the pachinko machine, and the player plays a game by hitting a game ball onto the board surface of the management gaming machine game board 10 .
(2) The managed gaming machine 100 has no upper and lower trays, and the player cannot directly touch the game balls.
(3) The management gaming machine 100 circulates the minimum number of game balls required for shooting within the management gaming machine 100, and a shooting device, a ball polishing device, and a game ball circulation device are provided during the circulation. there is
(4) The shooting device has the shooting performance of current gaming machines, and may be bottom firing or top firing.
(5) In the ball polishing device, a polishing cloth for removing dirt from game balls is stored in a cassette, and is replaced at regular intervals.
(6) The number of game balls and the number of acquired game balls are managed and displayed as numerical data by the management game machine 100 (frame control board 70).
(7) At the end of the game, by pressing the counting switch 83 (counting button), the number of game balls managed by the management gaming machine 100 (frame control board 70) can be transferred to a dedicated unit for management. .

The management game machine game board 10 includes a main control board 30 (first control means) and an effect control board 50 . The main control board 30 has a main control CPU 31 and controls the contents of the progress of the game. The performance control board 50 has a performance control CPU 51, and controls the contents of game performance. The main control board 30 can communicate with the effect control board 50 and the frame control board 70 . Although the effect control board 50 can communicate with the main control board 30, this communication is performed only in one direction from the main control board 30 to the effect control board 50, and two-way communication is not performed.

The main control board 30 is connected with a prize winning port switch 41, an out switch 42, and the like. The winning opening switch 41 includes each switch such as a winning opening corresponding to a normal symbol or a special symbol, a large winning opening, a normal winning opening (general winning opening), and the like. The out switch 42 is arranged in the out passage. A game ball launched into the game area (board surface) flows down the game area and enters the winning opening or the out opening. be.

A liquid crystal display 61, a speaker 62, a lamp 63, and the like are connected to the performance control board 50. FIG. The effect control board 50 receives a command transmitted from the main control board 30, determines the content of the effect based on the received command, and executes the effect using a liquid crystal display 61, a speaker 62, a lamp 63, and the like. .

The management game machine frame 20 has a frame control board 70 (second control means). The frame control board 70 has a frame control CPU 71 and controls the contents regarding the number of game balls. The frame control board 70 can communicate bi-directionally with the main control board 30 . The frame control board 70 is connected with a subtraction sensor 81, a foul ball sensor 82, a counting switch 83, a game ball count display device 84, and the like.

When the frame control board 70 receives a winning ball number command (a request for the number of winning game balls) from the main control board 30, the number of winning balls included in the winning ball number command is added to the number of game balls, and the number of game balls, etc. It is displayed on the display device 84 . When the subtraction sensor 81 detects the shooting of game balls, the frame control board 70 subtracts 1 from the number of game balls and displays it on the display device 84 such as the number of game balls. When the foul ball sensor 82 detects the passage of a game ball, the frame control board 70 adds 1 to the number of game balls and displays it on the display device 84 such as the number of game balls. When the count switch 83 is pressed, the frame control board 70 transmits the number of counted balls to the dedicated unit, subtracts the number of counted balls from the number of game balls, and displays the number of game balls after the subtraction on the display device 84 for the number of game balls, etc. to display. When the frame control board 70 receives the number information of the number of rental balls from the exclusive unit, the number information and the number of the game balls are added to display the number of the game balls on the display device 84 for the number of the game balls. A foul ball (return ball) is a game ball that has been shot by a shooting device but returned without reaching the game area.

By the way, depending on the model number of the chip mounted on the main control board 30 or the frame control board 70, as described above, if an unintended signal is input from the outside during execution of the security check (input signal level (Low, If there is a change in High), the CPU may malfunction such as freezing, or may stop operating due to this, and as a result, the game may not be executed normally.

Therefore, in the managed gaming machine 100, a plurality of measures are taken to avoid signal input from the outside before shifting to the user mode. Three embodiments will be described in order below. For convenience of explanation, in the following explanation, an example in which a chip having the above-described problems is employed in the main control board 30 will be explained.

[First embodiment]
First, the configuration of the management gaming machine 100 of the first embodiment, which takes hardware countermeasures against the chip problem described above, will be described.

FIG. 2 is a circuit diagram showing a simplified circuit mounted on the main control board 30 of the management game machine 100 of the first embodiment.

In the main control board 30 of the first embodiment, a buffer IC 34 (control circuit, buffer circuit) is provided in front of the RX0 terminal of the main control CPU 31, and external to the main control board 30 (for example, the frame control board 70). An input signal from is input to the main control CPU 31 via the buffer IC 34 . Specifically, the input signal from the outside is input to the 2 pin of the buffer IC 34, is logically operated within the buffer IC 34, is output from the 18 pin of the buffer IC 34, and is input to the RX0 terminal of the main control CPU 31. . The RX0 terminal is an input signal receiving terminal, and corresponds to, for example, a receiving terminal of an asynchronous serial communication circuit.

In addition, the XSRST terminal (system reset input terminal) of the main control CPU 31 is connected to the terminal of the reset circuit 32 by a signal line, and the XRSTO terminal (reset output terminal) of the main control CPU 31 is connected to the 1 pin of the inverter 33 by a signal line. 2 pins of the inverter 33 are connected to the enable terminal (hereinafter referred to as "G terminal") of the buffer IC 34 by a signal line.

In the management gaming machine 100, system reset factors (for example, power-on, momentary power failure, etc., timeout of watch dog timer (hereinafter referred to as "WDT"), or function of prohibiting travel outside the designated area (hereinafter referred to as "IAT") When an internal reset factor such as the detection of ) occurs, a system reset occurs, and when the system reset is released, the security mode is always entered and a security check is performed. In the first embodiment, the input signal is masked using the circuits arranged as shown in FIG. conduct.

FIG. 3 is a diagram for explaining the signal flow after transition to the security mode, that is, during the security mode (during execution of the security check). In FIG. 3, thin line arrows indicate the flow of Low level signals, and thick line arrows indicate the flow of High level signals. As for the buffer IC 34, the pins (3-9, 11-17 pins) not involved in the signal masking process are omitted from the drawing (the same applies to FIG. 4).

(A) in FIG. 3 shows the signal flow during the security mode. During resetting, a reset signal (low level) is output from the terminal of the reset circuit 32 and input to the XSRST terminal of the main control CPU 31 ((1) in the figure). In response to this, the main control CPU 31 outputs a Low level signal from the XRSTO terminal ((2) in the figure). When a low level signal is input to pin 1 of inverter 33 ((3) in the figure), inverter 33 inverts the signal and outputs a high level signal from pin 2 ((4) in the figure). The output High level signal is input to the G terminal of the buffer IC 34 ((5) in the figure). At this time, the input signal from the outside of the main control board 30 is at the Low level ((6) in the figure), and no signal is input from the outside. When a high level signal is input to the G terminal, the output terminal of the buffer IC 34 becomes high impedance. A level signal is input ((7) in the figure).

(B) in FIG. 3 shows the signal flow when a signal is input from the outside of the main control board 30 during the security mode. The signal flow from the XRSTO terminal of the main control CPU 31 to the G terminal of the buffer IC 34 via the inverter 33 is the same as that shown in FIG. At this time, an external input signal (high level) is input to pin 2 of the buffer IC 34 ((6) in the figure), but since the output terminal of the buffer IC 34 is still at high impedance, even in such a situation, A high level signal is input from the positive power supply (VCC) to the RX0 terminal of the main control CPU 31 via a pull-up resistor ((7) in the figure).

In this way, the output terminal of the buffer IC 34 has a high impedance while a high level signal is being input to the G terminal. There is no output to the RX0 terminal of the main control CPU31, and a High level signal is input to the RX0 terminal of the main control CPU31 from the positive power supply (VCC) via a pull-up resistor. As a result, a signal of a constant level (high level) is always input to the RX0 terminal during resetting and security mode, so that the level of the input signal to the RX0 terminal remains unchanged. It is possible to prevent malfunction of the main control CPU 31 and the like.

FIG. 4 is a diagram for explaining the signal flow after transition to the user mode, that is, during the user mode (after the security check is completed).

(A) in FIG. 4 shows the flow of signals during the user mode. The reset circuit 32 outputs a high-level signal ((1) in the drawing) when the reset is released. Further, when the security check is completed, the main control CPU 31 outputs a High level signal from the XRSTO terminal ((2) in the figure). When a high level signal is input to pin 1 of inverter 33 ((3) in the figure), inverter 33 inverts the signal and outputs a low level signal from pin 2 ((4) in the figure). The output Low level signal is input to the G terminal of the buffer IC 34 ((5) in the figure). At this time, the input signal from the outside of the main control board 30 is at the Low level ((6) in the figure), and no signal is input from the outside. Under such circumstances, the buffer IC 34 outputs a Low level signal from pin 18 to the RX0 terminal of the main control CPU 31 ((7) in the figure).

(B) in FIG. 4 shows the flow of signals when signals are input from the outside of the main control board 30 during the user mode. The signal flow from the XRSTO terminal of the main control CPU 31 to the G terminal of the buffer IC 34 via the inverter 33 is the same as that shown in FIG. At this time, when an external input signal (high level) is input to the 2 pin of the buffer IC 34 ((6) in the figure), the buffer IC 34 directs the high level signal from the 18 pin to the RX0 terminal of the main control CPU 31. Output ((7) in the figure).

Thus, the buffer IC 34 outputs the signal input from the outside of the main control board 30 to the RX0 terminal of the main control CPU 31 as it is while the signal of Low level is input to the G terminal. As a result, during the user mode, the input signal from the outside can be transferred to the RX0 terminal as it is, so that the main control CPU 31 can appropriately execute the game process according to the input signal from the outside. .

2-4, only one input signal receiving terminal (RX0) of the main control CPU 31 is shown for easy understanding of the invention, but in reality there are two input signal receiving terminals. (RX0, RX1). The RX1 terminal (not shown) is connected to a different pin of the buffer IC 34 through a connection line different from that of the RX0 terminal, and an external input signal is input to the RX1 terminal via this pin. The structure for processing the input signal through the buffer IC 34 for the RX1 terminal is the same as for the RX0 terminal described above.

Also, in FIGS. 2-4, for convenience of explanation, an example in which the above-described problematic chip is adopted in the main control board 30 has been explained, but the main control board 30 does not have the problem. If a chip with a problem is used and the frame control board 70 uses a chip with a problem, the circuit configuration described above may be mounted on the frame control board 70 . If both the main control board 30 and the frame control board 70 employ problematic chips, the circuit configuration described above may be mounted on both the main control board 30 and the frame control board 70 . It should be noted that it is also possible to apply the circuit configuration described above to a substrate on which chips having no problem are adopted.

[Second embodiment]
Next, the configuration of the management gaming machine 100 of the second embodiment, in which measures are taken from the aspect of software to deal with the chip problem described above, will be described.

FIG. 5 is a timing chart showing the flow and timing of processing executed by the main control CPU 31 and the frame control CPU 71 after the power is turned on in the managed gaming machine 100 of the second embodiment. In FIG. 5, for convenience of explanation, the timings at which each event occurs are shown as times t1 to t6. The occurrence timing of each event may actually have some time difference. Hereafter, it demonstrates in order along a time series.

Time t1: The management gaming machine 100 is powered on.
Time t2: When the power is turned on, each chip mounted on the main control board 30 and the frame control board 70 is reset, shifts to the security mode, and a security check is performed.
Time t3: When the security check ends without any problem, each chip shifts to the user mode. In response to this, the main control CPU 31 and the frame control CPU 71 execute user programs pre-stored in their internal ROMs.

Specifically, the main control CPU 31 first executes start-up processing (step A1). Here, "startup processing" means restoring the game state (so-called power recovery) based on the backup information saved at the time of the previous power shutdown, or conversely, clearing the backup information to restore the initial state of the board. It is a process for adjusting the state.

After completing the activation process, the main control CPU 31 turns on the main command permission signal (step A2). Here, the "main command" is a general term for various commands that the main control CPU 31 receives from the outside of the main control board 30, and the "main command permission signal" is the preparation for the main control CPU 31 to receive the main command. is ready (=permits transmission of the main command to the main control board 30). A main command permission signal is transmitted from the main control CPU 31 to the frame control CPU 71 .

On the other hand, the frame control CPU 71 also first executes the activation process (step B1), and after completing the execution of the activation process, turns on the frame command permission signal (step B2). Here, the "frame command" is a general term for various commands that the frame control CPU 71 receives from outside the frame control board 70, and the "frame command permission signal" is a signal that the frame control CPU 71 prepares to receive the frame command. is ready (=permission of frame command transmission to the frame control device 70). A frame command permission signal is transmitted from the frame control CPU 71 to the main control CPU 31 .

When the frame command permission signal is turned on, the main control CPU 31 determines that the frame command can be transmitted, and transmits the frame command according to the situation to the frame control CPU 71 . The transmitted frame command is received at the RX0 terminal of the frame control CPU 71 . Also, when the main command permission signal is turned on, the frame control CPU 71 determines that the main command can be sent, and sends the main command to the main control CPU 31 according to the situation. The transmitted main command is received at the RX0 terminal of the main control CPU 31 .

From a different point of view, the main control CPU 31 determines that it is impossible to transmit the frame command during the period until the frame command permission signal is turned on (time t1 to t4), and does not transmit the frame command. , when the frame command permission signal is turned on (from time t4), it is determined that the frame command can be transmitted, and the frame command is transmitted. Also, the frame control CPU 71 judges that it is impossible to transmit the main command until the main command permission signal is turned on (time t1 to t4), and does not transmit the main command. When the permission signal is turned on (from time t4), it is determined that the main command can be sent, and the main command is sent.

The main control CPU 31 and the frame control CPU 71 can appropriately execute the processing related to the game according to the main command received at its own RX0 terminal and the frame control CPU 71 according to the frame command received at its own RX0 terminal. .

Time t5: A power failure occurs during execution of the game (the power supply to the managed gaming machine 100 is cut off). When power failure occurs, the main control CPU 31 detects that the power failure signal is turned on (step A3), and immediately turns off the main command permission signal (step A4). On the other hand, when the frame control CPU 71 also detects that the power-off signal is turned on (step B3), it immediately turns off the frame command permission signal (step B4). As a result, after time t6, the main control CPU 31 stops sending frame commands, and the frame control CPU 71 stops sending main commands.

In addition, the timing of detecting the ON of the power-off signal may differ slightly between the main control CPU 31 and the frame control CPU 71 due to individual differences on the board, etc. Therefore, the situation where the command is received after the command permission signal is turned OFF. can occur. For example, when the main control CPU 31 detects that the power-off signal has been turned on slightly later than the frame control CPU 71, the frame control CPU 71 transmits the main command before the main control CPU 31 turns off the main command permission signal. . If the main command permission signal is turned off before the main control CPU 31 receives this main command, the main control CPU 31 will receive the main command after turning off the main command permission signal. In consideration of the occurrence of such a situation, each of the CPUs 31 and 71 waits for a certain period of time after turning off the command permission signal so as to be able to receive a command.

Time t7: A reset signal is input to the XSRST terminal of each of the CPUs 31 and 71 due to the power failure that occurred at time t5. After that, the mode shifts to the security mode again, and the security check is executed. Therefore, even after the reset signal is input, the main control CPU 31 transmits the frame command during the period from the end of the security check until the command permission signal is turned on again, in the same manner as the period from time t1 to t4 described above. First, the frame control CPU 71 does not transmit the main command.

As described above, in the second embodiment, the frame control CPU 71 does not transmit the main command during the period until the main command permission signal is turned on, that is, until the initial state of the main control board 30 is established. No main command is received at the RX0 terminal of the main control CPU 31 during this period. Since the main control CPU 31 does not transmit a frame command during the period until the frame command permission signal is turned on, that is, until the initial state of the frame control board 70 is completed, the RX0 terminal of the frame control CPU 71 is turned on during this period. It never receives frame commands. Therefore, by executing the above-described control, commands are not transmitted to the RX0 terminals of the CPUs 31 and 71 during the period until the initial states of the boards 30 and 70 are ready. 71 can be prevented from malfunctioning.

Note that if a problematic chip is employed in at least one of the main control board 30 and the frame control board 70, the problem chip is used for both the main control board 30 and the frame control board 70. It is necessary to apply the control configuration in the above-described second embodiment not only to the substrates that are used, but also to the substrates that have chips with no problems.

[Third embodiment]
Next, the configuration of the managed gaming machine 100 according to the third embodiment, in which countermeasures are taken from the aspect of the type of reset, will be described with respect to the chip problem described above.
FIG. 6 is a diagram illustrating user reset. There are two types of reset, system reset and user reset.

(A) in FIG. 6 shows the difference between system reset and user reset. A system reset can be performed by inputting a signal to the XSRST pin when the power is turned on or during a momentary power failure, or when a system reset is selected as the operation when an internal reset factor occurs in the setting of the program management area (KRES), which will be described later. , WDT timeout or IAT detection. On the other hand, a user reset can occur due to WDT timeout or IAT detection when user reset is selected as an operation when an internal reset factor occurs in the setting of the program management area (KRES).

Note that an IAT (Illegal Address Trap) is detected when the user program is executed outside the designated area, that is, when there is some problem with the user program. Considering that it will be put on the market, it is unlikely that the IAT will be detected in the managed gaming machine 100 that will be put on the market. Therefore, in reality, it can be said that the cause of the internal reset is the timeout of the WDT.

In both the system reset and the user reset, all registers of the CPU are initialized, and the user program pre-stored in the built-in ROM is executed from the top address 0000H, but the built-in RAM is not initialized.

In addition, in system reset, all functions are blocked, while in user reset, functions other than functions related to variable-length random numbers and fixed-length random numbers are blocked. Specifically, for variable-length random numbers, after starting random numbers that apply the setting of the maximum value setting register (setting of the maximum value of variable-length random numbers), the operation continues according to the set conditions even after a user reset occurs. do. Also, the fixed-length random numbers are automatically activated after the transition to the user mode, but continue to operate without being initialized even after the user reset occurs.

In the system reset, if there is no problem after shifting to the security mode, the system shifts to the user mode. Therefore, if a user reset is selected as the operation when an internal reset factor occurs, security mode is not entered, and security checks are not executed. Therefore, an unexpected signal is not input from the outside while security checks are being executed. Therefore, malfunction of the CPU can be prevented.

(B) in FIG. 6 represents the setting contents of a predetermined area of the program management area regarding the selection of the type of reset. The program management area is an area for storing information necessary for the CPU to execute the user program, and is assigned a predetermined address space of the built-in ROM. Information about the reset setting is stored at address 3FD9H (reset setting area KRES) of the program management area. In the reset setting area KRES, in addition to various selections regarding the WDT (timeout time, activation method, etc.), it is possible to select an operation when an internal reset factor occurs. For example, by setting the reset setting area KRES to "00H", the WDT operation is prohibited (the WDT function is disabled), and user reset is selected as the operation when an internal reset factor occurs. However, among these, bit 7 is set to select user reset.

Therefore, by setting the setting value of bit 7 of the reset setting area KRES of the built-in ROM to "0" in the main control board 30 and the frame control board 70 on which the problematic chip is adopted, When an internal reset factor occurs in the board, it is possible to directly shift to the user mode without going through the security mode, so that it is possible to prevent malfunction of the CPU in the board.

As described above, according to each embodiment described above, the following effects can be obtained.
(1) According to the first embodiment, the buffer IC is provided in front of the input signal receiving terminals (RX0, RX1) of the CPU, and input signals from the outside of the substrate are input to the CPU via the buffer IC. During the execution of the security check, the input signal is masked so that the input signal receiving terminal of the CPU does not receive an external signal as it is. It is possible to maintain a state in which the level of the input signal to the input signal receiving terminal does not change, thereby preventing malfunction of the CPU.

(2) According to the second embodiment, the main command and frame command permission signals are turned on after transitioning from the security mode to the user mode and completing execution of the activation process. is sent, and when a reset factor occurs, the main command enable signal and frame command enable signal are turned off immediately, and the main command and frame command enable signal and frame command enable signal are turned on again. Since the data is not transmitted until the user mode is changed, it is possible to prevent malfunctions of the main control CPU 31 and the frame control CPU 71 before shifting to the user mode.

(3) According to the third embodiment, by setting the value of bit 7 in a predetermined area (address 3FD9H, reset setting area KRES) in the program management area of the built-in ROM to "0", an internal reset factor is generated. Since the user reset is selected as the time operation, when an internal reset factor occurs, it is possible to shift directly to the user mode without going through the security mode, thereby preventing malfunction of the CPU on that board. can be done.

The present invention is not limited to the above-described embodiments, and can be implemented in various modifications. For example, the embodiments described above can be modified as follows.

The configuration of each embodiment described above can also be applied to a normal gaming machine that is not a managed gaming machine. Here, the "ordinary gaming machine" means, as shown in the block diagram of FIG. It refers to a gaming machine 200 having a controlling payout control device 120 and an effect control device 130 controlling effects associated with a game based on commands from the main control device 110 .

In a normal game machine, when chips with the above-described problems are adopted in either the main controller 110 or the payout controller 120, each configuration of the first embodiment and the third embodiment By applying the configuration of the second embodiment to a device that employs a problematic chip, and applying the configuration of the second embodiment to both devices, it is possible to prevent malfunctions of the CPU. .

Also, the configuration of each embodiment described above can be applied to a slot machine. That is, even in a slot machine having a main control board for controlling the execution and stopping of a game and a medal number control board for controlling the payout of medals, malfunction of the CPU, etc., can be prevented by applying the configuration of each of the above-described embodiments. can be prevented from occurring.

Although the above-described embodiments can prevent malfunctions of the CPU and the like even if they are applied alone, they may be applied in combination with the configurations of a plurality of embodiments.

10 management game machine game board 20 management game machine frame 30 main control board 31 main control CPU
32 reset circuit 33 inverter 34 buffer IC
50 effect control board 51 effect control CPU
70 frame control board 71 frame control CPU
100 management game machine

Claims (2)

having a CPU and storage means, and having control means for executing a security check before the CPU executes the user program stored in the storage means when a system reset occurs,
The control means is
A gaming machine characterized in that, during execution of the security check, an input signal from the outside of the control means is masked and output to the CPU. In the gaming machine according to claim 1,
The control means is
further comprising a control circuit to which the input signal from the outside is input;
The control circuit is
A signal of a predetermined level is input to a predetermined terminal during execution of the security check, and a signal is sent to the CPU regardless of the level of the input signal from the outside while the signal of the predetermined level is input to the predetermined terminal. A game machine characterized by not outputting.

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