JP2001127111A - Mounting substrate for semiconductor device - Google Patents

Mounting substrate for semiconductor device

Info

Publication number
JP2001127111A
JP2001127111A JP31057899A JP31057899A JP2001127111A JP 2001127111 A JP2001127111 A JP 2001127111A JP 31057899 A JP31057899 A JP 31057899A JP 31057899 A JP31057899 A JP 31057899A JP 2001127111 A JP2001127111 A JP 2001127111A
Authority
JP
Japan
Prior art keywords
mounting
semiconductor device
metal wiring
bga
connection terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP31057899A
Other languages
Japanese (ja)
Other versions
JP3801397B2 (en
Inventor
Yuichi Tanida
裕一 谷田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP31057899A priority Critical patent/JP3801397B2/en
Publication of JP2001127111A publication Critical patent/JP2001127111A/en
Application granted granted Critical
Publication of JP3801397B2 publication Critical patent/JP3801397B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Abstract

PROBLEM TO BE SOLVED: To improve reliability for mounting BGA or flip-chip connecting structure. SOLUTION: A plurality of metal electrodes 3 is provided on the lower side of a BGA package sealing a semiconductor therein, and a solder ball with a 500 μm diameter D is connected to each of the metal electrodes 3. A metal wiring 13 of 700 μm height H1 and 250 μm width W1 is formed protruded to the side of the BGA package 1 on a mounting surface 11a of a mounting substrate 11 in its position corresponding to each of the solder ball 5 in the BGA package 1. The solder balls in relation to metal wirings 9 are connected to each of the metal wiring 9. Even though stress is generated due to difference in coefficient of thermal expansion between the BGA package 1 and the mounting substrate 11 on mounting or after mounting, deformation of the metal wiring 13 can absorb the stress.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、下面に複数のボー
ル状の接続端子が接続された半導体装置の接続端子と金
属配線が接続されて半導体装置が面実装される半導体装
置の実装基板に関するものである。より具体的には、B
GA(Ball Grid Array,米国特許第5148265号
参照)実装された半導体装置の接続や、フリップチップ
接続に用いる実装基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting board for a semiconductor device in which a plurality of ball-shaped connecting terminals are connected to a lower surface of a semiconductor device and metal wiring is connected to the semiconductor device and the semiconductor device is surface-mounted. It is. More specifically, B
The present invention relates to a mounting substrate used for connection of a semiconductor device mounted with a GA (Ball Grid Array, US Pat. No. 5,148,265) and flip-chip connection.

【0002】[0002]

【従来の技術】現在、半導体チップを封止したパッケー
ジの下面に半田ボール等の接続端子を有する半導体装置
として、BGAやμBGA(端子ピッチが0.8mm以
下のBGAであり、CSP(Chip Scale Package)とも
いう)などが存在する。BGAやμBGAを用いた実装
構造(以下、BGA実装構造という)は、複数のリード
をパッケージ周辺から取り出したQFP(Quad Flat Pa
ckage)を実装した場合に比べて、搭載面積を小さくで
きるので高密度搭載に適するという利点がある。
2. Description of the Related Art At present, as a semiconductor device having connection terminals such as solder balls on the lower surface of a package in which a semiconductor chip is sealed, a BGA or a μBGA (a BGA having a terminal pitch of 0.8 mm or less, a CSP (Chip Scale Package)). )). A mounting structure using a BGA or μBGA (hereinafter referred to as a BGA mounting structure) is a QFP (Quad Flat Pa) in which a plurality of leads are taken out from the periphery of a package.
In this case, the mounting area can be reduced as compared with the case where the ckage is mounted.

【0003】図1は、(A)は従来の実装基板を示す断
面図、(B)はその実装基板を用いたBGA実装構造を
示す断面図である。半導体チップを封止したBGAパッ
ケージ1は、その下面1aに複数の金属電極3が設けら
れ、各金属電極3には、接続端子としての半田ボール5
がそれぞれ接続されている。実装基板7のBGAパッケ
ージ1に対向する実装面7aの、BGAパッケージ1の
各半田ボール5に対応する位置に金属配線9が設けられ
ている。金属配線9の厚さは例えばJIS規格の材料厚
さとして用いられている18μmや50μm等であり、
その厚さはいずれも半田ボール5のボール径よりも小さ
い。各金属配線9には、対応する半田ボール5がそれぞ
れ接続される。
FIG. 1A is a sectional view showing a conventional mounting board, and FIG. 1B is a sectional view showing a BGA mounting structure using the mounting board. In a BGA package 1 in which a semiconductor chip is sealed, a plurality of metal electrodes 3 are provided on a lower surface 1a, and each metal electrode 3 has a solder ball 5 as a connection terminal.
Are connected respectively. A metal wiring 9 is provided on a mounting surface 7 a of the mounting board 7 facing the BGA package 1 at a position corresponding to each solder ball 5 of the BGA package 1. The thickness of the metal wiring 9 is, for example, 18 μm or 50 μm, which is used as the material thickness of the JIS standard,
Each of the thicknesses is smaller than the ball diameter of the solder ball 5. The corresponding solder balls 5 are connected to the respective metal wires 9.

【0004】また、高密度搭載を実現する実装構造とし
て、半導体チップの能動素子面を、半田ボール等の接続
端子を介して、実装基板に直接接続するフリップチップ
接続構造がある。フリップチップ接続構造も、BGA実
装構造と同様に、搭載面積を小さくできるので高密度搭
載に適する。
As a mounting structure for realizing high-density mounting, there is a flip-chip connection structure in which an active element surface of a semiconductor chip is directly connected to a mounting substrate via connection terminals such as solder balls. The flip-chip connection structure is also suitable for high-density mounting, since the mounting area can be reduced similarly to the BGA mounting structure.

【0005】[0005]

【発明が解決しようとする課題】しかし、BGA実装構
造では、パッケージをガラスエポキシなどの実装基板に
実装すると、パッケージと実装基板との熱膨張係数の違
いによって応力が生じ、その応力が金属配線と接続端子
の接合部分付近に集中して接続端子にクラックが生じて
接合不良を起こすことが一般的に知られている。フリッ
プチップ接続構造でも、半導体チップと実装基板との熱
膨張係数の違いによって応力が生じ、接続端子にクラッ
クが生じて接合不良を起こすことが一般的に知られてい
る。
However, in the BGA mounting structure, when the package is mounted on a mounting substrate such as glass epoxy, a stress is generated due to a difference in thermal expansion coefficient between the package and the mounting substrate, and the stress is generated by the metal wiring. It is generally known that cracks are generated in the connection terminals in the vicinity of the connection portions of the connection terminals, resulting in poor connection. It is generally known that even in the flip-chip connection structure, a stress is generated due to a difference in thermal expansion coefficient between the semiconductor chip and the mounting substrate, and a crack occurs in the connection terminal to cause a bonding failure.

【0006】このような不具合を回避するため、特開平
09−129789号公報、特開平09−199540
号公報、特開平10−173006号公報等で接続後の
信頼性を向上させる発明が公開されているが、接続端子
(半田ボール等)の構造や大きさ・形状に特徴を持たせ
るか、あるいは接続端子(半田ボール等)の接続部分を
凹型にするなどといったものであり、何れもパッケージ
に特徴を持たせることで問題を解決しており、実装基板
にのみ特徴を持たせることによって効果を得るものでは
ない。
In order to avoid such problems, Japanese Patent Application Laid-Open No. 09-129789 and Japanese Patent Application Laid-Open No. 09-199540
And Japanese Patent Application Laid-Open No. H10-173006 disclose inventions for improving reliability after connection. However, the structure, size, and shape of connection terminals (such as solder balls) are characterized by The connection portion of the connection terminal (solder ball or the like) is formed in a concave shape, and the problem is solved by giving a characteristic to the package, and the effect is obtained by giving the characteristic only to the mounting board. Not something.

【0007】そこで本発明は、BGA実装構造又はフリ
ップチップ接続構造において、実装基板の配線構造に特
徴を持たせることにより、パッケージ又は半導体チップ
を実装基板に実装した後の熱膨張係数の差による応力を
分散させ、実装後の信頼性の向上させることを目的とす
るものである。
Accordingly, the present invention provides a BGA mounting structure or a flip-chip connection structure in which a wiring structure of a mounting substrate is characterized by a stress caused by a difference in thermal expansion coefficient after mounting a package or a semiconductor chip on the mounting substrate. And to improve the reliability after mounting.

【0008】[0008]

【課題を解決するための手段】本発明は、下面に複数の
ボール状の接続端子が接続された半導体装置の接続端子
と金属配線が接続されて半導体装置が面実装される半導
体装置の実装基板であって、その金属配線は、少なくと
も接続端子が接続される位置では、厚さが接続前の接続
端子の高さ以上になっているものである。
According to the present invention, there is provided a mounting board for a semiconductor device in which a plurality of ball-shaped connecting terminals are connected to a lower surface of the semiconductor device and the metal wiring is connected to the semiconductor device and the semiconductor device is surface-mounted. The thickness of the metal wiring is greater than the height of the connection terminal before connection at least at a position where the connection terminal is connected.

【0009】金属配線は、少なくとも接続端子が接続さ
れる位置では、厚さが接続前の接続端子の高さ以上にな
っていることより、金属配線が変形して、パッケージ又
は半導体チップと実装基板との熱膨張係数の違いによっ
て生じる応力を吸収する。その結果、接続端子と金属配
線の接合部分付近に応力が集中することを防止すること
ができ、接続端子の疲労破壊を抑制することができる。
At least at the position where the connection terminal is connected, the thickness of the metal wiring is equal to or greater than the height of the connection terminal before connection. Absorbs the stress caused by the difference in the coefficient of thermal expansion. As a result, it is possible to prevent stress from being concentrated near the joint between the connection terminal and the metal wiring, and it is possible to suppress fatigue damage of the connection terminal.

【0010】[0010]

【発明の実施の形態】接続前の接続端子の高さ以上の寸
法で半導体装置側に突出し、半導体装置のパッケージの
下面を支持する支持部材をさらに備えていることが好ま
しい。その結果、接続した状態で金属配線が半導体装置
の電極に到達していなくても、その間を接続端子自体に
よって埋めることができるようになるので、金属配線の
厚さを薄くしても応力を吸収できるようになる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS It is preferable that the semiconductor device further includes a support member that projects toward the semiconductor device with a dimension not less than the height of the connection terminal before connection and supports the lower surface of the package of the semiconductor device. As a result, even if the metal wiring does not reach the electrode of the semiconductor device in the connected state, the gap can be filled with the connection terminal itself, so that the stress can be absorbed even if the thickness of the metal wiring is reduced. become able to.

【0011】少なくとも一部の金属配線の周囲に、金属
配線の厚さよりも大きい寸法で半導体装置側に突出し、
その先端部分には接続端子側に向かって高さが低くなる
ように傾斜した案内面が形成された案内部材をさらに備
えていることが好ましい。その結果、実装時のアライメ
ント精度を緩和して実装性を向上させることができる。
支持部材の先端部分には接続端子側に向かって高さが低
くなるように傾斜した案内面が形成されていることが好
ましい。その結果、支持部材は案内部材を兼ねることが
できる。
[0011] At least a part of the metal wiring is projected toward the semiconductor device with a dimension larger than the thickness of the metal wiring,
It is preferable that the distal end portion further includes a guide member having a guide surface inclined so that the height decreases toward the connection terminal. As a result, the alignment accuracy at the time of mounting can be relaxed and the mountability can be improved.
It is preferable that a guide surface that is inclined so that the height decreases toward the connection terminal side is formed at a tip portion of the support member. As a result, the support member can also serve as the guide member.

【0012】[0012]

【実施例】図2は、一実施例をBGA実装構造に適用し
た例を示す断面図であリ、(A)は実装基板、(B)は
BGA実装構造を示す。半導体チップを封止したBGA
パッケージ1の下面1aに複数の金属電極3が設けら
れ、各金属電極3には、接続端子としての半田ボール5
がそれぞれ接続されている。半田ボール5の直径寸法D
は例えば500μmである。半田ボール5は、例えば予
め金属電極3に供給した状態で、リフロー炉を通過させ
ることによって半田ボール5が溶融して金属電極3に接
続される。
FIG. 2 is a sectional view showing an example in which one embodiment is applied to a BGA mounting structure. FIG. 2A shows a mounting substrate, and FIG. 2B shows a BGA mounting structure. BGA sealed semiconductor chip
A plurality of metal electrodes 3 are provided on the lower surface 1a of the package 1, and each metal electrode 3 has a solder ball 5 as a connection terminal.
Are connected respectively. Diameter D of solder ball 5
Is, for example, 500 μm. The solder balls 5 are connected to the metal electrodes 3 by, for example, being supplied to the metal electrodes 3 in advance and passing through a reflow furnace so that the solder balls 5 are melted.

【0013】実装基板11は、そのBGAパッケージ1
に対向する実装面11aの、BGAパッケージ1の各半
田ボール5に対応する位置に金属配線13がBGAパッ
ケージ1側に突出して設けられている。金属配線13
は、材料はCuやAu、Ni、Alなどが用いられ、形
状は例えば直方状であり、高さ(厚さ)H1は700μ
mであり、幅W1は250μmである。実装基板11の
実装面11aには、金属配線13に接続されている配線
パターン(図示は省略)が形成されている。
The mounting board 11 includes the BGA package 1
A metal wiring 13 is provided at a position corresponding to each solder ball 5 of the BGA package 1 on the mounting surface 11a opposed to the BGA package 1 so as to protrude toward the BGA package 1 side. Metal wiring 13
Is made of Cu, Au, Ni, Al, or the like, and has a rectangular shape, for example, and a height (thickness) H1 of 700 μm.
m, and the width W1 is 250 μm. On the mounting surface 11a of the mounting substrate 11, a wiring pattern (not shown) connected to the metal wiring 13 is formed.

【0014】各金属配線13には、(B)に示すよう
に、対応する半田ボール5がそれぞれ接続される。半田
ボール5は、例えば予め実装基板11の対応する金属配
線13に位置決めされた状態で、リフロー炉を通過させ
ることによって半田ボール5が溶融して金属配線13に
接続される。
As shown in FIG. 2B, corresponding solder balls 5 are connected to the respective metal wirings 13. The solder balls 5 are melted and connected to the metal wires 13 by passing through a reflow furnace, for example, in a state where the solder balls 5 are positioned on the corresponding metal wires 13 of the mounting board 11 in advance.

【0015】このような構造にすることにより、実装時
又は実装後にBGAパッケージ1と実装基板11の熱膨
張係数の違いによって応力が生じても、金属配線13が
変形して応力を吸収し、半田ボール5と金属電極3、金
属配線13の接合部分にのみ応力が集中することを防止
して、応力に起因する半田ボール5のクラックの発生を
防止することができ、実装信頼性を向上させることがで
きる。
With such a structure, even if stress is generated due to a difference in the coefficient of thermal expansion between the BGA package 1 and the mounting substrate 11 during or after mounting, the metal wiring 13 is deformed to absorb the stress, and It is possible to prevent stress from being concentrated only at the joint between the ball 5 and the metal electrode 3 or the metal wiring 13, thereby preventing cracks in the solder ball 5 caused by the stress and improving mounting reliability. Can be.

【0016】図3は、他の実施例をBGA実装構造に適
用した例を示す断面図であリ、(A)は実装基板、
(B)はBGA実装構造を示す。実装基板15は、その
BGAパッケージ1に対向する実装面15aの、BGA
パッケージ1の各半田ボール5に対応する位置に図2と
同様の金属配線17がBGAパッケージ1側に突出して
設けられている。金属配線17の高さH2は300μm
であり、幅W2は300μmである。
FIG. 3 is a sectional view showing an example in which another embodiment is applied to a BGA mounting structure.
(B) shows a BGA mounting structure. The mounting board 15 is provided on the mounting surface 15a of the mounting surface 15a facing the BGA package 1.
At the position corresponding to each solder ball 5 of the package 1, a metal wiring 17 similar to that of FIG. 2 is provided so as to protrude toward the BGA package 1. The height H2 of the metal wiring 17 is 300 μm
And the width W2 is 300 μm.

【0017】実装基板15の実装面15aには、実装時
にBGAパッケージ1を実装基板15との間に間隔を保
持して支持し、BGAパッケージ1の実装基板15側へ
の接近自由度を抑制する複数の支持部材19がBGAパ
ッケージ1側に突出して設けられている。支持部材19
は、材料は実装基板15と同じ材料やレジスト材料など
の絶縁材料が用いられ、例えば直方状であり、高さH3
は600μmであり、幅W3は200μmである。
The BGA package 1 is supported on the mounting surface 15a of the mounting board 15 with a space between the mounting board 15 and the mounting board 15 during mounting, and the degree of freedom of approach of the BGA package 1 to the mounting board 15 is suppressed. A plurality of support members 19 are provided to protrude toward the BGA package 1. Support member 19
Is made of the same material as the mounting substrate 15 or an insulating material such as a resist material.
Is 600 μm, and the width W3 is 200 μm.

【0018】各金属配線17には、(B)に示すよう
に、対応する半田ボール5がそれぞれ接続される。半田
ボール5は、BGAパッケージ1の下面1aが支持部材
19の上端面に支持されて、実装基板11の対応する金
属配線17に位置決めされた状態で、リフロー炉を通過
させることによって半田ボール5が溶融して金属配線1
7に接続される。金属配線17の高さH2は、図2の金
属配線13の高さH1に比較して低いが、高さH3の支
持部材19によって実装基板15に対して所定の間隔を
保持してBGAパッケージ1の下面1aを支持すること
により、金属配線17と金属電極3との間に厚さの一定
した半田ボール5を介在させることができる。
The corresponding solder balls 5 are connected to the respective metal wirings 17 as shown in FIG. The solder balls 5 are passed through a reflow furnace in a state where the lower surface 1a of the BGA package 1 is supported on the upper end surface of the support member 19 and positioned on the corresponding metal wiring 17 of the mounting board 11, so that the solder balls 5 Molten metal wiring 1
7 is connected. Although the height H2 of the metal wiring 17 is lower than the height H1 of the metal wiring 13 in FIG. 2, the BGA package 1 is held at a predetermined distance from the mounting board 15 by the supporting member 19 having a height H3. By supporting the lower surface 1a, the solder ball 5 having a constant thickness can be interposed between the metal wiring 17 and the metal electrode 3.

【0019】このような構造にすることにより、実装時
にBGAパッケージ1と実装基板15の熱膨張係数の違
いによって応力が生じても、金属配線17と半田ボール
5が変形して応力を吸収し、半田ボール5と金属電極
3、金属配線17の接合部分にのみ応力が集中すること
を防止して、応力に起因する半田ボール5のクラックの
発生を防止することができ、実装信頼性を向上させるこ
とができる。この実施例では、支持部材としての支持部
材19が金属配線17,17間にそれぞれ設けられてい
るが、支持部材の形状、配置及び数はこれに限定される
ものではなく、実装基板との間に所定の間隔を保持して
パッケージの下面を支持できる構成であれば、どのよう
な形状、配置及び数であってもよい。
By adopting such a structure, even when a stress is generated due to a difference in thermal expansion coefficient between the BGA package 1 and the mounting board 15 during mounting, the metal wiring 17 and the solder ball 5 are deformed to absorb the stress, and It is possible to prevent stress from being concentrated only at the joint between the solder ball 5 and the metal electrode 3 or the metal wiring 17, thereby preventing cracking of the solder ball 5 due to the stress and improving mounting reliability. be able to. In this embodiment, the support members 19 as the support members are provided between the metal wirings 17, respectively. However, the shape, arrangement and number of the support members are not limited to these, and the support members 19 may be disposed between the metal wirings 17 and 17. Any shape, arrangement, and number may be used as long as the structure can support the lower surface of the package while maintaining a predetermined interval.

【0020】図4は、さらに他の実施例をBGA実装構
造に適用した例を示す断面図であリ、(A)は実装基
板、(B)はBGAパッケージ実装前の実装基板及びB
GAパッケージを示す。実装基板21は、そのBGAパ
ッケージ1に対向する実装面21aの、BGAパッケー
ジ1の各半田ボール5に対応する位置に図2と同様の金
属配線23がBGAパッケージ1側に突出して設けられ
ている。金属配線23の高さH4は700μmであり、
幅W4は250μmである。
FIGS. 4A and 4B are cross-sectional views showing an example in which still another embodiment is applied to a BGA mounting structure. FIG. 4A is a mounting board, and FIG. 4B is a mounting board before mounting a BGA package.
4 shows a GA package. The mounting substrate 21 has a metal wiring 23 similar to that of FIG. 2 protruding toward the BGA package 1 at a position corresponding to each solder ball 5 of the BGA package 1 on a mounting surface 21 a facing the BGA package 1. . The height H4 of the metal wiring 23 is 700 μm,
The width W4 is 250 μm.

【0021】実装基板21の実装面21aには、金属配
線23に接近して、実装時に半田ボール5を対応する金
属配線23の先端に案内する複数の案内部材25がBG
Aパッケージ1側に突出して設けられている。案内部材
25は、材料は実装基板21と同じ材料やレジスト材料
などの絶縁材料が用いられ、形状は先端面から金属配線
23に対向する側面に向かって面取りされて案内面25
aが形成された直方状であり、高さH5は600μmで
あり、幅W5は500μmである。
On the mounting surface 21a of the mounting board 21, a plurality of guide members 25 which approach the metal wiring 23 and guide the solder balls 5 to the front ends of the corresponding metal wiring 23 during mounting are provided with BGs.
It protrudes from the A package 1 side. The guide member 25 is made of the same material as that of the mounting substrate 21 or an insulating material such as a resist material. The shape of the guide member 25 is chamfered from the front end surface to the side surface facing the metal wiring 23 and the guide surface 25 is formed.
a is formed, the height H5 is 600 μm, and the width W5 is 500 μm.

【0022】BGAパッケージ1の実装時において、半
田ボール5が実装基板21の対応する金属配線23に位
置決めされた状態で、リフロー炉を通過させることによ
って半田ボール5が溶融して金属配線23に接続され
る。その位置決めの際に、半田ボール5の位置が金属配
線23に対してずれていても、半田ボール5は案内部材
25の案内面25aによって対応する金属配線23に位
置決めされるので、アライメント精度を緩和して実装性
を向上させることができる。このとき、金属配線23と
案内部材25が互いに接触しないように、予め金属配線
23と案内部材25との間に100μm程度の空間を設
けておくことが好ましい。これにより、実装後の熱膨張
係数の違いによる応力の吸収が円滑に行なわれる。この
実施例では、案内部材25が金属配線23,23間にそ
れぞれ設けられているが、案内部材25の形状、配置及
び数はこれに限定されるものではなく、接続端子を実装
基板の対応する金属配線に案内できる構成であれば、ど
のような形状、配置及び数であってもよい。
At the time of mounting the BGA package 1, the solder balls 5 are melted by passing through a reflow furnace while being positioned on the corresponding metal wirings 23 of the mounting board 21, and are connected to the metal wirings 23. Is done. At the time of the positioning, even if the position of the solder ball 5 is shifted with respect to the metal wiring 23, the solder ball 5 is positioned on the corresponding metal wiring 23 by the guide surface 25a of the guide member 25, so that the alignment accuracy is eased. As a result, the mountability can be improved. At this time, it is preferable to provide a space of about 100 μm between the metal wiring 23 and the guide member 25 in advance so that the metal wiring 23 and the guide member 25 do not contact each other. Thereby, the absorption of stress due to the difference in the coefficient of thermal expansion after mounting is performed smoothly. In this embodiment, the guide members 25 are provided between the metal wirings 23, 23. However, the shape, arrangement and number of the guide members 25 are not limited to these, and the connection terminals correspond to those of the mounting board. Any shape, arrangement, and number may be used as long as it can be guided to the metal wiring.

【0023】図5は、さらに他の実施例をBGA実装構
造に適用した例を示す断面図であリ、(A)は実装基
板、(B)はBGA実装構造を示す。実装基板27は、
そのBGAパッケージ1に対向する実装面27aの、B
GAパッケージ1の各半田ボール5に対応する位置に図
2と同様の金属配線29がBGAパッケージ1側に突出
して設けられている。金属配線29の高さH6は300
μmであり、幅W6は300μmである。実装基板27
の実装面27aには、金属配線29に接続されている配
線パターン(図示は省略)が形成されている。
FIGS. 5A and 5B are cross-sectional views showing an example in which still another embodiment is applied to a BGA mounting structure. FIG. 5A shows a mounting substrate, and FIG. 5B shows a BGA mounting structure. The mounting board 27
B of the mounting surface 27a facing the BGA package 1
At the position corresponding to each solder ball 5 of the GA package 1, the same metal wiring 29 as that of FIG. 2 is provided so as to protrude toward the BGA package 1. The height H6 of the metal wiring 29 is 300
μm, and the width W6 is 300 μm. Mounting board 27
A wiring pattern (not shown) connected to the metal wiring 29 is formed on the mounting surface 27a.

【0024】実装基板27の実装面27aには、実装時
にBGAパッケージ1を実装基板27との間に間隔を保
持して支持し、BGAパッケージ1の実装基板27側へ
の接近自由度を抑制するとともに、半田ボール5を対応
する金属配線29の先端に案内する複数の支持・案内部
材31がBGAパッケージ1側に突出して設けられてい
る。支持・案内部材31は、材料は実装基板27と同じ
材料やレジスト材料などの絶縁材料が用いられ、例えば
形状は端面から金属配線29に対向する側面に向かって
面取りされて案内面31aが形成された直方状であり、
高さH7は600μmであり、幅W7は500μmであ
る。
The BGA package 1 is supported on the mounting surface 27a of the mounting board 27 with a space between the mounting board 27 and the mounting board 27 during mounting, and the degree of freedom of approach of the BGA package 1 to the mounting board 27 is suppressed. In addition, a plurality of support / guide members 31 for guiding the solder balls 5 to the tips of the corresponding metal wirings 29 are provided so as to protrude toward the BGA package 1. The supporting / guiding member 31 is made of the same material as the mounting substrate 27 or an insulating material such as a resist material. For example, the shape of the supporting / guiding member 31 is chamfered from an end surface toward a side surface facing the metal wiring 29 to form a guide surface 31a. Is rectangular,
The height H7 is 600 μm and the width W7 is 500 μm.

【0025】各金属配線29には、対応する半田ボール
5がそれぞれ接続される。半田ボール5は、BGAパッ
ケージ1の下面1aが支持・案内部材31の上端面に支
持されて、実装基板27の対応する金属配線29に位置
決めされた状態で、リフロー炉を通過させることによっ
て半田ボール5が溶融して金属配線29に接続される。
その位置決めの際に、半田ボール5の位置が金属配線2
9に対してずれていても、半田ボール5は支持・案内部
材31の案内面31aによって対応する金属配線29に
位置決めされるので、アライメント精度を緩和して実装
性を向上させることができる。
Each metal wiring 29 is connected to a corresponding solder ball 5. The solder balls 5 are passed through a reflow furnace with the lower surface 1a of the BGA package 1 supported on the upper end surface of the support / guide member 31 and positioned on the corresponding metal wiring 29 of the mounting board 27. 5 is melted and connected to the metal wiring 29.
At the time of the positioning, the position of the solder ball 5 is
9, the solder balls 5 are positioned on the corresponding metal wirings 29 by the guide surfaces 31a of the support / guide members 31, so that the alignment accuracy can be relaxed and the mountability can be improved.

【0026】支持・案内部材31の形状、配置及び数は
この実施例に限定されるものではなく、接続端子を実装
基板の対応する金属配線に案内でき、かつ実装基板との
間に所定の間隔を保持してパッケージの下面を支持でき
る構成であれば、どのような形状、配置及び数であって
もよい。
The shape, arrangement and number of the supporting / guiding members 31 are not limited to those in this embodiment, and the connection terminals can be guided to the corresponding metal wiring on the mounting board and have a predetermined distance from the mounting board. Any shape, arrangement, and number may be used as long as it can hold the lower surface of the package while holding the.

【0027】これらの実施例では実装基板の金属配線の
半田ボールに対応する部分のみがパッケージ側に突出し
ているが、金属配線のすべてが突出していてもよいし、
半田ボールに対応する部分が突出していればその他の部
分が突出していてもよい。また、これらの実施例はBG
A実装構造に適用しているが、フリップチップ実装構造
に適用することもできる。
In these embodiments, only the portion of the metal wiring of the mounting board corresponding to the solder ball protrudes toward the package. However, all of the metal wiring may protrude.
Other portions may protrude as long as the portion corresponding to the solder ball protrudes. Also, these embodiments are based on BG
Although it is applied to the A mounting structure, it can be applied to a flip chip mounting structure.

【0028】[0028]

【発明の効果】本発明の半導体装置の実装基板は、下面
に複数のボール状の接続端子が接続された半導体装置の
接続端子と金属配線が接続されて半導体装置が面実装さ
れる半導体装置の実装基板であって、その金属配線は、
少なくとも接続端子が接続される位置では、厚さが接続
前の接続端子の高さ以上になっており、金属配線が変形
して、パッケージ又は半導体チップと実装基板との熱膨
張係数の違いによって生じる応力を吸収し、パッケージ
又は半導体チップを実装基板に実装した後の熱膨張係数
の差による応力を分散させて接続端子と金属配線の接合
部分付近に応力が集中することを防止するようにしたの
で、接続端子の疲労破壊を抑制することができ、実装後
の信頼性の向上させることができる。
According to the present invention, there is provided a mounting board for a semiconductor device in which a plurality of ball-shaped connecting terminals are connected to a lower surface of the semiconductor device and the metal wiring is connected to the semiconductor device. A mounting board, the metal wiring of which is
At least at the position where the connection terminal is connected, the thickness is equal to or greater than the height of the connection terminal before connection, and the metal wiring is deformed, which is caused by a difference in thermal expansion coefficient between the package or the semiconductor chip and the mounting substrate. Since the stress is absorbed and the stress due to the difference in thermal expansion coefficient after mounting the package or semiconductor chip on the mounting board is dispersed, the stress is prevented from being concentrated near the joint between the connection terminal and the metal wiring. In addition, fatigue damage of the connection terminal can be suppressed, and reliability after mounting can be improved.

【0029】さらに、接続前の接続端子の高さ以上の寸
法で半導体装置側に突出し、半導体装置のパッケージの
下面を支持する支持部材を備えているようにすれば、接
続した状態で金属配線が半導体装置の電極に到達してい
なくても、その間を接続端子自体によって埋めることが
できるようになるので、金属配線の厚さを薄くしても応
力を吸収できるようになる。さらに、少なくとも一部の
金属配線の周囲に、金属配線の厚さよりも大きい寸法で
半導体装置側に突出し、その先端部分には接続端子側に
向かって高さが低くなるように傾斜した案内面が形成さ
れた案内部材をさらに備えているようにすれば、実装時
のアライメント精度を緩和して実装性を向上させること
ができる。さらに、支持部材の先端部分には接続端子側
に向かって高さが低くなるように傾斜した案内面が形成
されているようにすれば、支持部材は案内部材を兼ねる
ことができる。
Furthermore, if a supporting member is provided which protrudes toward the semiconductor device with a dimension not less than the height of the connection terminal before connection and supports the lower surface of the package of the semiconductor device, the metal wiring in the connected state is provided. Even if the electrode does not reach the electrode of the semiconductor device, the space therebetween can be filled with the connection terminal itself, so that stress can be absorbed even if the thickness of the metal wiring is reduced. Further, a guide surface that protrudes toward the semiconductor device with a dimension larger than the thickness of the metal wiring around at least a part of the metal wiring, and has a guide surface that is inclined at the tip portion so that the height decreases toward the connection terminal side. If the formed guide member is further provided, the alignment accuracy at the time of mounting can be relaxed and the mountability can be improved. Furthermore, if a guide surface that is inclined so as to decrease in height toward the connection terminal side is formed at the distal end portion of the support member, the support member can also serve as the guide member.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 (A)は従来の実装基板を示す断面図、
(B)はその実装基板を用いたBGA実装構造を示す断
面図である。
FIG. 1A is a cross-sectional view showing a conventional mounting board,
(B) is a sectional view showing a BGA mounting structure using the mounting substrate.

【図2】 一実施例をBGA実装構造に適用した例を示
す断面図であリ、(A)は実装基板、(B)はBGA実
装構造を示す。
FIGS. 2A and 2B are cross-sectional views showing an example in which one embodiment is applied to a BGA mounting structure, wherein FIG. 2A shows a mounting substrate and FIG. 2B shows a BGA mounting structure.

【図3】 他の実施例をBGA実装構造に適用した例を
示す断面図であリ、(A)は実装基板、(B)はBGA
実装構造を示す。
3A and 3B are cross-sectional views illustrating an example in which another embodiment is applied to a BGA mounting structure, wherein FIG. 3A is a mounting board, and FIG.
The mounting structure is shown.

【図4】 さらに他の実施例をBGA実装構造に適用し
た例を示す断面図であリ、(A)は実装基板、(B)は
BGAパッケージ実装前の実装基板及びBGAパッケー
ジを示す。
4A and 4B are cross-sectional views illustrating an example in which still another embodiment is applied to a BGA mounting structure, wherein FIG. 4A illustrates a mounting substrate, and FIG. 4B illustrates a mounting substrate and a BGA package before mounting a BGA package.

【図5】 さらに他の実施例をBGA実装構造に適用し
た例を示す断面図であリ、(A)は実装基板、(B)は
BGA実装構造を示す。
5A and 5B are cross-sectional views showing an example in which still another embodiment is applied to a BGA mounting structure, wherein FIG. 5A shows a mounting substrate, and FIG. 5B shows a BGA mounting structure.

【符号の説明】[Explanation of symbols]

1 BGAパッケージ 1a BGAパッケージの下面 3 金属電極 5 半田ボール 7,11,15,21,27 実装基板 7a,11a,15a,21a,27a 実装面 9,13,17,23,29 金属配線 19 支持部材 25 案内部材 31 支持・案内部材 Reference Signs List 1 BGA package 1a Lower surface of BGA package 3 Metal electrode 5 Solder ball 7, 11, 15, 21, 27 Mounting substrate 7a, 11a, 15a, 21a, 27a Mounting surface 9, 13, 17, 23, 29 Metal wiring 19 Support member 25 guide member 31 support / guide member

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 下面に複数のボール状の接続端子が接続
された半導体装置の接続端子と金属配線が接続されて半
導体装置が面実装される半導体装置の実装基板におい
て、 前記金属配線は、少なくとも前記接続端子が接続される
位置では、厚さが接続前の接続端子の高さ以上になって
いることを特徴とする半導体装置の実装基板。
1. A mounting board for a semiconductor device in which a plurality of ball-shaped connection terminals are connected to a connection terminal of a semiconductor device and a metal wiring is connected to a lower surface of the semiconductor device, and wherein the semiconductor device is surface-mounted. A mounting board for a semiconductor device, wherein a thickness of the connection terminal is higher than a height of the connection terminal before connection at a position where the connection terminal is connected.
【請求項2】 接続前の前記接続端子の高さ以上の寸法
で前記半導体装置側に突出し、前記半導体装置のパッケ
ージの下面を支持する支持部材をさらに備えた請求項1
に記載の実装基板。
2. The semiconductor device according to claim 1, further comprising a support member projecting toward the semiconductor device with a dimension not less than the height of the connection terminal before connection, and supporting a lower surface of a package of the semiconductor device.
The mounting board according to 1.
【請求項3】 少なくとも一部の前記金属配線の周囲
に、前記金属配線の厚さよりも大きい寸法で前記半導体
装置側に突出し、その先端部分には前記接続端子側に向
かって高さが低くなるように傾斜した案内面が形成され
た案内部材をさらに備えた請求項1又は2に記載の半導
体装置の実装基板。
3. The semiconductor device protrudes around at least a part of the metal wiring with a dimension larger than the thickness of the metal wiring toward the semiconductor device, and has a tip portion having a height decreasing toward the connection terminal. 3. The mounting board for a semiconductor device according to claim 1, further comprising a guide member having a guide surface inclined as described above.
【請求項4】 前記支持部材の先端部分には前記接続端
子側に向かって高さが低くなるように傾斜した案内面が
形成されている請求項2に記載の半導体装置の実装基
板。
4. The mounting board for a semiconductor device according to claim 2, wherein a guide surface inclined so as to decrease in height toward the connection terminal is formed at a tip portion of the support member.
JP31057899A 1999-11-01 1999-11-01 Semiconductor device mounting substrate and semiconductor device mounting body Expired - Fee Related JP3801397B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31057899A JP3801397B2 (en) 1999-11-01 1999-11-01 Semiconductor device mounting substrate and semiconductor device mounting body

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31057899A JP3801397B2 (en) 1999-11-01 1999-11-01 Semiconductor device mounting substrate and semiconductor device mounting body

Publications (2)

Publication Number Publication Date
JP2001127111A true JP2001127111A (en) 2001-05-11
JP3801397B2 JP3801397B2 (en) 2006-07-26

Family

ID=18006934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31057899A Expired - Fee Related JP3801397B2 (en) 1999-11-01 1999-11-01 Semiconductor device mounting substrate and semiconductor device mounting body

Country Status (1)

Country Link
JP (1) JP3801397B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100715971B1 (en) * 2001-04-13 2007-05-08 삼성전자주식회사 Wafer level chip scale package and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100715971B1 (en) * 2001-04-13 2007-05-08 삼성전자주식회사 Wafer level chip scale package and manufacturing method thereof

Also Published As

Publication number Publication date
JP3801397B2 (en) 2006-07-26

Similar Documents

Publication Publication Date Title
JP2000077563A (en) Semiconductor device and its manufacture
JPH10275828A (en) Mounting structure of semiconductor device and inspection method therefor
JP2008181908A (en) Semiconductor device and lead frame therefor
JP2002118205A (en) Ball grid array package and circuit board used therefor
JP3150253B2 (en) Semiconductor device, its manufacturing method and mounting method
JPH10199912A (en) Semiconductor device
KR20020044577A (en) Advanced flip-chip join package
JPH10189806A (en) Semiconductor device and junction structure of semiconductor device and substrate
JP3801397B2 (en) Semiconductor device mounting substrate and semiconductor device mounting body
US6331738B1 (en) Semiconductor device having a BGA structure
TWI378546B (en) Substrate and package for micro bga
JP2000133668A (en) Semiconductor device and packaging structure
JPH10189863A (en) Mounting board
US20040080034A1 (en) Area array semiconductor device and electronic circuit board utilizing the same
JP2000307016A (en) Semiconductor device, semiconductor module and manufacture thereof
JPH10242328A (en) Circuit board, circuit module having the circuit board and electronic equipment having the circuit module
JP2002359336A (en) Semiconductor device
JP2001118951A (en) Semiconductor device
JP2001044307A (en) Semiconductor device and manufacture thereof
JP2005167074A (en) Semiconductor device
JP2715974B2 (en) Semiconductor device and manufacturing method thereof
JP2000232181A (en) Semiconductor devices of bga and lga structures, and manufacture thereof
JP3127948B2 (en) Semiconductor package and mounting method thereof
JP2730304B2 (en) Semiconductor device
JPS60165742A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050111

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20051121

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20051129

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060127

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060221

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060331

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20060425

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20060425

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100512

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110512

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120512

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120512

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130512

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140512

Year of fee payment: 8

LAPS Cancellation because of no payment of annual fees