JP2001118949A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device wherein a semiconductor chip and an interposer are arranged side by side on a carrier tape and which can provide good electrical characteristics with use of a short wiring pattern substantially symmetrical with respect to the semiconductor chip, can facilitate its manufacturing with a small size, and can improve its heat radiating performance. SOLUTION: A semiconductor chip electrically connected to a wiring formed on a carrier tape is arranged in a side-by-side relation with an interposer on the tape and in the vicinity of the chip. The tape is bent so as to wrap the chip arranged on the tape in its center, the chip and interposer are overlapped, and then covered with molding resin.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and uses a short wiring having a wiring pattern substantially symmetrical with respect to a semiconductor chip to improve electrical characteristics, to facilitate manufacture.
Also, the present invention relates to a semiconductor device which is small and can improve heat dissipation.

[0002]

2. Description of the Related Art In recent years, with the demand for higher performance and smaller size of electronic equipment, a semiconductor device having a high integration and a smaller size and a multi-pin semiconductor device have been required. Also, with the demand for higher performance and smaller size, a plurality of semiconductor chips are arranged in one package to form a multi-chip package (MCP).
Higher functionality and miniaturization of semiconductor devices have been achieved. For achieving the above miniaturization and increase in the number of pins, for example, a semiconductor device disclosed in JP-A-6-334098 has been proposed. As shown in FIGS. 11 and 12, the semiconductor device 110 has a package body 112 formed of a multilayer printed circuit board on the other surface corresponding to the joint portion of the heat sink 117 with a flexible wiring board 116 joined to the heat sink 117.
And the flexible wiring board 116 extending outside the package body 112 is folded back to form a package body 1
Twelve cavities 115 are joined to the open side. In the semiconductor device thus formed, as shown in FIG.
a is attached, and a lead pin as an external connection terminal 118 is joined to an outer surface of the flexible wiring board 116 joined to the package body 112 via a circuit board 116a such as a printed circuit board.

A multi-chip package in which a plurality of semiconductor chips are arranged in one package has a planar type M in which a plurality of semiconductor chips are arranged in a plane.
There are a CP and a stacked (stacked) MCP in which a plurality of semiconductor chips are stacked in the thickness direction. A planar MCP in which semiconductor chips are arranged in a plane requires a large mounting area, and therefore has a small contribution to miniaturization of electronic devices. For this reason, a stacked MCP in which semiconductor chips are stacked has been actively developed. An example of this is disclosed in Japanese Patent Laid-Open No. 6-2043.
No. 99 or JP-A-8-167630, a technique for forming a module by stacking semiconductor chips vertically after sealing them in a package and making electrical connection between the packages using via holes and through holes; and so on.

[0004]

However, in the semiconductor device disclosed in JP-A-6-334098, a printed circuit board having a predetermined wiring pattern formed on one side of a flexible wiring board 116 is laminated in multiple layers. Therefore, since the package body 112 having the cavity 115 formed therein is joined and manufactured, there are problems that the assembly is complicated and the size cannot be effectively reduced.

[0005] In the conventional laminated MCP, via holes and through holes for interlayer connection must be formed in order to electrically connect the semiconductor chip and the wiring board. Manufacturing processes such as processing, filling of conductors in holes, or plating are difficult. For this reason, without using a difficult manufacturing process such as via holes and through holes, a semiconductor chip is mounted on an insulating film tape provided with copper wiring, and a stacked semiconductor chip is electrically connected, for example, Japanese Patent Application Laid-Open No. 8-167630 has been proposed. In a semiconductor module comprising at least one semiconductor chip, a substrate for mounting them, and wiring electrically connected to the semiconductor chip formed on the substrate,
The substrate is folded to be multilayered, and the layers of the substrate are bonded by bonding means. In addition, a heat diffusion substrate is arranged between the folded layers to diffuse heat.
In addition, a rigidity securing substrate is disposed between the folded layers to increase the rigidity of the semiconductor module, prevent the solder balls from floating due to deformation such as warpage, and ensure electrical connection between the semiconductor module and the wiring board. It is described. However, in the case of the publication, the substrate is folded from the portion of the mountain fold line and the valley fold line to perform multilayering, and the semiconductor chip is disposed in the same space of the portion of the valley fold line, In addition, the active surfaces of the semiconductor chips are arranged to face each other in the space. For this reason, it is necessary to increase the size of the substrate at the mountain fold line because if the bending radius is reduced, the wiring may be cut or the like may occur, and the thickness of the semiconductor module is reduced because there are a plurality of the mountain fold lines. It gets thicker. Further, heat generated from the opposing semiconductor chips acts on each other, and further raises the temperature to cause an abnormal operation in the semiconductor chip, and further causes an abnormality in the semiconductor module based on the abnormal operation. In particular, when the active surface of the semiconductor chip is located at a position facing the semiconductor chip,
The heat acts on each other to cause abnormal operation. For this reason, in the same publication, a heat diffusion substrate is arranged between semiconductor chips to diffuse heat. However, since the heat diffusion substrate is arranged in contact with the active surface, the semiconductor is spread through the heat diffusion substrate. There is no change in the heat generated by the chips acting on each other,
Since the temperature does not decrease too much, the temperature may rise and cause abnormal operation of the semiconductor chip,
The problem of large size still remains.

The present invention focuses on the above-mentioned conventional problems, and arranges a semiconductor chip and an interposer on a carrier tape side by side, and uses a short wiring having a wiring pattern substantially symmetrical with respect to the semiconductor chip to improve electrical characteristics. Good and
It is an object of the present invention to provide a semiconductor device which is easy to manufacture, small in size, and capable of improving heat dissipation. For other purposes, the use area can be reduced by using a carrier tape on which electronic components are mounted, and as a result, the external dimensions of the entire package can be reduced and the mounting area can be reduced, improving workability and productivity. Thus, a semiconductor device whose manufacturing cost can be reduced is obtained.

[0007]

In order to achieve the above object, a semiconductor device according to the present invention comprises: a semiconductor chip electrically connected to wiring formed on a carrier tape; The semiconductor device is characterized in that an interposer is juxtaposed around a chip, a carrier tape is bent so as to include the semiconductor chip arranged in the center, the semiconductor chip and the interposer are overlapped, and covered with a mold resin.

According to the present invention having such a structure, the carrier tape material having substantially the same length in the left, right, and / or front and rear directions as shown with respect to the semiconductor chip disposed at the center is provided. The length can be shortened, and the electrical characteristics can be improved. In addition, it is only necessary to bend the short symmetrical carrier tape material in the same manner as the left and right sides, and the production can be facilitated.

In addition, a semiconductor device according to the present invention includes a plurality of parallel semiconductor chips electrically connected to wiring formed on a carrier tape, and a plurality of semiconductor chips arranged on the carrier tape and on both upper and lower sides of a semiconductor chip arranged at the center. The interposer and the interposer may be juxtaposed, and the carrier tape may be bent so that the interposer is superimposed on one surface of the central semiconductor chip and the semiconductor chip is superimposed on the other surface to form a multilayer, which is covered with a mold resin.

As described above, the present invention has a carrier tape material having substantially the same length in the vertical direction as shown in FIG. And the electrical characteristics can be improved. Further, since the carrier tape and the interposer can be arranged close to each other, the size can be reduced.

In the semiconductor device according to the present invention, it is preferable that an interposer made of a tape material is disposed on the carrier tape adjacent to the juxtaposed semiconductor chips, and external connection terminals are disposed on the interposer.

According to the present invention constructed as described above, an interposer made of a tape material is arranged on a carrier tape adjacent to the juxtaposed semiconductor chips, and external connection terminals are arranged on the interposer. The connection terminal portion is reinforced, and a single-layer wiring is sufficient and the cost is reduced.

In the semiconductor device according to the present invention, it is desirable that the active surfaces of the semiconductor chips are not opposed to each other and are stacked in a vertical direction to form a multilayer structure.

According to the present invention having such a configuration, the semiconductor chips can be stacked and multilayered and covered with mold resin while the active surfaces of the semiconductor chips are not opposed to each other. This prevents the semiconductor chip from being disposed on the opposing surface, and prevents the heat generated from the active surface from acting on each other to raise the heat, thereby reducing the rise in the temperature of the semiconductor chip. Therefore, abnormal operation does not occur in the semiconductor chip, and the semiconductor module operates normally.

Further, in the semiconductor device according to the present invention, it is desirable that a non-carrier tape is provided between the stacked semiconductor chips.

According to the present invention thus configured, the gap between the semiconductor chips can be reduced by the amount of the carrier tape omitted between the stacked semiconductor chips, so that the thickness of the semiconductor module can be reduced. Further, since no carrier tape having poor heat conductivity is not provided, the heat dissipation of the semiconductor chip is improved, the temperature does not rise so much, and the occurrence of abnormal operation can be prevented.

[0017]

Preferred embodiments of a semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a developed plan view of a semiconductor device 1 according to a first embodiment of the present invention, and FIG. 2 is a side sectional view of the semiconductor device 1.

In FIG. 1 or FIG. 2, the semiconductor device 1 of the first embodiment uses a rectangular carrier tape material 3 which is long in the horizontal direction as shown in the figure, and has a semiconductor chip 5 (shown by a dashed line) substantially in the center. ), And an interposer 2 which will be described in detail later on both sides of the semiconductor chip 5.
9a and 29b are arranged. In the semiconductor device 1, a semiconductor chip 5 is mounted on a carrier tape material 3 at a substantially central portion thereof while being electrically connected thereto. This semiconductor chip 5
It is formed in a rectangular shape, and has a plurality of electrodes 7 and 9 in parallel in the vicinity of opposing elongated sides thereof. The electrodes 7, 9 are, for example, first electrodes 7a, 7
, and the second electrodes 9a, 9b, 9 on the right side.
c,... are provided. A bump may be used for this electrode change.

A device hole 11 is formed in the carrier tape material 3 on the lower surface on which the semiconductor chip 5 is mounted so as to overlap with the position of the semiconductor chip 5. The dimensions of the device hole 11 are smaller than the outer shape of the semiconductor chip 5, and the semiconductor chip 5 and the device hole 11 are overlapped with a predetermined dimension La and are electrically connected. Thereby, the semiconductor device 1 can be reduced in size. The device hole 11 may be made larger than the semiconductor chip 5 and fixed with an adhesive (not shown).

The carrier tape material 3 is a flexible and insulating film tape made of a resin such as polyimide, polyester, or a glass epoxy material, and is bendable. On this carrier tape material 3, a copper wiring 13 is formed on one end surface side, and a land 17 on which a solder ball 15 to be described later is formed is formed on the other end surface side. The copper wiring 13 on one end side and the solder balls 15 on the other end side are electrically connected by through holes 19 provided in the carrier tape material 3. For this reason, the through hole 19 may be formed by plating the inner surface of the through hole, filling a conductive material disposed in the hole, or forming a conductive metal material disposed in the hole. Are electrically connected by a method of connecting wires, rods, or the like.

The copper wiring 13 is formed by edging the copper foil on an insulating flexible film to form a predetermined wiring pattern, and one end of the copper wiring 13 is connected to the corresponding electrodes 7 and 9 of the semiconductor chip 5. Inner lead 23,
Reference numeral 25 is provided so as to protrude inward beyond the peripheral end of the elongated left and right sides of the device hole 11.
The inner leads 23, 25 are provided with inner leads 23a, 23b, 23c,... On the left side in the figure, and the inner leads 25a, 25b, 25c,. The copper wiring 13 may be formed by forming a conductive film on the surface of the flexible film by vapor deposition or sputtering, and etching the conductive film to form a predetermined wiring pattern. Except for the lands 17 to which the electrodes 7 and 9 and the solder balls 15 are bonded, the copper wiring 13 may be coated with a protective resin such as polyimide to form a protective film.

The carrier tape member 3 has, for example, a first carrier tape member 3a on the left side in the drawing and a second carrier tape member 3 on the right side in the drawing with the semiconductor chip 5 disposed substantially at the center therebetween. 3b is provided. The first carrier tape member 3a has a first bent portion 27a,
The second bent portion 27b is provided on the second carrier tape material 3b. This copper wiring 13 is, for example, TAB
The electrodes 7 and 9 of the semiconductor chip 5 and the solder balls 15 are electrically connected by a (Tape Automated Bonding) technique. The copper wiring 13 is bonded to the electrodes 7 and 9 of the semiconductor chip 5 and the solder balls 1 by wire bonding, for example, by bonding with an adhesive such as epoxy silver paste.
5 may be electrically connected.

A first interposer 29a is provided on the first carrier tape member 3a on the left side in the drawing, and a second interposer 29 is provided on the second carrier tape member 3b on the right side in the drawing.
b is fixed by an adhesive (not shown).

The semiconductor device 1 developed as described above has:
It is manufactured in the following process sequence. First, as described above, the semiconductor chip 5 is placed at a position where the semiconductor chip 5 overlaps the device hole 11 formed in the carrier tape material 3. Also,
The electrodes 7, 9 of the semiconductor chip 5 and the copper wiring of the carrier tape material 3 are electrically connected by TAB technology or wire bonding technology. A first interposer 29a and a second interposer 29b are fixed to both ends of the carrier tape material 3 by an adhesive (not shown). next,
The first bent portion 27a of the first carrier tape material 3a and the second bent portion 27b of the second carrier tape material 3b provided on both of the semiconductor chips 5 divide the semiconductor chip 5 between the two carrier tape materials 3a and 3b. It is bent at an almost right angle so as to be stored between the insides. Further, similarly to the above, the first bent portion 2 of the first carrier tape material 3a is formed.
7a and the second bent portion 27b of the second carrier tape material 3b are bent at a substantially right angle so that the illustrated lower surface of the semiconductor chip 5 and the first interposer 29a and the second interposer 29b overlap. In this state, the outside of the semiconductor chip 5 and the carrier tape material 3 is molded with a predetermined thickness, and the gap between the semiconductor chip 5 and the inside of the carrier tape is molded with the resin sealing material 31. For this resin sealing, a transfer molding method using a mold or a potting method using a potting resin can be used. Thereafter, the solder balls 15 are bonded to the lands 17 and are electrically connected. Also,
The solder ball 15 may be formed by bonding a solder to a copper ball to form a spherical external bonding terminal.

As described above, by making the size of the device hole 11 smaller than the outer shape of the semiconductor chip 5, the carrier tape material 3 provided between the periphery of the device hole 11 and the periphery of the semiconductor chip 5 is formed. The copper wiring 13 can be provided in the overlapping area, and the use of the carrier tape material 3 for one semiconductor device 1 can be reduced. Further, the dimensions of the semiconductor device 1 manufactured from the carrier tape material 3 can be significantly reduced, and the mounting area can be reduced. Further, since the first carrier tape material 3a and the second carrier tape material 3b having substantially the same length in the horizontal direction as shown in the drawing with respect to the semiconductor chip 5, the length of the wiring pattern can be shortened. The electrical characteristics of the device 1 can be improved. In addition, it is only necessary to bend the short symmetrical carrier tape material in the same manner as the left and right sides, and the production can be facilitated.

FIG. 3 is an exploded plan view of a semiconductor device 1A according to a second embodiment of the present invention, FIG. 4 is a side sectional view of the semiconductor device 1A, and FIG. 5 is a plan view of the semiconductor device 1A after assembly.

In the semiconductor device 1A of the second embodiment, a substantially square carrier tape material 43 is used, and a substantially square semiconductor chip 45 is provided at a substantially central portion thereof.
And the semiconductor chip 45
Triangular interposer 4 protruding from each of the four sides
9 is arranged to be freely bent.

In FIGS. 3 and 4, a semiconductor chip 45 is electrically connected to and mounted on substantially the center of the carrier tape material 43. The semiconductor chip 45 is formed in a substantially square shape, and has a plurality of electrodes 51, 53, 55, and 57 near each side thereof in parallel. The electrodes 51, 53, 55, and 57 include, for example, first electrodes 51a, 51b, 51c,.
The electrodes 53a, 53b, 53c,...
5a, 55b, 55c,... And the fourth electrodes 57a, 57b, 57c,.

As in the first embodiment, the semiconductor chip 45
A device hole 11 is formed in the carrier tape material 43 on the lower surface on which is mounted so as to overlap the position of the semiconductor chip 45. As shown in FIG. 4, the size of the device hole 11 is smaller than the outer shape of the semiconductor chip 45, and the semiconductor chip 45 and the device hole 11 are overlapped with a predetermined size La, and are electrically connected. It is connected. Thereby, similarly to the first embodiment,
The external shape can be made smaller.

As in the first embodiment, the carrier tape material 43 has a copper wiring 13 on one end surface and a solder ball 15 to be described later on the other end surface.
Are formed, and the material, configuration, and the like are the same, and therefore detailed description is omitted.

The copper wiring 13 has a predetermined wiring pattern formed by edging copper wire on an insulating flexible film, and one end of the copper wiring 13 has a plurality of electrodes 51, 53, 55, In order to connect to the terminal 57, the inner leads 61, 63, 65, 67 are provided so as to protrude inward beyond the peripheral edge of the device hole 11 formed in a square shape. The inner leads 61, 63, 65, and 67 have first inner leads 61a, 61b, 61c,... On the left side in the drawing, second inner leads 63a, 63b, 63c on the right side in the drawing, and a third inner lead on the upper side. The leads 65a, 65b, 65c,.
And the fourth inner leads 67a, 67b, 67 on the lower side.
c,... are provided. The copper wiring 13 is formed by the first
As in the embodiment, it is also possible to form a conductor film on the surface of the flexible film.

As shown in FIG. 3, for example, the carrier tape material 43 is connected in a triangular shape so as to surround each side of a quadrangular semiconductor chip 45 disposed substantially at the center. That is, the first carrier tape material 43a is shown on the left side of the semiconductor chip 45, the second carrier tape material 43b is shown on the right side, the third carrier tape material 43c is shown on the upper side, and the fourth carrier tape material 43d is shown on the lower side. It is arranged.

The first carrier tape member 43a has a first bent portion 69a, and the second carrier tape member 43b has a second bent portion 69a.
The bent portion 69b is provided with a first bent portion 69c on the third carrier tape material 43c, and the fourth bent portion 69d is provided on the fourth carrier tape material 43d.
The copper wiring 13 is formed, for example, by TAB (Ta
pe Automated Bonding) or manufactured by wire bonding technology. In addition, each carrier tape material 43
The first interposer 49a,
The second interposer 49b, the third interposer 49c, and the fourth interposer 49d are fixed with an adhesive (not shown).

The semiconductor device 1A developed as described above
Are manufactured in the following process sequence. First, as described above, the semiconductor chip 45 is placed at a position where it overlaps with the device hole 11 formed in the carrier tape material 43. Further, a plurality of electrodes 51, 53, 55, 57 and a carrier tape material 43 are arranged in parallel near each side of the semiconductor chip 45.
Are electrically connected by TAB technology or wire bonding technology. Each interposer 49 is fixed to an end of each triangular shape of the carrier tape member 43 by an adhesive (not shown). Next, the first bent portion 69a of the first carrier tape material 43a, the second bent portion 69b of the second carrier tape material 43b, and the first bent portion of the third carrier tape material 43c provided on each side of the semiconductor chip 5 69c and the fourth bent portion 69d of the fourth carrier tape material 43d are bent almost at a right angle so as to house the semiconductor chip 45 between the insides of the carrier tape materials 43a, 43b, 43c and 43d. further,
Similarly to the above, the illustrated lower surface of the semiconductor chip 45 and the first
The interposer 49a, the second interposer 49b, the third interposer 49c, and the fourth interposer 49d are bent at substantially right angles so as to overlap with each other. Thereby, as shown in FIG. 5, the first carrier tape member 43a and the second carrier tape member 43b each having a triangular shape connected to each side.
The third carrier tape member 43c and the fourth carrier tape member 43d form a flat surface, and the semiconductor chip 45
For each carrier tape material 43a, 43b, 43c, 43d
To be stored between the insides. In this state, the semiconductor chip 45
Then, the outside of the carrier tape material 43 is molded with a predetermined thickness, and the gap between the semiconductor chip 45 and the inside of the carrier tape is molded with the resin sealing material 31. For this resin sealing, a transfer molding method using a mold or a potting method using a potting resin can be used. Thereafter, the solder balls 15 are bonded to the lands 17 and are electrically connected. Further, the solder ball 15 may be formed by bonding a solder to a copper ball to form a spherical external bonding terminal.

As described above, similarly to the first embodiment, the size of the device hole 11 is made smaller than the outer shape of the semiconductor chip 45, so that the device hole 11 is provided between the periphery of the device hole 11 and the periphery of the semiconductor chip 45. The copper wiring 13 can be provided in the overlapping region of the carrier tape material 43 to be used, and the use of the carrier tape material 43 for one semiconductor device 1A can be reduced. Further, the size of the semiconductor device 1A manufactured from the carrier tape material 43 can be significantly reduced, and the mounting area can be reduced. Further, a first carrier tape material 43a, a second carrier tape material 43b, a third carrier tape material 43c, and a fourth carrier tape material 43d having substantially the same length in the left, right, up and down directions as shown in the figure with respect to the semiconductor chip 45 are provided. As a result, the length of the wiring pattern can be reduced, and the electrical characteristics of the semiconductor device 1 can be improved. In addition, it is only necessary to bend the short side of the carrier tape material left and right or / and vertically symmetrically in the same manner as the left and right sides, and the production can be facilitated.

FIG. 6 is an exploded plan view of a semiconductor device 1B according to a third embodiment of the present invention, FIG. 7 is a side sectional view of the semiconductor device 1B, taken along the line YY of FIG. 1, and FIG. FIG. 2 is a sectional view taken along the line ZZ of FIG. 1.

In the third embodiment, a semiconductor device 1B as an example of a tape folding type stack will be described.

6 to 8, the semiconductor device 1B
A plurality (five in the present embodiment) of semiconductor chips 75 are mounted on the carrier tape material 73 in the illustrated horizontal direction, and an interposer 77 is mounted in the illustrated vertical direction. ing. In the case of the present embodiment, the semiconductor chips 75 are sequentially arranged on the first semiconductor chip 7 from the right side in the drawing.
5a, second semiconductor chip 75b, third semiconductor chip 75
c, the fourth semiconductor chip 75d, and the fifth semiconductor chip 5e. The interposer 77 has an upper interposer 77a above the third semiconductor chip 75c and a lower interposer 77b below the third semiconductor chip 75c.

The third semiconductor chip 75c disposed substantially at the center of the carrier tape member 73 is formed in a substantially rectangular shape, and a plurality of electrodes 8 are arranged in parallel near each side thereof.
1, 83, 85 and 87. These electrodes 81, 8
3, 85 and 87 are, for example, first electrodes 81 on the left side of the drawing.
, 81b, 81c,...
3b, 83c,..., The third electrodes 85a, 85b,.
, 85c,... And the fourth electrodes 87a, 87 on the lower side.
, 87c,... are provided. A plurality of electrodes 89 are arranged in a line at the center of the first semiconductor chip 75a, the second semiconductor chip 75b, the fourth semiconductor chip 75d, and the fifth semiconductor chip 5e.
Reference numeral 9 denotes a pump which is electrically connected to each copper wiring 13.

As in the first embodiment, a plurality (five in the case of the present embodiment) of device holes 11 are formed in the lower surface of the carrier tape material 73 on which the semiconductor chips 75 are mounted. ing. In the case of the present embodiment, the device holes 11 are sequentially formed from a first device hole 11a, a second device hole 11b,
The device hole 11c, the fourth device hole 11d, and the fifth device hole 11e. The device hole 11 is formed to be smaller than the outer dimensions of the semiconductor chip 75.
And the device hole 11 are overlapped with a predetermined dimension La,
It is electrically connected. Thereby, the semiconductor device 1 can be reduced in size. The device hole 11 may be made larger than the semiconductor chip 5 and fixed with an adhesive (not shown).

Here, when the outer dimensions of the first semiconductor chip 75a and the second semiconductor chip 75b are the same, device holes of the same size are formed in the first device hole 11a and the second device hole 11b. . Also, the first
If the outer dimensions of the semiconductor chip 75a and the second semiconductor chip 75b are different, the first device hole 11a and the second
Device holes having dimensions different from those of the device holes 11b are formed. The device hole 11 has the same configuration, although the description is omitted below. In the present embodiment, as described above, the semiconductor chip is formed by five semiconductor chips, but the number is not limited thereto, and may be two, three, or four or more.

As in the first embodiment, a copper wiring 13 is formed on one end surface of the carrier tape material 73, as in the first embodiment. A third electrode 85a disposed above the third semiconductor chip 75c;
, 85b, 85c,...
a, 87b, 87c,...
A land 17 on which a solder ball 15 described later is formed is formed on the other end surface side. Also, the carrier tape material 73
Since other materials, configurations and the like are the same, detailed description is omitted.

The copper wiring 13 has a predetermined wiring pattern formed by edging the copper foil on an insulating flexible film, and one end of the copper wiring 13 is connected to the third semiconductor chip 7.
In order to connect to the corresponding plurality of electrodes 81, 83, 85, and 87 of 5c, the inner leads 91, 93, 95, and 97 extend inward beyond the peripheral edge of the third device hole 11c formed in a rectangular shape. It is provided so as to protrude. The inner lead has a first inner lead 91 on the left side of the drawing, a second inner lead 93 on the right side of the drawing,
The third inner lead 95 is provided on the upper side, and the fourth inner lead 97 is provided on the lower side. This copper wiring 13
Similarly to the first embodiment, it is also possible to form a conductive film on the surface of the flexible film.

As shown in FIG. 6, for example, the carrier tape member 73 is composed of a rectangular semiconductor chip 75 disposed substantially horizontally at the center and a third semiconductor chip 75 disposed substantially at the center. The lower interposer 77b is connected to the upper interposer 77a and the lower interposer 77b disposed below and above the illustrated 75c, and has a cross shape. That is, the first carrier tape member 73a is located on the right side of the third semiconductor chip 75c and the second carrier tape member 73 is located on the left side.
b is a third carrier tape material 73c on the upper side, and
The fourth carrier tape member 73d is provided on the lower side.

The first carrier tape member 73a has a first bent portion 99a, and the second carrier tape member 73b has a second bent portion 99a.
The bent portion 99b is provided with a third bent portion 99c in the third carrier tape material 73c, and the fourth bent portion 99d is provided in the fourth carrier tape material 73d.
The copper wiring 13 is formed, for example, by TAB (Ta
pe Automated Bonding) or manufactured by wire bonding technology. Next, a portion of the perforation 101 of the carrier tape material 3 is cut along a cut line 103.

The semiconductor device 1B developed as described above
Are manufactured in the following process sequence. First, as described above, each semiconductor chip 75 is mounted at a position where it overlaps with each device hole 11 formed in the carrier tape material 73. Further, the plurality of electrodes 81, 83, 85, 87 and the copper wiring 13 of the carrier tape material 73 are electrically connected in parallel near each side of each semiconductor chip 75 by TAB technology or wire bonding technology. Third semiconductor chip 7
The first semiconductor chip 75a, the second semiconductor chip 75b, the fourth semiconductor chip 75d, the fifth semiconductor chip 5e, and the upper interposer 77a are provided at the respective cross-shaped ends of the carrier tape material 73 around the center 5c. The lower interposer 77b is fixed with an adhesive (not shown). At this time, the first semiconductor chip 75a and the second semiconductor chip 75
b, each electrode 89 at the center of the fourth semiconductor chip 75d and the fifth semiconductor chip 5e is electrically connected to each copper wiring 13 by pumping.

Next, the first carrier tape material 73a provided on each of the left and right sides of the third semiconductor chip 75c has the first
The bent portion 99a and the second bent portion 99b of the second carrier tape member 73b are rotated upward (arrow Wa) in the drawing, and the first semiconductor chip 75a and the second semiconductor chip 75b are moved relative to the third semiconductor chip 75c. , The fourth semiconductor chip 75d, and the fifth semiconductor chip 5e are superposed in a line.

Next, the third carrier tape material 73c
Folded portion 99c and fourth carrier tape material 43
d is bent downward (arrow Va) in the figure.
, The upper interposer 77a and the lower interposer 77b are superimposed on the third semiconductor chip 45c in a line. That is, thereby, the third semiconductor chip 75c is placed above the first semiconductor chip 75c in the drawing.
a, second semiconductor chip 75b, fourth semiconductor chip 75
d and the fifth semiconductor chip 5e are configured such that the upper interposer 77a and the lower interposer 77b overlap on the lower side in the figure and are housed inside. At this time, mountain folding is performed only once, and a plurality of small semiconductor chips are superimposed on a large semiconductor chip. In this state, the outside of the semiconductor chip 75 and the carrier tape material 73 is formed with a predetermined thickness, and
And the gap between the carrier tape material 73 and the resin sealing material 31
Mold. For this resin sealing, a transfer molding method using a mold or a potting method using a potting resin can be used. Thereafter, the solder balls 15 are bonded to the lands 17 and are electrically connected. Further, the solder ball 15 may be formed by bonding a solder to a copper ball to form a spherical external bonding terminal.

In the above description, for example, the active surfaces (Ac) of the first semiconductor chip 75a, the second semiconductor chip 75b, the fourth semiconductor chip 75d, and the fifth semiconductor chip 5e are placed horizontally with the upper side in the drawing. Next, the third semiconductor chip 75c is placed horizontally with the active surface of the third semiconductor chip 75c facing down, and the third semiconductor chip 75c and the other first semiconductor chips 75a,
The second semiconductor chip 75b, the fourth semiconductor chip 75d, and the fifth semiconductor chip 5e may be arranged so as to be separated from each other so that the active surfaces do not face each other. As a result, the semiconductor devices 1B in the case of the tape bending type stack are stacked without facing the active surfaces, so that the temperatures of the semiconductor chips 5 do not interact with each other and operate normally, and abnormal operation occurs. Can be prevented. In addition, since the carrier tape material 3 is laminated without being sandwiched between the semiconductor chips 5, the carrier tape material 3 having low thermal conductivity is reduced while the size is reduced.
Therefore, the heat dissipation from the semiconductor chip 5 is improved, and the semiconductor device 1B operates normally and can prevent occurrence of abnormal operation.

The semiconductor device 1B developed as described above
The carrier tape material provided between the periphery of the device hole 11 and the periphery of the semiconductor chip 75 by making the size of the device hole 11 smaller than the outer shape of the semiconductor chip 45 as in the first embodiment. The copper wiring 13 can be provided in the overlapping region of 73, and the use of the carrier tape material 73 for one semiconductor device 1B can be reduced. Further, the dimensions of the semiconductor device 1B manufactured from the carrier tape material 73 can be significantly reduced, and the mounting area can be reduced. Further, the first carrier tape member 73a, the second carrier tape member 73b, the fourth carrier tape member 73d, and the fifth carrier tape member 7 having substantially the same length in the left, right, up and down directions as shown in FIG.
3e, the length of the wiring pattern can be reduced, and the electrical characteristics of the semiconductor device 1B can be improved. In addition, it is only necessary to bend the short side of the carrier tape material left and right or / and vertically symmetrically in the same manner as the left and right sides, and the production can be facilitated.

FIG. 9 is a side sectional view of a semiconductor device 1C according to a fourth embodiment of the present invention, and FIG. 10 is a front sectional view of the semiconductor device. The semiconductor device 1C according to the fourth embodiment includes a third device.
This is a modification of the embodiment, and is a carrier tape material 73 connecting between the semiconductor chips 75 and connecting the interposer 77.
Position is different.

In the third embodiment, in FIG. 1, a carrier tape material 73 is arranged with the copper wiring 13 facing upward, and the first semiconductor chip 75a and the second semiconductor chip 75 are placed thereon.
b, third semiconductor chip 75c, fourth semiconductor chip 75
d, the fifth semiconductor chip 5e, and further, the upper interposer 77a and the lower interposer 77b are mounted. The developed semiconductor device 1B is provided with a third semiconductor chip 75.
The first semiconductor chip 75a, the second semiconductor chip 75b, the fourth semiconductor chip 75d, and the fifth
The semiconductor chip 5e is rotating upward (arrow Wa) in the figure. The upper interposer 77a and the lower interposer 77b rotate around the third semiconductor chip 75c downward (arrow Va) in the figure.

On the other hand, in the semiconductor device 1C of the fourth embodiment, in FIG. 1, the carrier tape member 73 is disposed with the copper wiring 13 as the lower surface, and the first semiconductor chip 75a, the second semiconductor chip 75b, third semiconductor chip 7
5c, the fourth semiconductor chip 75d, and the fifth semiconductor chip 5e, and further, the upper interposer 77a and the lower interposer 77b are mounted. This developed semiconductor device 1
C is rotated in the same manner as in the third embodiment. This allows
In the semiconductor device 1C, the upper interposer 77a and the lower interposer 77b can be arranged while being in contact with the lower surface of the third semiconductor chip 75c. The first semiconductor chip 75a, the second semiconductor chip 75b, and the third semiconductor chip 7
5c, the fourth semiconductor chip 75d, and the fifth semiconductor chip 5e can be arranged at predetermined intervals.
For this reason, in the semiconductor device 1C of the fourth embodiment, since the interposer 77 and the third semiconductor chip 75c are disposed in contact with each other, the semiconductor device 1C can be smaller than the semiconductor device 1C of the third embodiment. In addition, the active surfaces of the semiconductor chip 75 can be disposed so as not to face each other, and a rise in temperature can be prevented.

[0055]

As described above, according to the present invention, the semiconductor chip electrically connected to the wiring formed on the carrier tape and the interposer are juxtaposed on the carrier tape and around the semiconductor chip. At the same time, the carrier tape is bent so as to include the semiconductor chip placed in the center, and the semiconductor chip and the interposer are overlapped,
It is configured to be covered with mold resin. As a result, a carrier tape material having substantially the same length in the left-right direction and / or the front-rear direction as shown with respect to the center semiconductor chip can be formed, so that the length of the wiring pattern can be shortened and the electrical characteristics can be improved. Can be done. In addition, it is only necessary to bend the short symmetrical carrier tape material in the same manner as the left and right sides, and the production can be facilitated.

Further, according to the present invention, an interposer is juxtaposed on a carrier tape and on both upper and lower sides of a semiconductor chip arranged in the center, and the interposer is arranged on one surface of the center semiconductor chip by bending the carrier tape and on the other surface. When the semiconductor chip is stacked and formed into a multilayer structure, the length of the wiring pattern can be reduced because the carrier tape material having substantially the same length in the vertical direction is provided as described above.
The electrical characteristics can be improved, and the carrier tape and the interposer can be arranged close to each other, so that the size can be reduced.

When an interposer made of a tape material is disposed on a carrier tape adjacent to the juxtaposed semiconductor chips and an external connection terminal is disposed on the interposer, the external connection terminal is disposed on the interposer. The external connection terminal portion is reinforced by the interposer, and a single-layer wiring improves the cost and reduces the cost.

When the semiconductor chips are stacked so that the active surfaces of the semiconductor chips are not opposed to each other and are vertically overlapped, heat generated from the active surfaces does not act on each other to increase the heat. The temperature of the chip is less likely to rise. For this reason, abnormal operation does not occur in the semiconductor chip, and the semiconductor module can operate normally.

If a non-carrier tape is used between the stacked semiconductor chips, the gap between the semiconductor chips can be reduced by the amount of the carrier tape omitted between the stacked semiconductor chips, so that the thickness of the semiconductor module can be reduced. Can be made smaller. Since no carrier tape is provided, the heat dissipation of the semiconductor chip is improved, the temperature does not rise too much, and the occurrence of abnormal operation can be prevented.

[Brief description of the drawings]

FIG. 1 is a developed plan view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a side sectional view of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a developed plan view of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a side sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a plan view after assembling a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a developed plan view of a semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a side sectional view of a semiconductor device according to a third embodiment of the present invention, which is a sectional view taken along line YY of FIG. 1;

FIG. 8 is a front sectional view of a semiconductor device according to a third embodiment of the present invention, which is a sectional view taken along line ZZ of FIG. 1;

FIG. 9 is a side sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 10 is a front sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 11 is a diagram illustrating a method of manufacturing a semiconductor device using a conventional flexible wiring board.

FIG. 12 is a diagram showing a configuration of a semiconductor device using a conventional flexible wiring board.

[Explanation of symbols]

1, 1A, 1B, 1C Semiconductor device 3, 43, 73 Carrier tape material 5, 45, 75 Semiconductor chip 7, 9, 51, 53, 55, 57, 81, 83, 85,
87, 89 Electrode 11 Device hole 13 Copper wiring 15 Solder ball 19 Through hole 27, 69, 99 Bent part 29, 49, 77 Interposer

Claims (5)

[Claims] 1. A semiconductor chip electrically connected to wiring formed on a carrier tape, and an interposer arranged side by side on the carrier tape and around the semiconductor chip, and including a semiconductor chip arranged at the center. A semiconductor device characterized in that the carrier tape is bent in such a manner that the semiconductor chip and the interposer are overlapped and covered with a mold resin. 2. A semiconductor device comprising: a plurality of parallel semiconductor chips electrically connected to wiring formed on a carrier tape; and an interposer arranged on the carrier tape on both upper and lower sides of a centrally located semiconductor chip. A semiconductor device, wherein a tape is bent to form a multilayer by superposing a semiconductor chip on one surface of a central semiconductor chip and a semiconductor chip on the other surface, and covering with a mold resin. 3. An interposer of tape material is arranged on a carrier tape adjacent to the juxtaposed semiconductor chips, and
3. The semiconductor device according to claim 1, wherein an external connection terminal is provided on the interposer. 4. The semiconductor device according to claim 2, wherein the semiconductor chips are stacked so that the active surfaces of the semiconductor chips are not opposed to each other and are vertically stacked. 5. The semiconductor device according to claim 2, wherein a non-carrier tape is provided between the stacked semiconductor chips.