JP2001156250A - Semiconductor chip, multi-chip package and semiconductor device as well as electronic equipment using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip module, a multi-chip package and a semiconductor device as well as an electronic equipment using it capable of easily three-dimensionally mounting semiconductor chips, minimizing deterioration of electric characteristics and being easily manufactured with a small profile size. SOLUTION: The electrode positions of the semiconductor chips are etched to form a groove of a V shape or a pyramidal shape. The groove is cut and divided, electrodes are formed on the oblique parts of the groove of the divided chips and the end faces of the chips are substantially linearly aligned.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip, a multi-chip package, a semiconductor device, and an electronic device using the same.

[0002]

2. Description of the Related Art In recent years, with the increase in performance and miniaturization of electronic equipment, a plurality of semiconductor chips are arranged in one package to form a multi-chip package (Multi Chip Package), thereby achieving high performance of a semiconductor device. And miniaturization are achieved. The multi-chip package includes a package in which a plurality of semiconductor chips are arranged in a plane and a package in which a plurality of semiconductor chips are stacked in a thickness direction. A multi-chip package in which semiconductor chips are arranged in a plane requires a large mounting area, so that the contribution to miniaturization of electronic devices is small. Therefore, a stacked M in which semiconductor chips are stacked
CP is being actively developed.

As this type of package structure, as disclosed in Japanese Utility Model Laid-Open Publication No. Sho 62-158840 and Japanese Patent Laid-Open Publication No. Hei 6-37250, a plurality of semiconductor chips are formed in a pyramid shape according to the size of the external dimensions. Generally, terminal electrodes provided on the upper surface of each semiconductor chip are stacked and connected by wire bonding.

[0004]

However, the conventional multi-chip package has a drawback that the order of stacking is restricted by the chip size, and the degree of freedom in stacking is low. In addition, wire bonding is used to connect terminal electrodes between chips. However, since the distance between terminals is not constant, the wire length is various, and the electrical characteristics are deteriorated due to the bonding length. There is a problem. Further, the lower chip of the chips to be stacked must always have the terminal electrode formation region exposed more than the upper chip, and there is a requirement to limit the chip size.
Further, when a lower chip and an upper chip of the same size are used, there is a disadvantage that a space for wire bonding is required between the lower semiconductor chip and the upper semiconductor chip, and the outer dimensions are increased. For this reason, there is a demand for the development of a multi-chip package in which even a lower chip and an upper chip of the same size have small external dimensions and are easy to manufacture electrodes.

The present invention focuses on the above-mentioned conventional problems, and makes it easy to three-dimensionally mount a semiconductor chip, minimize the deterioration of electrical characteristics, and has a small external dimension and is easy to manufacture. It is an object to provide a semiconductor chip module, a multi-chip package, and a semiconductor device, and an electronic device using the same. Also,
The second object is to enable three-dimensional mounting without being affected by the chip size.

[0006]

In order to achieve the above-mentioned object, a semiconductor chip according to the present invention is formed by etching a predetermined electrode portion of a semiconductor chip on a wafer to form either a V-shaped or a pyramid-shaped electrode. And the grooves are cut and divided, and electrodes are formed on the inclined portions of the grooves of the divided semiconductor chips.

According to the present invention having the above-described structure, since the cutting is performed at the groove having the bottom, the division is facilitated. Further, since the electrodes are formed on the divided inclined portions, even if semiconductor chips of the same size are used, the vertical space required for wire bonding becomes unnecessary. Further, since the length of the wire bonding can be made substantially the same, the manufacture becomes easy.

In the semiconductor chip according to the present invention, a V-shaped or pyramid-shaped groove is formed by etching a predetermined electrode portion of the semiconductor chip on the wafer, and the same portion as the electrode portion is formed. Etching is performed on the back surface of the silicon wafer to form a V-shaped groove, and cut and divided at the position of the V-shaped or pyramid-shaped groove and the V-shaped groove on the back surface, and the divided semiconductor is formed. A configuration in which an electrode is formed on the inclined portion of the chip may be used.

According to the present invention having such a configuration, the inclined portion is provided on the back surface of the semiconductor chip, so that interference during wire bonding is eliminated.

[0010] The multi-chip package according to the present invention comprises:
A semiconductor chip having electrodes formed on an upper inclined portion is stacked, and electrodes of each semiconductor chip are connected by a conductive portion.

According to the present invention having the above-described structure, similarly to the above, the multi-chip package can eliminate the vertical space required for wire bonding. Further, the length of the wire bonding can be made substantially the same, and the electrodes can be connected in the same row.

[0012] The multi-chip package according to the present invention comprises:
It is preferable that either the upper inclined portion on which the electrode is formed is inclined while being laminated in the same direction, or the upper inclined portion on which the electrode is formed is opposed and laminated.

According to the present invention having such a configuration, since the layers are stacked while being inclined in the same direction, the connection by wire bonding is facilitated. In addition, since the inclined portions are stacked so as to face each other, the number of connection terminals of the partner with respect to the electrodes can be reduced.

Further, in the multi-chip package according to the present invention, the end face on the electrode side of the multi-chip package in which the upper inclined portions on which the electrodes are formed are inclined in the same direction is substantially linearly formed at right angles or the electrodes are formed. It is preferable that the above-mentioned upper inclined portion is arranged on any one of the substantially linear inclined surfaces.

According to the present invention thus configured, various sizes of semiconductor chips to be stacked can be used.

In the semiconductor device according to the present invention, the conductive portion for connecting the electrodes may be any one of a wire bonding, a solder ball and a wire bonding or a lead rod, or a combination of a solder applied by ink jet and a wire bonding or a lead rod. Each electrode is connected to an electrode of a logic chip.

According to the present invention configured as described above, the electrodes of the semiconductor to be stacked and the electrodes of the logic chip can be connected with a simple configuration and the same configuration, and the conductivity can be easily made. it can.

In the semiconductor device according to the present invention, a plurality of semiconductor chips of the same or different sizes are stacked with their adjacent two sides aligned and terminals common to each semiconductor chip are concentrated on the aligned edge side. Then, it is preferable that electrodes are arranged and connected to terminals between the stacked chips arranged in a concentrated manner.

According to the present invention thus configured, various sizes of semiconductor chips to be stacked can be used as described above. Also, even if semiconductor chips of various sizes are used, the electrodes can be connected in the same row by conductors having the same length or the same shape.

An electronic apparatus according to the present invention is characterized in that a semiconductor device is connected to a motherboard to form a circuit.

According to the present invention configured as described above, since the multi-chip package or the semiconductor device configured as described above is provided, the manufacturing is facilitated and the external shape is reduced. .

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of an electrode structure of a multi-chip package according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a perspective view of a multi-chip package 10 according to a first embodiment of the present invention or a process diagram showing a partial cross-sectional side shape.

FIG. 1A is a perspective view of a silicon wafer 51 constituting a semiconductor chip 14 of a multi-chip package 10 to be described later using the present invention. An etching protection film 57 is applied to the upper surface (active surface side) of the silicon wafer 51 except for an electrode forming portion 55 in which the electrode 53 of the chip 14 shown in FIG. 1C is formed. The electrode forming section 55 is formed in an inverted pyramid shape by etching described later. FIG. 1B is a view showing a state in which FIG. 1 is cut and divided. The electrode forming section 55 of the silicon wafer 51 is cut and divided to form an upper inclined portion 61 for forming an electrode 53. Further, a chip electrode pad 54 to which the other end of the electrode 53 is connected is formed. FIG. 1 (c)
Is a perspective view of the semiconductor chip 14, and shows an upper inclined portion 61.
An electrode 53 is formed between the semiconductor chip and the chip electrode pad 54.

FIG. 2A is a perspective view of a silicon wafer 51 showing another embodiment for manufacturing the semiconductor chip 14. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 1, the electrode forming section 55 is formed in an inverted pyramid shape, but in FIG.
A character-shaped groove 55A is formed in a vertical and horizontal cross shape. FIG. 2B is a diagram showing a state in which FIG. 2 is cut and divided. The electrode forming section 55 of the silicon wafer 51 is cut and divided to form an upper inclined portion 61A for forming the electrode 53. FIG. 2C is a perspective view of the semiconductor chip 14, and an electrode 53 is formed between the upper inclined portion 61 </ b> A and the chip electrode pad 54. In the above description, it is easier to divide the silicon wafer 51 by forming the lower groove 71 of the silicon wafer 51, but there is no problem in manufacturing even if it is not necessarily provided.

Next, the production of the semiconductor chip 14A shown in FIG. 2 will be specifically described with reference to the production steps shown in FIG.

FIG. 3A is a side view of a silicon wafer 51 constituting a semiconductor chip 14 of a multi-chip package 10 described later using the present invention. On the upper surface of the silicon wafer 51, except for the electrode forming portion 55 where the electrodes 53 of the semiconductor chip 14 are formed, the etching protection film 57 is formed.
To form At this time, an etching protection film 57a is also formed and placed on the back surface of the silicon wafer 51 at the same time. That is, the silicon wafer 51 having the (100) azimuthal plane on which various elements such as transistors, resistance elements, wirings, and electrode pads are formed, is subjected to the etching protection films 57 and 57a made of a silicon oxide film by the CVD method or the like. It is formed, but is etched through the opening (electrode forming portion 55) of the etching protection film 57 on the active surface side.
In this state, anisotropic wet etching is performed to etch the silicon single crystal substrate exposed from the opening of the etching protection film 57. In this anisotropic wet etching, the silicon single crystal substrate has an inclination angle of 5 °.
Since the etching stops at the azimuth plane (111) at 4.7 degrees, an inverted pyramid-shaped concave section having a V-shaped cross section is formed. Since the depth of the concave portion depends on the width of the opening of the etching protection film 57, it may be arbitrarily adjusted according to the thickness of the silicon wafer 51.

In FIG. 3C, the silicon wafer 51 is
The semiconductor chip 14 is cut at the position of the V-shaped groove 59 having a bottom (indicated by a two-dot chain line). Generally, this cutting is performed by a diamond cutter (Dc), a diamond blade, or a scribing method of cutting with a laser beam. However, in the present invention, a V-shaped groove 59 having a bottom is used, and the silicon wafer 51 is deformed by pressurizing or depressurizing a fluid to form the groove 57.
, Or the silicon wafer 51 can be deformed and broken by a mechanical pressing force of a roller or the like, thereby facilitating the manufacturing. Note that in the above step, the etching protection film 57 may be removed with an aqueous solution, a solvent, or the like before cutting.

In FIG. 3D, an electrode 53 is formed on the upper inclined portion 61 of the semiconductor chip 14 from which the V-shaped groove 59 has been cut. Although FIG. 2 shows an insulating film (SiO 2) 63 on the semiconductor chip 14, the insulating film 6
The formation of 3 may be performed before the formation of the electrode 53 or before the formation of the etching protection film 57. The electrode 53 is formed, for example, by vapor deposition of aluminum.

In FIG. 3E, the semiconductor chip 14 on which the electrodes 53 are formed is tilted in the same direction as the upper inclined portion 61 on which the electrodes 53 are mounted.
Are laminated with an insulating adhesive resin 65 interposed therebetween.
In addition, the stacked electrodes 53 are connected by bonding wires 67 so as to conduct electricity. As a result, the length of the wire bonding 67 can be made substantially the same, and the deterioration of the electrical characteristics can be minimized. Further, even when the upper semiconductor chip 14a and the lower semiconductor chip 14b of the same size are used, the wire bonding 6
The space for 7 is unnecessary, and the external dimensions can be reduced. The wire bonding 67 may be connected to an external electrode terminal 26 formed on the printed circuit board 12 described later.

FIG. 4 is a process diagram showing a partial cross-sectional side shape of an electrode structure of a multi-chip package 10A according to a second embodiment of the present invention. Components having the same functions as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

In the first embodiment, an etching protection film 57 is applied on the upper surface of the silicon wafer 51 except for an electrode forming portion 55 where the electrodes 53 of the semiconductor chip 14 are formed. The portion 55 is edged to form a V-shaped groove 59. On the contrary,
In the second embodiment, the silicon wafer 51 at the same location as the electrode forming portion 55 where the electrodes 53 of the semiconductor chip 14 are formed
A V-shaped lower groove 71 is also formed on the back surface of the substrate. That is, as shown in FIG.
The coating of the etching protection film 57 is removed at the same location as the electrode forming section 55 of the electrode 53 of the semiconductor chip 14 formed on the upper surface of the semiconductor chip 14 and on the back surface (Fb) of the silicon wafer 51. V-shaped lower groove 71
Is formed.

FIG. 4B shows a V-shaped groove 59 formed on the upper surface of the silicon wafer 51 and a silicon wafer 5.
The silicon wafer 51 is deformed by the pressurization or decompression of the fluid at the position of the V-shaped lower groove 71 formed on the lower surface of the substrate 1 and breaks at the position of the groove 59 and the lower groove 71 (Ca).
Is done. As a result, in the semiconductor chip 73, a lower inclined portion 75 is formed by the V-shaped lower groove 71. Also,
For the cutting, the silicon wafer 51 may be deformed and broken by a mechanical pressing force of a roller or the like. This allows
The division of the silicon wafer 51 is facilitated, and the cutting time and cost can be reduced.

In FIG. 4E, the semiconductor chip 73 on which the electrode 53 is formed is tilted in the same direction as the upper inclined portion 61 on which the electrode 53 is mounted, and the semiconductor chip 73 is tilted.
Are laminated with an insulating adhesive resin 65 interposed therebetween.
In addition, the stacked electrodes 53 are connected by bonding wires 67 so as to conduct electricity. At this time, since the semiconductor chip 73 has the lower inclined portion 75 on the back surface at the same place as the electrode 53, interference when performing the wire bonding 67 is eliminated, and the connection of the wire bonding 67 is facilitated. Further, similarly to the above, the connection length of the wire bonding 67 can be made substantially the same. Further, as described above, even when the upper semiconductor chip 73a and the lower semiconductor chip 73b have the same size, a space for the wire bonding 67 is not required.

FIG. 5 is a partial cross-sectional side view of an electrode structure of a multi-chip package 10B according to a third embodiment of the present invention.

In the third embodiment, the semiconductor chip 14
FIG. 3D of the first embodiment or FIG. 4C
3 (d) are the same as those manufactured in the step of attaching the electrodes of FIG.

In the third embodiment, the upper semiconductor chip 14a
And the lower semiconductor chip 14b are used as a pair, and the pair of semiconductor chips 14 are provided with the upper inclined portions 61 on which the electrodes 53 are mounted facing each other. At this time, although not shown, as in the first embodiment, the semiconductor chips 14 may be stacked with an insulating adhesive resin 65 interposed therebetween. Solder balls 81 are provided on the stacked electrodes 53.
Are bonded to each other, and the solder balls 81 are connected to each other by bonding wires 67a to establish conduction.
At this time, it is preferable that the electrode 53 be plated with gold (Au) to improve the adhesiveness and improve the conductivity. This allows
The pair of semiconductor chips 14 are connected to one solder ball 81 and the bonding wire 67a to perform conduction, so that the structure is simplified and the manufacturing is facilitated.
They can be connected by bonding wires 67a of the same length. Thereby, similarly to the above, the deterioration of the electric characteristics can be minimized. In the above embodiment, the solder balls 81 are used. However, solder may be applied from an unillustrated ink jet and may be conducted by the solder. Further, the insulating film 82 may be formed on the end face of the semiconductor chip 14 from the ink jet.

FIG. 6 is a partial sectional side view of an electrode structure of a multi-chip package 10C according to a fourth embodiment of the present invention.

In the fourth embodiment, as in the third embodiment, the semiconductor chip 14 has the electrodes shown in FIG. 3 (d) up to FIG. 3 (d) of the first embodiment or FIG. 5 (c). The same one manufactured in the attached process is used.

In the fourth embodiment, similarly to the third embodiment, the upper semiconductor chip 14a and the lower semiconductor chip 14b
Are used as a pair, and this pair of semiconductor chips 14
The upper inclined portion 61 on which the electrode 53 is mounted is opposed to each of a and 14b or 14c and 14d, and a solder ball 81 is bonded to the electrode 53. In the third embodiment, the solder balls 81 are connected to each other by the bonding wires 67a so as to establish electrical continuity. In the fourth embodiment, the solder balls 81 are connected by the lead rods 83 to establish electrical continuity. The solder ball 81 and the lead rod 83 are welded and connected by a laser beam. Since the others are the same, detailed description is omitted. The lead rod 83 may be connected to an external electrode terminal 26 formed on the printed circuit board 12 described later.

FIG. 7 is a partial cross-sectional side view of an electrode structure of a multi-chip package 10D according to a fifth embodiment of the present invention.

In the fifth embodiment, as in the third embodiment, the semiconductor chip 14 has the electrodes shown in FIG. 3 (d) up to FIG. 3 (d) of the first embodiment or FIG. 5 (c). The same one manufactured in the attached process is used.

In the fifth embodiment, the semiconductor chip 14 on which the electrodes 53 are formed is tilted in the same direction as the upper inclined portion 61 on which the electrodes 53 are mounted, and the upper semiconductor chip 85a and the lower semiconductor chip 85b are separated. They are arranged out of phase. Since the inclined electrodes 53 are arranged on substantially the same straight line, the bonding wires 67b
Connection becomes easier, and the wire bonding 67
The length of b can be made substantially the same, and the deterioration of the electrical characteristics can be minimized.

FIG. 7 shows multi-chip packages 10A to 10D according to the embodiment using the electrode structure described above.
2 is an example of a schematic perspective view showing a state in which one of the above is mounted on the printed circuit board 12, and FIG. 2 is a cross-sectional view illustrating an example of a state of connection between terminals of the multi-chip package 10.
As shown in these figures, the multi-chip package 10 includes a plurality of semiconductor chips 14A, 14 of different sizes.
B and 14C are vertically stacked such that two adjacent sides thereof are aligned. In other words, regardless of the size of the semiconductor chips 14A, 14B, 14C,
They are laminated so that their one corners coincide. In this embodiment, a square smallest semiconductor chip 14A is arranged in the upper layer, a slightly larger square semiconductor chip 14B is arranged in the lower intermediate layer, and the lowermost semiconductor chip 14A is The rectangular semiconductor chips 14C having a longer side longer than one side of the chip 14B and a shorter side shorter than one side of the square semiconductor chip 14B are stacked. Then, a plurality of minimum semiconductor chips 14 of the same size
A is continuously laminated with the edges aligned (three layers in the illustrated example).

In order to stack a plurality of semiconductor chips 14A, 14B, 14C of the same or different sizes in such a manner that one corner coincides so that two adjacent sides 16X, 16Y are aligned, each semiconductor chip is stacked. Chip 1
4 (14A, 14B, 14C) adopts the following configuration. That is, each of the semiconductor chips 14A, 14A
B, 14C are connected to the aligned edge 16
It is concentrated on the X and 16Y sides. For example, when the semiconductor chip 14 is configured as a memory element, electrode terminals such as a power supply line, a data line, and an address line;
Alternatively, a common control terminal such as a write enable can be used. Therefore, such a common terminal 18n
(N = 1, 2,..., N) are concentrated on the alignment edges 16X, 16Y of each semiconductor chip 14. At this time, the arrangement pattern of the common terminals of each semiconductor chip 14 is made to match. Of course, it is desirable to keep the terminal pitch interval constant. By doing so, when the semiconductor chips 14 are stacked, the terminals 18n arranged on the end surfaces of the stacked body are arranged in a straight line in the vertical direction.

In stacking the semiconductor chips 14,
By interposing the insulating adhesive resin 20 (see FIG. 3) between the layers, it is possible to prevent problems due to contact between the terminal and the substrate silicon between chips. Then, the terminal 18n of the laminated chip 14
As shown in FIG.
2 and the like to establish conduction. This is because, for example, an inclined surface is formed in the arrangement edge 16X, 16Y of the terminal 18n of each semiconductor chip 14, and the terminal 18n is formed.
A metallization layer 24 is formed on the metallization layer 24 to extend on the inclined surface, wire bonding is performed using the metallization layer 24, and connection to the external electrode terminals 26 formed on the printed circuit board 12 is performed by wire bonding. Just do it.

The multichip package 10 thus formed is mounted on the printed circuit board 12, and the connector terminals 32 provided on the edge of the printed circuit board 12 and the common electrode 18 n are connected by the wiring line 34. . Thus, a semiconductor device 36 having a function is manufactured. In the multi-chip package 10, the semiconductor chips 14 of different sizes are designed and manufactured so that the common terminal 18n is concentratedly arranged on the adjacent two sides 16X and 16Y, and the corners are matched so that these two sides 16X and 16Y are aligned. Since the configuration in which the chips are stacked is adopted, the chips need not be stacked in a pyramid shape, and the stacking operation can be performed extremely easily. And since there is no limitation on the stacking by the chip size, the stacking order can be set arbitrarily,
The degree of freedom in package design is significantly increased. Further, the connection distance between the common terminals 18n of the stacked chips 14 can be made common between the upper and lower sides, and
Is also the shortest. As a result, the deterioration of the electric characteristics can be suppressed to the minimum. Uneven edges are formed at portions other than the aligned edges 16X and 16Y of the multi-chip package 10, but there is no problem since the outer shape can be adjusted by resin molding.

In the above configuration, the semiconductor chips 14A, 14B, and 14C having different sizes are stacked. However, the semiconductor chips 14A, 14B, and 14C having different sizes are stacked regardless of the size. An electrode common to them is arranged in the same arrangement pattern within a range of two adjacent sides of each chip, and the two sides are aligned to stack different kinds of semiconductor chips, and a common electrode is formed at an end face of the stacked body. May be connected. Also in this case, the semiconductor chips of the same type may be continuously stacked as in the case of the semiconductor chip 14A described above.

FIG. 8 shows a circuit board 1000 on which the semiconductor device 36 according to the embodiment of the present invention is mounted. As the circuit board 1000, for example, an organic substrate such as a glass epoxy substrate is generally used. Circuit board 1000
For example, a bonding portion made of copper is formed so as to form a desired circuit. Then, by electrically connecting the bonding portion and the external electrode of the semiconductor device 36, their electrical continuity is achieved.

Since the mounting area of the semiconductor device 36 can be reduced to the area for mounting with a bare chip, the size of the electric equipment itself can be reduced by using the substrate circuit 1000 for electronic equipment. In the same area, more mounting space can be ensured, and higher functionality can be achieved.

FIG. 9 shows a notebook personal computer 1 as an electronic apparatus having the circuit board 1000.
200 is shown. Since the notebook personal computer 1200 includes the highly functional circuit board 1000, the performance can be improved.

[0052]

As described above, in the semiconductor chip according to the present invention, the V-shaped or pyramid-shaped groove is formed by etching a predetermined electrode portion of the semiconductor chip on the wafer. Since the grooves are cut and divided, and the electrodes are formed in the inclined portions of the grooves of the divided semiconductor chips, the division is facilitated for cutting in the groove having the bottom, and the electrodes are formed in the inclined portions. Therefore, the production of the electrode becomes easy. Further, since the electrodes are formed on the divided inclined portions, even if semiconductor chips of the same size are used, a space for wire bonding becomes unnecessary, and the outer dimensions can be reduced. Further, since the lengths of the wire bonding can be made substantially the same, the deterioration of the electric characteristics can be minimized, and the manufacturing becomes easy.

In addition to the above, a V-shaped groove is formed by etching the back surface of the silicon wafer, and the position of the V-shaped or pyramid-shaped groove portion and the V-shaped groove portion on the back surface is formed. The electrode is formed on the inclined portion of the divided semiconductor chip, and the end surface of the chip is arranged substantially in a straight line. Interference at the time is eliminated, and connection of wire bonding is facilitated.

In a multi-chip package,
It is preferable that the inclined portions on which the electrodes of the semiconductor chip are formed are laminated while being inclined in the same direction, and the respective electrodes are connected by wire bonding.

According to the present invention configured as described above, the length of the wire bonding can be made substantially the same, the deterioration of the electric characteristics can be minimized, and the electrodes can be connected in the same row. Manufacturing becomes easier.

Further, since the inclined portions on which the electrodes of the semiconductor chip are formed are laminated to face each other and the electrodes are connected by solder balls or solder balls and wire bonding, one solder ball is used. Since the electrodes of the two chips can be connected, manufacturing becomes easy.

Further, a plurality of semiconductor chips of the same or different sizes are stacked with their adjacent two sides aligned, and the terminals common to each semiconductor chip are concentrated on the aligned edge side, and are arranged in a concentrated manner. Since the electrodes are arranged and connected to the terminals between the stacked chips, the electrodes are concentrated and arranged within two adjacent sides, and the electrodes can be connected in the same row, thereby facilitating the manufacturing. In addition, three-dimensional mounting of a semiconductor chip can be facilitated, and deterioration of electrical characteristics can be minimized.

[Brief description of the drawings]

FIG. 1 is a perspective view or a process diagram showing a partial cross-sectional side shape of a multi-chip package according to an embodiment of the present invention.

FIG. 2 is a perspective view or a process diagram showing a partially cross-sectional side view of a multi-chip package according to another embodiment of the present invention.

FIG. 3 is a process diagram showing a partial cross-sectional side shape of the electrode structure of the multi-chip package according to the first embodiment of the present invention.

FIG. 4 is a process diagram showing a partial cross-sectional side shape of an electrode structure of a multi-chip package according to a second embodiment of the present invention.

FIG. 5 is a partial cross-sectional side view of an electrode structure of a multi-chip package according to a third embodiment of the present invention.

FIG. 6 is a partial cross-sectional side view of an electrode structure of a multi-chip package according to a fourth embodiment of the present invention.

FIG. 7 is a partial cross-sectional side view of an electrode structure of a multi-chip package according to a fifth embodiment of the present invention.

FIG. 8 is an explanatory diagram of an application example of the multichip package according to the embodiment to a circuit board.

FIG. 9 is an explanatory diagram of an application example to an electronic device mounted with the multi-chip package according to the embodiment.

[Explanation of symbols]

Reference Signs List 10 (10A, 10B, 10C, 10D) Multi-chip package 12 Printed circuit board 14 (14A, 14B, 14C) Semiconductor chip 16X, 16Y Alignment edge 18n Common terminal 20 Insulating adhesive resin 22 Bonding wire 24 Metallization layer 26 External electrode terminal 51 Silicon wafer 53 Electrode 55 Electrode forming part 57 Etch protective film 59 Groove 61 Inclined part 63 Insulating film 65 Insulating adhesive resin 67 Bonding wire 71 Lower groove 73, 85 Semiconductor chip 75 Lower inclined part 81 Solder ball 83 Lead rod

Claims (8)

[Claims] 1. A semiconductor chip formed by etching a predetermined electrode portion of a semiconductor chip on a wafer to form a V-shaped or pyramid-shaped groove, cutting the groove, and dividing the groove. Wherein an electrode is formed on an inclined portion of the groove. 2. Etching is performed on an electrode portion of a semiconductor chip which is set in advance on a wafer to form a V-shaped or pyramid-shaped groove, and etching is performed on the back surface of the silicon wafer at the same position as the electrode portion. To form a V-shaped groove, and cut and divide the V-shaped or pyramid-shaped groove at the position of the V-shaped groove on the back surface to form an electrode on the inclined portion of the divided semiconductor chip. A semiconductor chip characterized by the following. 3. The semiconductor chip according to claim 1, wherein semiconductor chips having electrodes formed on the upper inclined portion are stacked, and the electrodes of each semiconductor chip are connected by a conductive portion. And a multi-chip package. 4. The multi-chip package according to claim 3, wherein the upper inclined portions on which the electrodes are formed are stacked while being inclined in the same direction, or the upper inclined portions on which the electrodes are formed are stacked facing each other. A multi-chip package characterized by any one of the above. 5. The multi-chip package according to claim 3, wherein the end face on the electrode side of the multi-chip package in which the upper inclined portions on which the electrodes are formed are inclined in the same direction and are stacked is substantially linear and perpendicular to the electrode. A multi-chip package, wherein the formed upper inclined portions are arranged on any of substantially linear slopes. 6. The multi-chip package according to claim 4, wherein the conductive part for connecting the electrodes comprises:
A semiconductor device, wherein each electrode is connected to an electrode of a logic chip by one of wire bonding, solder ball and wire bonding, or a lead rod, or a combination of solder applied by ink jet and wire bonding or a lead rod. . 7. The multi-chip package according to claim 4, wherein a plurality of semiconductor chips of the same or different sizes are stacked with their adjacent two sides aligned and stacked, and are common to each semiconductor chip. A semiconductor device, wherein terminals are concentrated on the aligned edge side, and electrodes are arranged and connected between the terminals between the stacked chips arranged in a concentrated manner. 8. The electronic device according to claim 7, wherein the semiconductor device is connected to a motherboard to form a circuit.