JP2001109531A - Stabilized power circuit, subboard for computer equipped with same, and information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the whole system from being down by suppressing a rush current flowing to an output capacitor C1 for smoothing by a stabilized power circuit 11 mounted on a subboard of a computer when a power source 12 is turned on. SOLUTION: An LSI for the subboard needs to have a reset period when the power source is turned on and in this reset period, the LSI does not require large current consumption usually; even if the output current of a stabilized power circuit 11 is small, there is no deficiency in supply of the output current, so an input monitor circuit 19 charges an output capacitor C1 while setting the overcurrent protection value of an overcurrent protecting circuit 18 for a control transistor Q1 to a relatively small value in the reset period and puts it back to a normal value when the capacitor is fully charged a certain time later.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stabilized power supply circuit.
The present invention relates to a computer sub-board on which the stabilized power supply circuit is mounted and an information processing apparatus including the computer sub-board.

[0002]

2. Description of the Related Art Recently, integrated circuits mounted on computer sub-boards such as graphic boards and sound boards have been reduced in voltage and increased in current. On the other hand, the power supply inside the computer has a power supply of 5V and 12V. Because of two systems, a stabilized power supply circuit that generates a low voltage such as 3.3 V from 5 V is required. Also, with the increase in current,
Since the current waveform has become steeper, the capacity of the output capacitor of the stabilized power supply circuit has increased.

FIG. 10 is a block diagram showing an electrical configuration of a typical conventional stabilized power supply circuit 1. As shown in FIG. In the stabilized power supply circuit 1, an output transistor tr is disposed in series with a power supply line 4 from a power supply 2 to a load 3, and a control terminal of the output transistor tr corresponds to an output voltage vo. By controlling the input voltage vin from the power supply 2 to a desired output voltage vo and outputting the output voltage vo to the load 3. The power supply 2 and the output transistor tr
And a choke coil 1 for suppressing an inrush current to be described later, and on the output side, in parallel with the load 3,
An output capacitor c for smoothing is provided externally.

A feedback voltage va obtained by dividing the output voltage vo by voltage dividing resistors r1 and r2 is input to the control circuit 5, and a comparator 6 outputs the feedback voltage va and a constant current source f. And the reference voltage vref generated by the reference voltage generating circuit 7 are compared with each other, and an error signal corresponding to the difference between the two is supplied to the base of the output transistor tr via the control transistor q1. The base current of tr is adjusted, and the constant voltage operation as described above is performed.

An overcurrent protection circuit 8 is provided in connection with the control transistor q1. The overcurrent protection circuit 8 includes a current detection resistor r3 and a control transistor q2
It is provided with. The current detection resistor r3 is
The voltage conversion is performed on the collector current of the control transistor q1, that is, the base current of the output transistor tr. The control transistor q2 is an output of the comparator 6,
That is, the current detecting resistor r3 interposed between the base of the control transistor q1 and the ground and applied to the base.
As the terminal voltage of the output transistor tr increases, that is, as the base current of the output transistor tr increases, the error signal from the comparator 6 is bypassed, and the base current of the output transistor tr is suppressed. In this way, an overcurrent protection operation for preventing the output transistor tr from being destroyed by an overcurrent is performed.

[0006]

In the stabilized power supply circuit 1 configured as described above, if the output capacitor c is completely discharged when the stabilized power supply circuit 1 is started, the stabilized power supply circuit 1 has an extremely low impedance on the output side, and the charging current flows to the overcurrent protection value set by the overcurrent protection circuit 7 until the output capacitor c is charged with electric charge and becomes a high impedance state. . The period during which the charging current flows is a period until the charging is completed, and depends on the capacity of the output capacitor c.

FIG. 11 is a waveform diagram showing the output on / off characteristics of the stabilized power supply circuit 1 configured as described above.
Constant input voltage vin = 7V, output voltage vo = 5V,
Output current io = 0.5 A, overcurrent protection value iop = 1.4
A. For example, by turning on / off the constant current source f and controlling generation of the reference voltage vref by the reference voltage generation circuit 7, the output of the stabilized power supply circuit 1 is turned on / off.

When output control voltage vc for turning on / off constant current source f rises at time t1, output voltage v
It can be understood that a current up to the overcurrent protection value iop flows through the input current iin during a period from the start of the activation of the output capacitor o to the time t2 when the charging of the output capacitor c is completed. In addition, the input voltage vin lacks transient current responsiveness,
It is understood that the input voltage vin decreases during the period when the current up to the overcurrent protection value iop flows.

FIG. 12 is a waveform diagram showing the rise of the stabilized power supply circuit 1, that is, the characteristics when the power supply 2 is turned on. As described above, the steady-state input voltage vin = 7
V, output voltage vo = 5V, output current io = 0.5A, and overcurrent protection value iop = 1.4A. When the input voltage vin is applied at time t11, the output voltage vo starts to be activated, and during the period until time t12 when the charging of the output capacitor c is completed, the current up to the overcurrent protection value iop may flow. Understood.

On the other hand, in recent computers, peripheral devices can be connected and disconnected in the operating state of the computer, such as plug and play, and the sub-board is inserted and removed from the motherboard in a live state. Therefore, when a sub-board in which the mounted circuit is always on (operable when power is supplied) is mounted, the stabilized power supply circuit 1 performs a rising operation as shown in FIG. . In addition, the LSI for the sub-board has a stabilizing power supply circuit 1 as shown in FIG. Output on / off function is used.

However, as described above, in recent years, the operating voltage and the current consumption of the sub-board LSI have been reduced, and accordingly, the stabilized power supply circuit 1 mounted on the sub-board has The output voltage has been reduced, the output current has been increased, the transient current has been sharpened, and the capacity of the output capacitor c has been increased. Therefore, the charging current (rush current) flowing through the output capacitor c at the time of the rise or the output ON is relatively large, which affects the input power supply 2 of the stabilized power supply circuit 1 and the transient current response of the input voltage vin is poor. In addition, there is a problem that the input voltage vin may be reduced in voltage, leading to malfunction of the entire device.

Therefore, the choke coil 1 is inserted in order to dull the waveform of the rush current. Also,
For example, in Japanese Patent Application Laid-Open No. 6-311739, a parallel circuit composed of a fuse resistor and a bypass FET is inserted, and when the power is turned on, the bypass FET is opened to suppress an inrush current. Furthermore, Japanese Patent Application Laid-Open
Japanese Patent Application Laid-Open No.-327244 discloses a configuration in which, when a circuit unit is mounted, a terminal via a current limiting resistor is connected first, and then a directly connected terminal is connected.

[0013] However, any of the above-mentioned conventional techniques not only causes an increase in cost, but also results in an increase in loss, a deterioration in transient current response of the stabilized power supply circuit, and the like.

An object of the present invention is to provide a stabilized power supply circuit having a simple configuration and not deteriorating characteristics, a computer sub-board including the same, and an information processing apparatus.

[0015]

According to the stabilized power supply circuit of the present invention, an overcurrent lower than a normal overcurrent protection value for a period shorter than a reset operation period of a load side circuit in response to a rise of an input power supply. It operates at the protection value, and operates at the normal overcurrent protection value after the period has elapsed.

According to the above configuration, a load-side circuit such as an integrated circuit performs a reset operation when the input power to the stabilized power supply circuit is turned on. During the reset operation period, utilizing the fact that the current consumption of the load side circuit is relatively small, within the reset operation period, the stabilized power supply circuit firstly sets an overcurrent protection value lower than a normal overcurrent protection value. And then returns to the normal overcurrent protection value.

Therefore, the rush current to the smoothing output capacitor can be suppressed during the period without causing a shortage of the supply to the load side circuit. In this way, it is possible to realize a simple and low-cost stabilized power supply circuit without deteriorating characteristics such as loss and transient current responsiveness.

Further, the stabilized power supply circuit of the present invention has a control circuit that controls a base current of an output transistor interposed in series on a power supply line from a power supply to a load in accordance with an output voltage, so that a desired value is obtained. In a stabilized power supply circuit that obtains an output voltage stabilized to a voltage that exceeds the threshold voltage, an overcurrent protection circuit that suppresses the base current when an overcurrent occurs, and the overcurrent protection circuit responds to a rise of an input power supply. ,
An input monitoring circuit that operates at an overcurrent protection value lower than the normal overcurrent protection value for a period shorter than the reset operation period of the load-side circuit, and operates at the normal overcurrent protection value when the period elapses. It is characterized by the following.

According to the above configuration, the input monitoring circuit monitors the power supply, and in response to the power-on, supplies the overcurrent protection circuit with the load-side circuit during the reset operation. First, the operation is performed with an overcurrent protection value lower than the normal overcurrent protection value, and thereafter, the operation is restored to the operation with the normal overcurrent protection value.

Therefore, the rush current to the smoothing output capacitor can be suppressed during the period without causing a shortage of the supply to the load side circuit. In this way, it is possible to realize a simple and low-cost stabilized power supply circuit without deteriorating characteristics such as loss and transient current responsiveness.

Further, the stabilized power supply circuit according to the present invention comprises:
In response to the switching of the output from off to on, the load-side circuit operates at an overcurrent protection value lower than the normal overcurrent protection value for a shorter period than the reset operation period, and when the period elapses, the normal It operates with an overcurrent protection value.

According to the above configuration, the load-side circuit such as an integrated circuit performs a reset operation in response to switching of the output of the stabilized power supply circuit from off to on. During the reset operation period, the stabilized power supply circuit uses the fact that the current consumption of the load-side circuit is relatively small.
First, it operates with an overcurrent protection value lower than the normal overcurrent protection value, and then returns to the normal overcurrent protection value.

Therefore, the rush current to the smoothing output capacitor can be suppressed during the period without causing a shortage of the supply to the load side circuit. In this way, it is possible to realize a simple and low-cost stabilized power supply circuit without deteriorating characteristics such as loss and transient current responsiveness.

Further, the stabilized power supply circuit of the present invention has a control circuit that controls a base current of an output transistor interposed in series on a power supply line from a power supply to a load in accordance with an output voltage, so that a desired value is obtained. A stabilized power supply circuit that obtains an output voltage stabilized to a voltage that causes the overcurrent protection circuit to suppress the base current when an overcurrent occurs; and an overcurrent protection circuit that responds to an on / off signal from the outside. When the output is switched from off to on, the circuit is operated with an overcurrent protection value lower than a normal overcurrent protection value for a period shorter than the reset operation period of the load side circuit, and when the period elapses, the normal operation is performed. And an overcurrent protection value switching means that operates with the overcurrent protection value.

According to the above arrangement, the overcurrent protection value switching means monitors an external on / off signal, and when it is input that the output should be switched from off to on,
During the period when the load side circuit is performing the reset operation, the overcurrent protection circuit first operates with the overcurrent protection value lower than the normal overcurrent protection value, and then returns to the operation with the normal overcurrent protection value Let it.

Therefore, the inrush current to the smoothing output capacitor can be suppressed during the period without causing a shortage of the supply to the load side circuit. In this way, it is possible to realize a simple and low-cost stabilized power supply circuit without deteriorating characteristics such as loss and transient current responsiveness.

Still further, in the stabilized power supply circuit according to the present invention, during the period, the amount of charge to be stored in the output capacitor determined by the capacitance and the output voltage of the output capacitor and the normal overcurrent protection value It is set to be longer than the charging period of the output capacitor determined based on the lower overcurrent protection value.

According to the above configuration, the overcurrent protection value can be reliably reduced until a predetermined amount of charge to be stored in the output capacitor is stored, and the occurrence of the rush current is prevented. Can be reliably prevented.

In the stabilized power supply circuit according to the present invention, the period is determined by a charging time of an external capacitor.

According to the above configuration, the electrostatic capacitance of the external capacitor is set corresponding to the reset operation period of the integrated circuit or the like and the charging period of the output capacitor determined by the capacitance and the output voltage of the output capacitor. By simply selecting the capacitance, the period during which the overcurrent protection value is reduced can be reliably set within the reset operation period and an optimum period equal to or longer than the period during which charging of the output capacitor is completed.

Further, the stabilized power supply circuit of the present invention
The power supply system further comprises first discharging means for discharging the electric charge of the external capacitor when the power is turned on.

According to the above configuration, the input voltage is turned off immediately after the input rise operation, and the power supply is turned off again in a state where the potential of the external capacitor has been increased while the output capacitor has not been charged. In case of re-impeachment,
Since the charge of the external capacitor is discharged by the first discharging means, in such a case, the output capacitor is not charged with a high overcurrent protection value.
Even in such a case, the overcurrent protection value can be reliably reduced.

Further, the stabilized power supply circuit according to the present invention is characterized by further comprising a second discharging means for discharging the electric charge of the external capacitor in response to an external signal.

According to the above configuration, the electric charge of the external capacitor can be discharged also by the external signal, and while the external signal is being output, the overcurrent protection value is forcibly kept low. Can be maintained.

Further, in the stabilized power supply circuit according to the present invention, the overcurrent protection circuit detects a base current of the output transistor, and comprises a plurality of n current detection resistors arranged in parallel with each other; It is characterized by comprising a control transistor connected in series with at least n-1 current detection resistors among a plurality of current detection resistors, and switching means for selectively switching the control transistors. And

According to the above configuration, by using a plurality of n current detecting resistors sequentially or in appropriate combination by at least n-1 control transistors,
It is possible to configure so that the resistance value gradually decreases.

In the stabilized power supply circuit according to the present invention, the output transistor is a multi-collector transistor, and the overcurrent protection circuit detects a collector current of a part of the output transistor and is arranged in parallel with each other. Multiple n
A plurality of current detecting resistors, a control transistor connected in series with at least n-1 current detecting resistors among the plurality of current detecting resistors, and a switching means for selectively switching the control transistors. It is characterized by comprising.

According to the above configuration, the plurality of n current detecting resistors are used sequentially or in appropriate combination by at least n-1 control transistors, whereby:
It is possible to configure so that the resistance value gradually decreases. In addition, by using overcurrent protection from the collector current as compared to the configuration that protects the overcurrent from the base current of the output transistor, the chip size of the output transistor part increases, but the accuracy of the overcurrent protection value is improved. It can be improved and can be suitably used when accuracy of overcurrent protection is required.

Further, the stabilized power supply circuit of the present invention
The power supply system further includes a reset signal generation circuit that outputs a reset signal when at least one of the input voltage and the output voltage of the stabilized power supply circuit decreases.

According to the above configuration, a stabilizing power supply circuit can be provided with a reset signal output function for the reset function necessary for most computer sub-boards, and the convenience can be improved.

A computer sub-board according to the present invention is provided with any one of the above-mentioned stabilized power supply circuits.

According to the above configuration, a desired low voltage is generated from a power supply of, for example, 5 V or 12 V in the computer, and a low voltage is generated in a live state in response to a reduction in the voltage of the integrated circuit mounted on the sub-board. It is possible to suppress the rush current to the output capacitor in response to the insertion / removal or the on / off signal from the motherboard.

Further, an information processing apparatus according to the present invention uses any one of the above stabilized power supply circuits.

According to the above configuration, since the information processing apparatus uses the sub-board or the motherboard on which the above-mentioned stabilized power supply circuits are mounted, the information processing apparatus can be inserted and removed in the hot-line state, and can be used for power saving. Rush current to the output capacitor can be suppressed with respect to the on / off operation.

[0045]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing a schematic configuration of a stabilized power supply circuit 11 according to the first embodiment of the present invention.
The stabilized power supply circuit 11 is mounted on the sub-board, and generally includes a power supply line 1 from a power supply 12 to a load 13.
4, an output transistor TR1 is interposed in series, and the control terminal of the output transistor TR1 is controlled by the control circuit 15 in accordance with the output voltage Vo, so that the input voltage Vin from the power supply 12 becomes a desired output voltage. This is a three-terminal regulator that is stabilized at Vo and outputs to the load 13. On the output side of the stabilized power supply circuit 11, an output capacitor C1 for smoothing is connected in parallel with the load 13.
Is attached externally.

The output voltage Vo is applied to the control circuit 15.
Is input by a feedback voltage Va obtained by voltage dividing by the voltage dividing resistors R1 and R2,
The feedback voltage Va and the reference voltage Vre generated by the constant current source F1 and the reference voltage generation circuit 17 are used.
f with each other, and an error signal corresponding to the difference between
The output transistor T is connected via the control transistor Q1.
By providing the output transistor TR to the base of R1,
1 and the constant current operation as described above is performed.

An overcurrent protection circuit 18 is provided in connection with the control transistor Q1. In response to the output of the input monitoring circuit 19, the overcurrent protection value of the overcurrent protection circuit 18 is controlled to a relatively low value when the input rises, and to a normal value after a certain period of time.

That is, the sub-board LSI requires a reset period when the power is turned on. During the reset period, the sub-board LSI often does not require a large current consumption. Even if the current is low, the output current supply capacity does not become insufficient, and the present invention utilizes this. The period reset is generally 3
It is about 0 to 100 msec.

Here, for example, assuming that the capacitance of the output capacitor C1 is 47 μF and the output voltage Vo is 3.3 V, the electric charge Q to be stored in the output capacitor C1 is as follows.

Q = C1 · Vo = 47 × 10 ⁻⁶ × 3.3 =
155.1 × 10 ⁻⁶ [Coulomb] On the other hand, if the low overcurrent protection value is 0.3 A, the charging period Δt of the output capacitor C1 is Δt = ΔQ / I = 155.1 × 10 ^{-6 /} /0.3=51
7 [μsec].

That is, since the charging period is sufficiently shorter than the reset period, there is no problem in the operation of the sub-board LSI, and it is at a level that does not cause a problem with the transient current response of the input voltage Vin. LS for sub board
The input monitoring circuit 19 lowers the overcurrent protection value of the overcurrent protection circuit 18 at the time of starting up to the current consumption required for I.

FIG. 2 is a block diagram showing a specific configuration of the overcurrent protection circuit 18 and the input monitoring circuit 19.
The overcurrent protection circuit 18 includes current detection resistors R3 and R4,
Control transistors Q2 and Q3 are provided. The current detection resistors R3 and R4 convert the emitter current of the control transistor Q1, that is, the base current of the output transistor TR1 into a voltage. The control transistor Q2 is interposed between the output of the comparator 16, that is, the base of the control transistor Q1 and ground,
The current detection resistor R3 or R provided to the base
3, the higher the terminal voltage of R4, that is, the larger the base current of the output transistor TR1, the more the error signal from the comparator 16 is bypassed, and the more the base current of the output transistor TR1 is suppressed. In this manner, an overcurrent protection operation for preventing the output transistor TR1 from being damaged by overcurrent is performed.

The control transistor Q3 is interposed in series with one of the current detecting resistors R3 and R4 (R4 in the example of FIG. 2) arranged in parallel with each other. The detection result of the voltage is cut off when the power supply rises below a predetermined threshold, whereby the resistance value of the current detection resistor increases, the overcurrent protection value becomes relatively low, and the voltage becomes higher than the threshold value. As a result, the resistance value of the current detection resistor decreases, and the overcurrent protection value becomes a relatively high normal value.

On the other hand, the input monitoring circuit 19 includes a constant current source F2
, A comparator 20, and an external capacitor C2. The constant current source F2 supplies a constant current from the power supply 12 to the external capacitor C2 via the external terminal T0. The terminal voltage of the external capacitor C2 is supplied to the inverting input terminal of the comparator 20.
0 compares the terminal voltage with the reference voltage Vref generated by the constant current source F1 and the reference voltage generation circuit 17 provided to the non-inverting input terminal, and when the terminal voltage becomes equal to or higher than the reference voltage Vref. A high level is output to the base of the control transistor Q3 to make the control transistor Q3 conductive, and if it is lower than the reference voltage Vref, a low level is output to the base of the control transistor Q3 to shut off the control transistor Q3.

Thus, when the power supply 12 is turned on, the overcurrent protection value becomes relatively low for the predetermined time determined by the current value of the constant current source F2, the capacitance of the external capacitor C2 and the reference voltage Vref, After the lapse of the predetermined time, the value becomes a normal value. In this manner, when the sub-board LSI completes the reset operation, the power supply can be performed as usual, and the power line 14 may be deteriorated in characteristics such as loss and transient current responsiveness. It is possible to realize a simple and low-cost stabilized power supply circuit without intervening elements.

The reset operation period of the integrated circuit, etc., the capacitance of the output capacitor C1 and the output voltage Vo
The fixed time can be optimally set only by selecting the capacitance of the external capacitor C2 in accordance with the charging period of the output capacitor C1 determined by the above.

In the overcurrent protection circuit 18, although the number of current detection resistors is two, three or more n may be provided in parallel. In this case, the number of control transistors is at least n. -1 input monitoring circuit 1
Reference numeral 9 performs comparison with n-1 reference voltages, and conducts each control transistor sequentially or appropriately. In this way, a configuration may be adopted in which the resistance value gradually decreases.

FIG. 3 shows a second embodiment of the present invention.
It is as follows if it explains based on.

FIG. 3 is a block diagram showing an electrical configuration of a stabilized power supply circuit 31 according to the second embodiment of the present invention.
The stabilized power supply circuit 31 includes the above-described stabilized power supply circuit 11.
, And corresponding parts are denoted by the same reference numerals,
The description is omitted. In the stabilized power supply circuit 31, a multi-collector type output transistor TR2 is used, and a current detection resistor R3 in the overcurrent protection circuit 38 detects a collector current of the output transistor TR2. The current detection resistor R3 is divided into R3a and R3b, and a series circuit of the current detection resistor R4 and the control transistor Q3 is connected in parallel with the current detection resistor R3b.

Therefore, while the stabilized power supply circuit 11 performs overcurrent protection from the base current, the stabilized power supply circuit 31 performs overcurrent protection from the collector current. Although there is an aspect that becomes large, it is possible to improve the accuracy of the overcurrent protection value by reducing the influence of the current amplification factor due to heat, etc., and it can be suitably used when the accuracy of the overcurrent protection is required. .

FIG. 4 shows a third embodiment of the present invention.
It is as follows if it explains based on.

FIG. 4 is a block diagram showing an electrical configuration of a stabilized power supply circuit 41 according to the third embodiment of the present invention.
The stabilized power supply circuit 41 includes the above-described stabilized power supply circuit 11.
, And corresponding parts are denoted by the same reference numerals,
The description is omitted. In the stabilized power supply circuit 41, the input monitoring circuit 49 includes the constant current source F2, the external capacitor C2, the comparator 20, and the input voltage dividing resistors R5, R6 and the diode D. I have.

The anode of the diode D is connected to the external capacitor C2, and the cathode is an input voltage dividing resistor R5.
Connected to the connection point of R6. Therefore, when the input voltage turns off and the input side goes low, the external capacitor C
2 is discharged through the diode D. As a result, in each of the stabilized power supply circuits 11 and 31, the input voltage is turned off immediately after the input rising operation, the output capacitor C1 is not charged and the external capacitor C1 is not charged.
If the power supply is re-impeached again in a state where the potential of 2 has risen, the output capacitor C1 may be charged in a state of a high overcurrent protection value. Since the power supply circuit 41 immediately discharges the charge of the external capacitor C2 when the input voltage is turned off, the overcurrent protection value can be reliably reduced in such a case.

FIG. 5 shows a fourth embodiment of the present invention.
It is as follows if it explains based on.

FIG. 5 is a block diagram showing an electrical configuration of a stabilized power supply circuit 51 according to the fourth embodiment of the present invention.
This stabilized power supply circuit 51 is the same as the aforementioned stabilized power supply circuit 41.
Is similar to In the stabilized power supply circuit 51, the constant current source F1 and the input monitoring circuit 5 in the control circuit 55
9, control transistors Q4 and Q5 are interposed between the constant current source F2 and the power supply line 14, respectively. The bases of the control transistors Q4 and Q5 have a power supply control mounted on a motherboard. An on / off signal input to the external input terminal T1 from an IC or the like is provided.

At the time of an ON signal, the external input terminal T1 is at a high level, and power is supplied to the constant current sources F1 and F2. At the time of an OFF signal, the external input terminal T1 is at a low level, and power is supplied to the constant current sources F1 and F2. The supply is cut off.

Thus, each of the stabilized power supply circuits 11, 3
1, 41 decrease the overcurrent protection value when the power supply 12 is turned on, and may operate with the normal overcurrent protection value when the output is switched from off to on by the output on / off function. On the other hand, the stabilized power supply circuit 51 can surely lower the overcurrent protection value even when the external on / off signal is switched from the off state to the on state.

FIG. 6 shows a fifth embodiment of the present invention.
It is as follows if it explains based on.

FIG. 6 is a block diagram showing an electrical configuration of a stabilized power supply circuit 61 according to the fifth embodiment of the present invention.
The stabilized power supply circuit 61 includes the stabilized power supply circuit 51 described above.
Is similar to The stabilized power supply circuit 61 includes a reset signal generation circuit 62 for resetting a microcomputer or the like when the power supply input voltage Vin decreases.

The reset signal generating circuit 62 includes voltage dividing resistors R7 and R8, a comparator 63, and an output transistor Q6. Comparator 63
Are the voltage dividing resistors R7, R8 applied to the non-inverting input terminal.
And the reference voltage Vref applied to the inverting input terminal are compared with each other. When the input divided voltage becomes equal to or higher than the reference voltage Vref, a low level is output to the base of the output transistor Q6 to perform the control. Transistor Q6
Is cut off, and when the voltage is lower than the reference voltage Vref, a high level is output to the base of the control transistor Q6 to make the control transistor Q6 conductive. Control transistor Q6
Are grounded, and the collector can output an open or ground level reset signal Vr to the external output terminal T2.

With this configuration, the reset function required for most sub-boards is
The stabilized power supply circuit 61 can be provided with an output function of the reset signal Vr in response to a decrease in the input voltage Vin, so that convenience can be improved.

FIG. 7 shows a sixth embodiment of the present invention.
It is as follows if it explains based on.

FIG. 7 is a block diagram showing an electrical configuration of a stabilized power supply circuit 71 according to the sixth embodiment of the present invention.
This stabilized power supply circuit 71 is the same as the aforementioned stabilized power supply circuit 61.
Is similar to In the stabilized power supply circuit 71, the reset signal generation circuit 62 is provided on the output side, and outputs the reset signal Vr when the output voltage Vo decreases.

With this configuration, it is possible to provide a reset signal output function in response to a decrease in the output voltage of the stabilized power supply circuit 71, thereby improving convenience. Incidentally, as shown by the stabilized power supply circuit 61,
It goes without saying that it may be used in combination with a configuration for detecting a decrease in the input voltage Vin.

FIG. 8 shows a seventh embodiment of the present invention.
It is as follows if it explains based on.

FIG. 8 is a block diagram showing an electrical configuration of a stabilized power supply circuit 81 according to the seventh embodiment of the present invention.
The stabilized power supply circuit 81 is the same as the stabilized power supply circuit 71 described above.
Is similar to In this stabilized power supply circuit 81, a control transistor Q7 is interposed in parallel with an external capacitor C2 in an input monitoring circuit 89, and an external signal input to an external input terminal T3 is provided at the base of the control transistor Q7. Given.

When the external signal goes high, the terminals of the external capacitor C2 are short-circuited and the comparator 20
Becomes the low level. Therefore, while the external signal is at the high level, the overcurrent protection value can be forcibly maintained at a low level.

The above-mentioned stabilized power supply circuits 41, 5
The output transistors 1, 61, 71, and 81 may be multi-collector transistors as in the above-described stabilized power supply circuit 31.

FIG. 9 shows each of the stabilized power supply circuits 11 and 3 described above.
1 is a block diagram showing an electrical configuration of an information processing device 90 using a computer sub-board 91 on which any of 1, 41, 51, 61, 71, 81 is mounted. The information processing device 90 is realized as a so-called personal computer, and the sub-board 91 is mounted on a motherboard 92. The information processing device 90 includes a power supply 93.
A power supply line 94 of 5 V and a power supply line 95 of 12 V are routed, and power is supplied to the hard disk device 96 and the CD-ROM device 97 together with the motherboard 92.

The sub-board 91 is the graphic board, the sound board, or the like, and its integrated circuit has a large current and a low voltage, for example, 3.3 V. Therefore, the stabilized power supply circuit mounted on the sub-board 91 generates 3.3 V from the 5 V or 12 V, and responds to the insertion / removal in the hot state or the on / off signal from the motherboard 92 to respond to the aforementioned. The inrush current to the output capacitor C1 as described above is suppressed.

Each of the stabilized power supply circuits 11, 31, 41,
Needless to say, 51, 61, 71 and 81 may be mounted not only on the sub-board 91 but also on the motherboard 92 as indicated by reference numeral 98 in response to the reduction in the voltage of the CPU and its peripheral circuits. No.

[0083]

As described above, in the stabilized power supply circuit of the present invention, the load side circuit such as an integrated circuit performs a reset operation when the input power is turned on.
Utilizing that the current consumption of the load side circuit is relatively small, during the reset operation period, the stabilized power supply circuit first operates at an overcurrent protection value lower than a normal overcurrent protection value,
After that, it returns to the normal overcurrent protection value.

Therefore, the inrush current to the smoothing output capacitor can be suppressed during the above-mentioned period without insufficiency of supply to the load side circuit, and the characteristics such as loss and transient current response deteriorate. And a simple and low-cost stabilized power supply circuit can be realized.

In the stabilized power supply circuit according to the present invention, as described above, the input monitoring circuit monitors the power supply, and the overcurrent protection circuit resets the load-side circuit in response to the power-on. During the period during which the operation is being performed, the operation is first performed with an overcurrent protection value lower than the normal overcurrent protection value, and then the operation is restored to the operation with the normal overcurrent protection value.

Therefore, the rush current to the smoothing output capacitor can be suppressed during the period without causing a shortage of the supply to the load side circuit, and the characteristics such as the loss and the transient current response deteriorate. And a simple and low-cost stabilized power supply circuit can be realized.

Further, the stabilized power supply circuit of the present invention
As described above, the load-side circuit such as the integrated circuit performs the reset operation in accordance with the switching of the output from off to on, so that during the reset operation period, the current consumption of the load-side circuit is relatively small. Utilizing the reset operation period, the stabilized power supply circuit first operates at an overcurrent protection value lower than the normal overcurrent protection value, and then returns to the normal overcurrent protection value.

Therefore, the inrush current to the smoothing output capacitor can be suppressed during the above-mentioned period without causing a shortage of the supply to the load side circuit, and the characteristics are deteriorated such as loss and transient current response. And a simple and low-cost stabilized power supply circuit can be realized.

Further, in the stabilized power supply circuit of the present invention, as described above, the overcurrent protection value switching means includes an external ON / OFF switch.
When the off signal is monitored and it is input that the output should be switched from off to on, the overcurrent protection circuit first applies the normal overcurrent protection during the period when the load side circuit is performing the reset operation. The operation is performed with the overcurrent protection value lower than the value, and then the operation is restored to the operation with the normal overcurrent protection value.

Therefore, the inrush current to the smoothing output capacitor can be suppressed during the above-mentioned period without causing a shortage of the supply to the load side circuit, and the characteristics such as the loss and the transient current response are deteriorated. And a simple and low-cost stabilized power supply circuit can be realized.

Further, the stabilized power supply circuit of the present invention
As described above, the period is determined based on the amount of charge to be stored in the output capacitor determined by the capacitance and the output voltage of the output capacitor, and the overcurrent protection value lower than the normal overcurrent protection value. Is set so as to be longer than the charging period of the output capacitor determined by the above.

Therefore, the overcurrent protection value can be reliably reduced until a predetermined amount of charge to be stored in the output capacitor is stored, and the occurrence of the rush current is reliably prevented. can do.

Further, in the stabilized power supply circuit of the present invention, the period is determined by the charging time of the external capacitor as described above.

Therefore, the capacitance of the external capacitor is selected according to the reset operation period of the integrated circuit or the like and the charging period of the output capacitor determined by the capacitance and the output voltage of the output capacitor. Thus, the period during which the overcurrent protection value is reduced can be reliably set within the reset operation period and an optimum period equal to or longer than the period during which charging of the output capacitor is completed.

Further, the stabilized power supply circuit of the present invention
As described above, the apparatus further includes the first discharging unit that discharges the electric charge of the external capacitor when the power is turned on.

Therefore, when the input voltage is turned off immediately after the input rising operation, the charge of the output capacitor is not charged and the potential of the external capacitor is increased, and the power supply is impeached again. In addition, since the charge of the external capacitor is discharged by the first discharging means, in such a case, the output capacitor is not charged in the state of the high overcurrent protection value. Also in this case, the overcurrent protection value can be reliably reduced.

Further, as described above, the stabilized power supply circuit of the present invention further includes the second discharging means for discharging the electric charge of the external capacitor in response to the external signal.

Therefore, the overcurrent protection value can be forcibly maintained low while the external signal is being output.

Further, the stabilized power supply circuit of the present invention
As described above, the overcurrent protection circuit includes the plurality of n current detection resistors for detecting the base current of the output transistor and at least n-1 control transistors.

Therefore, by using the current detecting resistors sequentially or in appropriate combination, the resistance value can be configured to gradually decrease.

Further, in the stabilized power supply circuit of the present invention, as described above, the output transistor is a multi-collector transistor, and the overcurrent protection circuit includes a plurality of n currents for detecting the base current of the output transistor. It is composed of a detection resistor and at least n-1 control transistors.

Therefore, by using the current detection resistors sequentially or in appropriate combination, the resistance value can be configured to gradually decrease. In addition, by performing overcurrent protection from the collector current as opposed to the configuration that performs overcurrent protection from the base current of the output transistor,
Although the chip size of the output transistor part increases, the accuracy of the overcurrent protection value can be improved,
It can be suitably used when accuracy of overcurrent protection is required.

Further, the stabilized power supply circuit of the present invention
As described above, the system further includes a reset signal generation circuit that outputs a reset signal when at least one of the input voltage and the output voltage of the stabilized power supply circuit decreases.

Therefore, a stabilizing power supply circuit can be provided with a reset signal output function with respect to a reset function necessary for most computer sub-boards.
Convenience can be improved.

Further, as described above, the computer sub-board of the present invention has any one of the above-mentioned stabilized power supply circuits mounted thereon.

Therefore, in response to the reduction in the voltage of the integrated circuit mounted on the sub-board, a desired low voltage is generated from a power supply of, for example, 5 V or 12 V in the computer, and is inserted or removed in a live state or from the motherboard. , The rush current to the output capacitor can be suppressed in response to the ON / OFF signal.

Further, the information processing apparatus of the present invention uses any one of the above-mentioned stabilized power supply circuits as described above.

Therefore, since a sub-board or a mother board on which each of the above-mentioned stabilized power supply circuits is mounted is used, insertion / removal of the board in the live state and ON / OFF for power saving are performed.
When the switch is turned off, the rush current to the output capacitor can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a stabilized power supply circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of an overcurrent protection circuit and an input monitoring circuit in the stabilized power supply circuit shown in FIG.

FIG. 3 is a block diagram showing an electrical configuration of a stabilized power supply circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing an electrical configuration of a stabilized power supply circuit according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing an electrical configuration of a stabilized power supply circuit according to a fourth embodiment of the present invention.

FIG. 6 is a block diagram illustrating an electrical configuration of a stabilized power supply circuit according to a fifth embodiment of the present invention.

FIG. 7 is a block diagram illustrating an electrical configuration of a stabilized power supply circuit according to a sixth embodiment of the present invention.

FIG. 8 is a block diagram showing an electrical configuration of a stabilized power supply circuit according to a seventh embodiment of the present invention.

FIG. 9 is a block diagram showing an electrical configuration of an information processing apparatus using a computer sub-board on which any of the above-described stabilized power supply circuits is mounted.

FIG. 10 is a block diagram showing the electrical configuration of a typical prior art stabilized power supply circuit.

11 is a waveform chart showing output on / off characteristics of the stabilized power supply circuit shown in FIG.

12 is a waveform chart showing the rise of the stabilized power supply circuit shown in FIG. 10, that is, characteristics at the time of power-on.

[Explanation of symbols]

11, 31, 41, 51, 61, 71, 81 Stabilized power supply circuit 12 Power supply 13 Load 14 Power supply line 15, 55 Control circuit 16, 20, 63 Comparator 17 Reference voltage generation circuit 18 Overcurrent protection circuit 19, 49, 59 , 89 input monitoring circuit 62 reset signal generation circuit 90 information processing device 91 sub-board 92 motherboard 93 power supply 94, 95 power supply line 96 hard disk drive 97 CD-ROM drive C1 output capacitor C2 external capacitor D diode F1, F2 constant current source Q1 , Q2, Q3, Q4, Q5, Q7 Control transistor Q6 Output transistor R1, R2, R7, R8 Voltage dividing resistor R3; R3a, R3b; R4 Current detecting resistor R5, R6 Input voltage dividing resistor T0 External terminal T1, T3 External input terminal T2 External output terminal TR 1, TR2 output transistor

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kenji Masui 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (72) Inventor Yasuhisa Nakazawa 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Sharp Incorporated (72) Inventor Mitsuru Hosoki 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Sharp Corporation (72) Inventor Tomohiro Shimizu 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Sharp Corporation F Terms (reference) 5H420 BB12 CC02 DD02 EA11 EA39 EA47 EB18 EB37 FF03 FF04 FF21 FF22 FF25 LL05

Claims (13)

[Claims] An operation is performed at an overcurrent protection value lower than a normal overcurrent protection value for a period shorter than a reset operation period of a load-side circuit in response to a rise of an input power supply. A stabilized power supply circuit that operates with an overcurrent protection value. 2. An output voltage stabilized to a desired voltage by a control circuit controlling a base current of an output transistor interposed in series on a power supply line from a power supply to a load in accordance with the output voltage. A stabilized power supply circuit that suppresses the base current at the time of an overcurrent; and wherein the overcurrent protection circuit responds to a rise of an input power supply from a reset operation period of a load-side circuit. An input monitoring circuit that operates at an overcurrent protection value lower than a normal overcurrent protection value for only a short period, and operates at the normal overcurrent protection value after the period has elapsed. circuit. 3. An apparatus according to claim 1, wherein the circuit operates in response to switching of the output from off to on with an overcurrent protection value lower than a normal overcurrent protection value for a period shorter than a reset operation period of the load-side circuit.
A stabilized power supply circuit that operates at the normal overcurrent protection value after the period has elapsed. 4. An output voltage stabilized to a desired voltage by a control circuit controlling a base current of an output transistor interposed in series with a power supply line from a power supply to a load in accordance with the output voltage. In the stabilized power supply circuit, an overcurrent protection circuit that suppresses the base current when an overcurrent occurs, and an overcurrent protection circuit that responds to an external on / off signal to change the output from off to on At the time of switching, the operation is performed with an overcurrent protection value lower than the normal overcurrent protection value for a period shorter than the reset operation period of the load side circuit, and after the period elapses, the operation is performed with the normal overcurrent protection value. And a current protection value switching means. 5. The method according to claim 1, wherein the period is based on an amount of charge to be stored in the output capacitor determined by a capacitance and an output voltage of the output capacitor, and an overcurrent protection value lower than the normal overcurrent protection value. The stabilized power supply circuit according to any one of claims 1 to 4, wherein the power supply period is set to be longer than a charging period of the output capacitor determined as follows. 6. The stabilized power supply circuit according to claim 1, wherein the period is determined by a charging time of an external capacitor. 7. The stabilized power supply circuit according to claim 6, further comprising first discharging means for discharging the electric charge of said external capacitor when power is turned on. 8. The stabilized power supply circuit according to claim 6, further comprising second discharging means for discharging the electric charge of said external capacitor in response to an external signal. 9. The overcurrent protection circuit detects a base current of the output transistor, and comprises at least a plurality of n current detection resistors arranged in parallel with each other, and at least one of the plurality of current detection resistors. 9. The semiconductor device according to claim 2, further comprising a control transistor connected in series with each of the n-1 current detection resistors, and a switching unit for selectively switching the control transistor.
The stabilized power supply circuit according to any one of the above. 10. The output transistor is a multi-collector transistor, wherein the overcurrent protection circuit detects a collector current of a part of the output transistor, and includes a plurality of n current detection resistors arranged in parallel with each other. A control transistor connected in series with at least n-1 current detection resistors of the plurality of current detection resistors, and switching means for selectively switching the control transistors. 9. The method according to claim 2, wherein:
The stabilized power supply circuit according to any one of the above. 11. A circuit according to claim 1, further comprising a reset signal generating circuit for outputting a reset signal when at least one of an input voltage and an output voltage of said stabilized power supply circuit decreases. 3. The stabilized power supply circuit according to 1. 12. A sub board for a computer, comprising the stabilized power supply circuit according to claim 1. 13. An information processing apparatus using the stabilized power supply circuit according to claim 1. Description: