CN219916685U

CN219916685U - Power supply time sequence control circuit and display device

Info

Publication number: CN219916685U
Application number: CN202321043897.7U
Authority: CN
Inventors: 杨国清; 毕宗义; 李献超
Original assignee: Hisense Visual Technology Co Ltd
Current assignee: Hisense Visual Technology Co Ltd
Priority date: 2023-04-28
Filing date: 2023-04-28
Publication date: 2023-10-27
Anticipated expiration: 2033-04-28

Abstract

The application provides a power supply time sequence control circuit and display equipment, and belongs to the time sequence control technology. The power supply timing control circuit includes: the power supply system comprises a first power supply module, a first power-down time sequence control module, N second power supply modules, a first power-down detection module, a second power-down time sequence control module and a power-down module, wherein the second power-down time sequence control module corresponds to each second power supply module; the power-down detection module is used for detecting whether the first power supply module starts to be powered down or not, and controlling the second power-down time sequence control module to conduct a power-down path of the corresponding power-down module when the first power supply module is detected to start to be powered down so as to enable the power-down module to discharge the second power supply module; the first power-down time sequence control module is used for controlling the power-down speed of the corresponding first power module, and the second power-down time sequence control module is used for controlling the power-down speed of the corresponding second power module so that the second power module finishes power-down earlier than the first power module. The application can avoid the problem of current backflow in the power-down process of the main board.

Description

Power supply time sequence control circuit and display device

Technical Field

The embodiment of the application relates to a time sequence control technology. And more particularly, to a power supply timing control circuit and a display device.

Background

In the process of powering up or powering down a main board of the display device, different components on the main board often need to be correspondingly powered up or powered down according to a certain time sequence relationship, otherwise, the problems of damage of the components on the main board and the like may occur. For example, in some tv motherboards, when the motherboard is powered on, a main control chip on the motherboard needs to be powered on before a memory corresponding to the main control chip.

At present, for a component on a motherboard, the power-on and power-off time sequence of the component is controlled by the same power time sequence control circuit, for example, a power module on the power time sequence control circuit is used for controlling the corresponding component to supply power to the component when the motherboard is powered on, and discharging the component when the motherboard is powered off. However, this method cannot simultaneously take the power-on and power-off time sequences into consideration, so that the problem that current flows backward when the main board is powered off while the power-on of the components on the main board is ensured according to the preset time sequence, and the components on the main board are damaged.

Disclosure of Invention

The utility model provides a power supply time sequence control circuit and display equipment, which are used for solving the problem of current backflow in the power-down time sequence control process of a main board in the prior art.

In a first aspect, the present application provides a power supply timing control circuit comprising: the power-down detection device comprises a first power supply module, a first power-down time sequence control module, N second power supply modules, a power-down detection module, a second power-down time sequence control module and a power-down module, wherein the second power-down time sequence control module corresponds to each second power supply module;

the first power supply module is respectively connected with the first end of the power-down detection module and the first end of the first power-down time sequence control module, the second end of the first power-down time sequence control module is grounded, the second end of the power-down detection module is connected with the first end of each second power-down time sequence control module, the second end of the second power-down time sequence control module is connected with one end of a corresponding power-down module, the second end of the power-down module is connected with the first end of the corresponding second power supply module and/or the third end of the power-down module is connected with the second end of the corresponding second power supply module, and the fourth end of the power-down module is grounded;

the power-down detection module is used for detecting whether the first power supply module starts to power down, and controlling the second power-down time sequence control module to conduct a power-down path of the corresponding power-down module when detecting that the first power supply module starts to power down so as to enable the power-down module to discharge the second power supply module;

The first power-down time sequence control module is used for controlling the power-down speed of the corresponding first power module, and the second power-down time sequence control module is used for controlling the power-down speed of the corresponding second power module so that the second power module finishes power-down earlier than the first power module.

Optionally, the power failure detection module includes: a power down detection sub-module and a switch sub-module; the first end of the power-down detection sub-module is the first end of the power-down detection module, the second end of the power-down detection sub-module is connected with the first end of the switch sub-module, the third end of the power-down detection sub-module is connected with the second end of the switch sub-module, and the third end of the switch sub-module is the second end of the power-down detection module;

the power-down detection sub-module is used for detecting whether the first power supply module starts to be powered down or not, and controlling the switch sub-module to be turned on when the first power supply module is detected to start to be powered down, so that the second power-down time sequence control module is controlled through the switch sub-module.

Optionally, the power failure detection sub-module includes: the first switch, at least one first energy storage element, a first resistor, a second resistor and a third resistor;

The first end of the first resistor is connected with the first end of the first switch and the first end of the second resistor respectively;

the second end of the first switch is connected with the first end of the third resistor, the second end of the third resistor is grounded, and the first energy storage element is connected in parallel with the two ends of the third resistor;

the second end of the first resistor is the second end of the power failure detection sub-module; the second end of the first switch is a third end of the power failure detection sub-module.

Optionally, the power failure detection sub-module further includes a fourth resistor and/or a fifth resistor;

the first end of the fourth resistor is the first end of the power failure detection submodule, the second end of the fourth resistor is respectively connected with the third end of the first switch, the second end of the second resistor and the first end of the fifth resistor, and the second end of the fifth resistor is grounded.

Optionally, the switch submodule includes: a second switch, a sixth resistor and a seventh resistor;

the third end of the second switch is connected with the first end of the sixth resistor, the second end of the sixth resistor is connected with the first end of the seventh resistor, and the second end of the seventh resistor is grounded;

The first end of the second switch is the first end of the switch sub-module, the second end of the second switch is the second end of the switch sub-module, and the second end of the sixth resistor is the third end of the switch sub-module.

Optionally, the first power-down timing control module includes: at least one second energy storage element connected in parallel.

Optionally, the second power-down timing control module includes: an eighth resistor, a ninth resistor and a first capacitor;

the first end of the eighth resistor is the first end of the second power-down time sequence control module, and the second end of the eighth resistor is the second end of the second power-down time sequence control module;

the second end of the eighth resistor is respectively connected with the first end of the ninth resistor and the first end of the first capacitor, and the second end of the ninth resistor and the second end of the first capacitor are grounded.

Optionally, the power-down module includes: a third switch, a tenth resistor, an eleventh resistor and a diode;

the first end of the third switch is the first end of the power-down module, the second end of the third switch is connected with the first end of the tenth resistor and the first end of the eleventh resistor respectively, the second end of the eleventh resistor is connected with the first end of the diode, the second end of the tenth resistor is the second end of the power-down module, the second end of the diode is the third end of the power-down module, and the third end of the third switch is the fourth end of the power-down module.

Optionally, the power supply timing control module further includes: a power-on time sequence control module;

the first power supply module is connected with the first end of the power-on time sequence control module, and the second end of the power-on time sequence control module is connected with the first end of the second power supply module;

and the power-on time sequence control module is used for controlling the power-on speed of the corresponding second power module when the first power module is detected to start power-on, so that the second power module is later than the first power module to finish power-on.

In a second aspect, the present application provides a display device comprising the power supply timing control circuit according to any one of the first aspects.

According to the power supply time sequence control circuit and the display device, on one hand, when the first power supply module is powered down, the second power supply module is controlled to finish discharging earlier than the first power supply module, so that the problem of current reverse pouring is avoided, and the voltage conversion controller and other components in the second power supply module are damaged. On the other hand, the power supply time sequence control circuit provided by the embodiment of the application can realize the multi-stage control of a plurality of second power supply modules and corresponding components, namely, the control of the power supply time sequence of the plurality of second power supply modules can be realized by connecting the plurality of second power supply time sequence control modules and the power supply modules corresponding to the second power supply modules in parallel, so that the application scene of the power supply time sequence control circuit provided by the application is enlarged, and various use requirements can be better met.

Drawings

In order to more clearly illustrate the embodiments of the present application or the implementation in the related art, the drawings that are required to be used in the embodiments or the related art description will be briefly described, and it is apparent that the drawings in the following description are some embodiments of the present application and that other drawings may be obtained according to these drawings for one of ordinary skill in the art.

FIG. 1 is a schematic diagram of a power timing control circuit according to the prior art;

FIG. 2 is a schematic diagram of another power timing control circuit according to the prior art;

FIG. 3 is a schematic diagram of a first power timing control circuit according to the present application;

FIG. 4 is a schematic diagram of a second power timing control circuit according to the present application;

FIG. 5 is a schematic diagram of a third power timing control circuit according to the present application;

FIG. 6 is a schematic diagram of a fourth power timing control circuit according to the present application;

FIG. 7 is a schematic diagram of a fifth power timing control circuit according to the present application;

FIG. 8 is a schematic diagram of a sixth power timing control circuit according to the present application;

FIG. 9 is a schematic diagram of a seventh power timing control circuit according to the present application;

FIG. 10 is a schematic diagram of an eighth power timing control circuit according to the present application;

FIG. 11 is a schematic diagram of a ninth power timing control circuit according to the present application;

FIG. 12 is a schematic diagram of a tenth power timing control circuit according to the present application;

FIG. 13 is a schematic diagram of a power down timing of a power timing control module according to the present application;

fig. 14 is a schematic diagram of an eleventh power timing control circuit according to the present application.

Detailed Description

For the purposes of making the objects, embodiments and advantages of the present application more apparent, an exemplary embodiment of the present application will be described more fully hereinafter with reference to the accompanying drawings in which exemplary embodiments of the application are shown, it being understood that the exemplary embodiments described are merely some, but not all, of the examples of the application.

It should be noted that the brief description of the terminology in the present application is for the purpose of facilitating understanding of the embodiments described below only and is not intended to limit the embodiments of the present application. Unless otherwise indicated, these terms should be construed in their ordinary and customary meaning.

Furthermore, the terms "comprise" and "have," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a product or apparatus that comprises a list of elements is not necessarily limited to those elements expressly listed, but may include other elements not expressly listed or inherent to such product or apparatus.

The following explains some of the terms related to the present application:

current backflow: that is, a phenomenon in which current flows backward from one end of an output current to one end of an input current in a circuit. When current back-flow occurs, damage to components in the circuit will result.

In a main board of a display device (for example, a television), a main control chip, a frame rate conversion (Frame Rate Conversion, FRC) chip, a low-power double data rate memory (Low Power Double Data Rate SDRAM, LPDDR) and other components are generally included. The working voltages required by different components are often different, so that a power supply module is arranged on the main board and used for converting fixed direct-current voltage into different working voltages so as to supply power for the corresponding components. The power supply module can realize voltage conversion through a built-in voltage conversion controller.

In addition to the different required operating voltages, specific requirements often exist for power up and power down timing of the different components on the motherboard. For example, in some motherboard circuits, when the motherboard is powered on, the main control chip needs to be powered on first, and then the LPDDR needs to be powered on to ensure normal operation of the components.

At present, aiming at a component on a main board, the main board realizes the power-on and power-off time sequence control of the component through the same power time sequence control circuit. The power supply time sequence control circuit comprises a power supply module, and when the main board is electrified, the power supply time sequence control circuit controls the power supply module to be electrified, so that components connected with the power supply module are controlled to be electrified according to a certain time sequence when the main board is electrified; when the main board is powered down, the power supply time sequence control circuit controls the power supply module to discharge, and then controls components connected with the power supply module to be powered down according to a certain time sequence when the main board is powered down.

In the following, a power supply time sequence control circuit in the prior art is taken as an example to explain how to realize power-on and power-off time sequence control of different components in a main board in the prior art. The power supply time sequence control circuit comprises a time sequence control module A, a time sequence control module B, a power supply module C and a power supply module D. Fig. 1 is a schematic diagram of a power timing control circuit provided in the prior art, as shown in fig. 1, where a power module D is connected to a timing control module a shown in fig. 1, and is a module for outputting a voltage to be converted (12V voltage shown in fig. 1), for example, a power board. Note that fig. 1 is a schematic diagram showing only the power supply module a, the timing control module B, and the power supply module C, as an example, without showing the power supply module D.

The end A of the time sequence control module is connected with the power supply module D to obtain the power supply voltage of the main board, namely the voltage to be converted; the B end of the power module C is used for connecting corresponding components so as to output the working voltage of the corresponding components obtained after the conversion of the built-in voltage conversion controller N1 to the components. The time sequence control module A and the time sequence control module B are used for controlling the power-on and power-off time of the power supply module C, so that the power-on and power-off time sequence control of corresponding components is realized.

Specifically, when the motherboard is powered on, the Standby terminal obtains a power-on signal of the display device (for example, the Standby terminal may be a voltage signal that can enable the EN pin of the voltage conversion controller N1 in the power module C to reach a preset voltage threshold). After the startup signal is acquired, the time sequence control module B controls the voltage of the EN pin to reach a preset voltage threshold after a certain time by adjusting the internal resistance value and the capacitance. Further, the voltage control converter N1 enters a working state, the power module C starts to power up, and the power module C converts the motherboard voltage obtained at the a end of the time sequence control module into a working voltage of a corresponding component through the voltage control converter N1 and outputs the working voltage to the component, so that the corresponding component is powered up to work.

When the main board is powered down, the end A and the Standby end of the timing control module A start to be powered down, and correspondingly, the voltage of the EN pin of the voltage controller N1 of the power supply module C is gradually reduced under the control of the timing control module B. When the voltage value of the EN pin is lower than the preset voltage threshold, the voltage control converter N1 stops working, the power module C starts to be powered down, and correspondingly, the components start to be powered down. The timing control module A controls the power-down speed of the end A, namely, the larger the total energy storage energy of all the capacitors connected in parallel in the timing control module A is, the slower the power-down speed of the end A is.

Because the power-on and power-off time sequence is controlled by the power time sequence control circuit in the prior art, the circuit structure, the resistance and the capacitance of the power time sequence control module B are the same during power-on and power-off, the power-on speed and the power-off speed of the EN pin are always positively correlated, namely the power-on speed and the power-off speed of the components controlled by the power module are always consistent.

However, in some motherboards, different settings are often required for the power-on timing and the power-off timing of the components, so the above method for performing power-on and power-off timing control by using one power timing control circuit may not be capable of achieving both power-on and power-off timing control of the components in the motherboard.

In addition, with continued reference to fig. 1, in some scenarios, in order to ensure the power-on timing of the power module C, and further ensure the power-on timing of the connected components, it may be often necessary to connect a plurality of energy storage elements such as capacitors in parallel to the B-end of the power module C, so as to prolong the power-on time of the power module C. However, the longer power-down time of the B terminal caused by the more parallel capacitors may cause that the B terminal of the power module C is not powered down after the a terminal of the timing control module a is powered down, which may cause the current backflow problem to burn out various components such as the voltage conversion controller N1 in the circuit.

Furthermore, based on the power supply time sequence control circuit, a plurality of different components are required to be powered on and powered off through the plurality of different power supply time sequence control circuits, so that the power on and the power off of the different components on the main board are realized according to different time sequence sequences. The differences of the power supply time sequence control circuits are mainly reflected in the differences of the resistance and the capacitance in the time sequence control module B. The power supply time sequence control mode is complex in circuit deployment, inconvenient to operate and high in cost.

Fig. 2 is a schematic diagram of another power timing control circuit provided in the prior art, where the power timing control circuit includes a timing control module E, a timing control module F, a power module G, and a power module H, and fig. 2 is a schematic diagram illustrating only the timing control module E, the timing control module F, and the power module G as examples.

The first end of the power module H is connected to the VIN end of the timing control module F, and is configured to output a voltage to be converted to the power module G through the timing control module F, so that the input voltage is converted into a working voltage required by a component connected to the power module G through the power module G.

The VDD1 end of the timing control module E is connected to the VDD2 end of the power module G of the power timing control circuit corresponding to the component that is powered on first. The VDD2 terminal of the power supply module G of each power supply timing control circuit is connected to the corresponding component, and the VDD1 terminal of the timing control module of the power supply timing control circuit corresponding to the next component to be powered on.

When the main board is powered on, the power module G of the power timing control circuit corresponding to the component needing to be powered on first is powered on first, so that the component needing to be powered on first is powered on. Meanwhile, the power module G of the power timing control circuit corresponding to the component needing to be powered on first is connected with the timing control module D of the power timing control circuit corresponding to the component needing to be powered on later, so that the timing control module D is powered on, and controls the EN pin voltage of the voltage control converter N2 of the power module G to reach a preset voltage threshold after a certain time, and the voltage conversion controller N2 starts to work. Then, the power module G converts the power supply acquired at the Vin end of the timing control module E into a working voltage of a corresponding component by using the voltage conversion controller N2, and outputs the working voltage from the VDD2 end to the component that needs to be powered on. That is, the power supply time sequence control module controls the power-on of the components needing to be powered on later through the working voltage of the components needing to be powered on first.

When the main board is powered down, the power module G corresponding to the first-powered-up component is powered down first, so that the timing control module D corresponding to the first-powered-up component and the last-powered-up component connected with the power module G is powered down. Further, the power module G corresponding to the rear power-on component is powered down, so that the rear power-on component is powered down. That is, the power-up and power-down sequences of the components controlled by the power supply timing control circuit shown in fig. 2 are often the same. In addition, when the power-on time of the VDD2 terminal of the power module G needs to be prolonged, a plurality of capacitors need to be connected in parallel to the VDD2 terminal. However, when the power is turned off, the more the number of capacitors at the VDD2 end is, the slower the power-off speed of the VDD2 end is, which makes it more likely that the power module G corresponding to the component that is powered on later than the power module G corresponding to the component that is powered on earlier, that is, the VDD2 end is powered off later than the VDD1 end, which causes a problem of current backflow and damages the circuit.

The inventor considers that if the power supply time sequence control circuit during power-on and the power supply time sequence control circuit during power-off can be isolated, so that the power supply time sequence control circuit during power-off is not influenced by the power supply time sequence control circuit during power-on, the voltage output after conversion by the voltage conversion controller during power-off can be ensured to be earlier than the input voltage power-off, the current backflow problem can be avoided, and the circuit is protected.

In view of this, the present application provides a power supply timing control circuit, which is applied to timing control during power-down, and is not affected by the power supply timing control circuit during power-up, so that when the motherboard is powered down, the voltage output after conversion by the voltage conversion controller can be earlier than the input voltage before conversion, and the current backflow problem is avoided. In addition, the power supply time sequence control circuit provided by the application can simultaneously realize power failure time sequence control of working voltages corresponding to a plurality of different components, is simple and convenient to deploy, and expands application scenes.

It should be understood that the power supply time sequence control circuit provided by the application can be applied to power supply time sequence control of internal components when the main board is powered down; the method can also be applied to power supply time sequence control of internal components when other equipment is powered down. The application is not limited to the specific application scenario of the power supply time sequence control circuit, and can be applied by a person skilled in the art according to actual situations.

The technical scheme of the present application will be described in detail with reference to specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.

Fig. 3 is a schematic diagram of a first power timing control circuit according to the present application, as shown in fig. 3, the power timing control circuit includes: the power supply system comprises a first power supply module 1, a first power-down time sequence control module 2, N second power supply modules 3, a first power-down detection module 4, a second power-down time sequence control module 5 and a power-down module 6, wherein the second power-down time sequence control module 5 corresponds to each second power supply module 3. Wherein N is an integer greater than or equal to 1.

The connection relation of the internal modules of the power supply time sequence control circuit is as follows:

the first power module 1 is respectively connected with a first end of the power-down detection module 4 and a first end of the first power-down time sequence control module 2, a second end of the first power-down time sequence control module 2 is grounded, a second end of the power-down detection module 4 is connected with a first end of each second power-down time sequence control module 5, a second end of the second power-down time sequence control module 5 is connected with one end of a corresponding power-down module 6, a second end of the power-down module 6 is connected with a first end of the corresponding second power module 3 and/or a third end of the power-down module 6 is connected with a second end of the corresponding second power module 3, and a third end of the power-down module 6 is grounded.

The configuration of the first power module 1 is related to the application scenario of the power timing control circuit provided by the application. For example, if the power supply timing control circuit provided by the present application is applied to power supply timing control of a motherboard, the first power supply module 1 may be, for example, a power panel; if the power timing control circuit provided by the application is applied to the power timing control of the power panel of the display device, the first power module 1 may be, for example, a power supply of the display device. In particular, the present application is not limited to a specific circuit structure of the first power module 1, and a voltage value output by the first power module 1 may be designed and determined by a person skilled in the art according to practical situations. For example, if the present application is applied to power timing control of a display device motherboard, the voltage value of the first power module 1 may be 12V, for example.

The N second power modules 3 are respectively connected with N corresponding components needing power-down time sequence control, and are simultaneously used for converting the voltage directly output by the first power module 1 to the second power module 3 into the working voltage required by the connected components when power is on, and outputting the working voltage to the components for working. The second power module 3 may, for example, include a voltage conversion controller, that is, the second power module 3 may convert the voltage output from the first power module 1 to the second power module 3 into an operating voltage of a component corresponding to the second power module 3 through the voltage conversion controller. It should be understood that, on the basis of the power timing control circuit provided by the present application, the present application is not limited to whether there are other connection relationships between the first power module 1 and the N second power modules 3, and those skilled in the art can set the connection relationships according to actual situations.

The power failure detection module 4 is described in detail below:

the power-down detection module 4 is configured to detect whether the first power module 1 starts to power down, and when detecting that the first power module 1 starts to power down, control the second power-down timing control module 5 to conduct a power-down path of the corresponding power-down module 6, so that the power-down module 6 discharges the second power module 3.

It should be understood that, since the first power module 1 is connected to the power-down detection module 4, when the first power module 1 is powered down, the power-down detection module 4 also starts to power down, so as to realize detection on whether the first power module 1 starts to power down.

Fig. 4 is a schematic diagram of a second power timing control circuit according to the present application, where the power timing control circuit includes only one second power module 3, and a corresponding second power-down timing control module 5 and a power-down module 6, as shown in fig. 4, in some embodiments, the power-down detection module 4 may include: a power down detection sub-module 41 and a switch sub-module 42.

With continued reference to fig. 4, at this time, the internal connection relationship of the power failure detection module 4 may be, for example:

the first end of the power-down detection sub-module 41 is the first end of the power-down detection module 4, the second end of the power-down detection sub-module 41 is connected with the first end of the switch sub-module 42, the third end of the power-down detection sub-module 41 is connected with the second end of the switch sub-module 42, and the third end of the switch sub-module 42 is the second end of the power-down detection module 4.

The power-down detection sub-module 41 is configured to detect whether the first power module 1 starts to power down, and when detecting that the first power module 1 starts to power down, control the switch sub-module 42 to be turned on, so as to control the second power-down timing control module 5 through the switch sub-module 42.

It should be understood that, since the first power module 1 is connected to the power-down detection sub-module 41, when the first power module 1 is powered down, the power-down detection sub-module 41 also starts to power down, so as to realize detection of whether the first power module 1 starts to power down. Since the switch sub-module 42 is connected with the second power-down timing control module 5, the second power-down timing control module 5 can be controlled by the switch sub-module 42.

The power failure detection sub-module 41 is exemplarily described below.

Fig. 5 is a schematic diagram of a third power timing control circuit according to the present application, as shown in fig. 5, in some embodiments, the power-down detection sub-module 41 may include: the first switch V1, at least one first energy storage element P1, a first resistor R1, a second resistor R2 and a third resistor R3.

With continued reference to fig. 5, at this time, the internal connection manner of the power failure detection sub-module 41 may be, for example:

the first end of the first resistor R1 is respectively connected with the first end of the first switch V1 and the first end of the second resistor R2; the second end of the first switch V1 is connected with the first end of the third resistor R3, the second end of the third resistor R3 is grounded, and the first energy storage element P1 is connected in parallel with the two ends of the third resistor R3; the second end of the first resistor R1 is the second end of the power-down detection sub-module 41; the third terminal of the first switch V1 is the third terminal of the power-down detection sub-module 41.

The first switch V1 is used for controlling current flow and performing voltage stabilizing function. In some embodiments, the first switch V1 may be a bidirectional diode, and it should be understood that fig. 5 is a schematic diagram illustrating the first switch V1 as a bidirectional diode. Alternatively, in some embodiments, the first switch V1 may include two diodes connected in anti-parallel, respectively, a first diode and a second diode, where a first end of the first diode is connected to a first end of the third resistor R3, a second end of the second diode is connected to a first end of the first resistor R1, and a second end of the first diode and a first end of the second diode are third ends of the power-down detection sub-module 41.

The first resistor R1, the second resistor R2, and the third resistor R3 are current limiting voltage dividing resistors for controlling the voltage division of the switch sub-module 42. By way of example, with continued reference to fig. 5, the voltage at the first end of the switch sub-module 42 may be controlled by adjusting the magnitudes of the resistances of the first resistor R1 and the second resistor R2; by adjusting the resistance of the third resistor R3 and the size of the first energy storage element P1, the voltage of the second end of the switch sub-module 42 can be controlled. Illustratively, since the voltage value output by the first power module 1 is fixed, the voltage of the first terminal of the switch sub-module 42 may be reduced by increasing the voltage divided by the first resistor R1 and the second resistor R2 by increasing the resistance values of the first resistor R1 and the second resistor R2.

The first energy storage element P1 may be, for example, a capacitor. The number of first energy storage elements P1 connected in parallel with the third resistor R3 and the total energy storage capacity of all energy storage elements are related to the conduction condition of the switch sub-module 42.

For example, when the first power module 1 is in the power-on or continuous power-on state, the power-down detection sub-module 41 controls the voltage of the first end of the switch sub-module 42 through the first resistor R1 and the second resistor R2, and controls the voltage of the second end of the switch sub-module 42 through the third resistor R3 and the first energy storage element P1, so that the voltage of the second end of the switch sub-module 42 and the voltage difference of the first end of the switch sub-module 42 cannot reach the conduction condition of the switch sub-module 42, and further the switch sub-module 42 cannot be turned on.

When the first power module 1 is powered down, the voltage at the first end of the switch sub-module 42 drops rapidly. However, since the first energy storage element P1 starts to discharge after the first power module 1 is powered down, the voltage at the second end of the switch sub-module 42 drops at a slower rate than the voltage at the first end of the switch sub-module 42. Thus, during power down, the voltage difference between the second and first ends of the switch sub-module 42 gradually increases over time until the voltage difference reaches the voltage difference required for the switch sub-module 42 to turn on, and the switch sub-module 42 turns on. At this time, the second power-down timing control module 5 connected to the switch sub-module 42 can be controlled by the on state of the switch sub-module.

In some embodiments, the power down detection sub-module 41 may further include a fourth resistor R4 and/or a fifth resistor R5.

With continued reference to fig. 5, when the power-down detection sub-module 41 includes the fourth resistor R4 and the fifth resistor R5, the internal connection relationship of the power-down detection sub-module 41 may be, for example:

the first end of the fourth resistor R4 is the first end of the power failure detection submodule 41, the second end of the fourth resistor R4 is respectively connected with the third end of the first switch V1, the second end of the second resistor R2 and the first end of the fifth resistor R5, and the second end of the fifth resistor R5 is grounded.

The fourth resistor R4 and the fifth resistor R5 are current-limiting voltage-dividing resistors, wherein the fourth resistor R4 is used for controlling the voltage division between the first end and the second end of the switch sub-module 42, and the fifth resistor R5 is used for controlling the voltage of the first end of the switch sub-module 42. For example, in the above connection manner, the voltage division at the first end of the switch sub-module 42 may be controlled by adjusting the resistance values of the first resistor R1, the second resistor R2, the fourth resistor R4 and the fifth resistor R5, and the voltage division at the second end of the switch sub-module 42 may be controlled by adjusting the resistance values of the third resistor R3 and the fourth resistor R4 and the first energy storage element P1.

With continued reference to fig. 5, in some embodiments, the power failure detection submodule 41 may further include a fourth capacitor C4, where a first end of the fourth capacitor C4 is connected to a first end of the second resistor R2, a first end of the first resistor R1, and a first end of the first switch V1, and a second end of the fourth capacitor C4 is connected to a second end of the second capacitor, a second end of the third capacitor C3, and a second end of the third resistor R3. Since a certain time is required for charging the fourth capacitor C4 during power-up, the power-up time of the first end of the switch sub-module 42 can be prolonged by adding the fourth capacitor C4; when power is lost, the fourth capacitor C4 will discharge, so that the power-down time of the first end of the switch sub-module 42 connected thereto is prolonged. Specifically, a person skilled in the art can choose whether to add the fourth capacitor C4 according to the actual requirement.

The switch sub-module 42 is described in detail below.

Fig. 6 is a schematic diagram of a fourth power timing control circuit according to the present application, as shown in fig. 6, and in some embodiments, the switch sub-module 42 may include: a second switch V2, a sixth resistor R6 and a seventh resistor R7.

With continued reference to fig. 6, at this time, the internal connection manner of the switch sub-module 42 may be, for example:

The third end of the second switch V2 is connected with the first end of a sixth resistor R6, the second end of the sixth resistor R6 is connected with the first end of a seventh resistor R7, and the second end of the seventh resistor R7 is grounded; the first end of the second switch V2 is the first end of the switch sub-module 42, the second end of the second switch V2 is the second end of the switch sub-module 42, and the second end of the sixth resistor R6 is the third end of the switch sub-module 42.

The second switch V2 is configured to be turned on when the power-down detection module 4 detects that the first power module 1 is powered down, and control the second power-down timing control module 5. The second switch V2 may be, for example, a P-type transistor or a P-type Metal-Oxide-Semiconductor Field-Effect Transistor (MOS) transistor, and it should be understood that fig. 6 is a schematic diagram of the second switch V2 as an example of a P-type transistor. When the second switch V2 is a P-type transistor, the base of the transistor may be, for example, a first terminal of the second switch V2, the emitter may be, for example, a second terminal of the second switch V2, and the collector may be, for example, a third terminal of the second switch V2. It should be understood that, when the second switch V2 is another component, reference may be made to a connection manner when the second switch V2 is a P-type transistor, which is not described herein. The sixth resistor R6 and the seventh resistor R7 are current limiting protection resistors, and the present application is not limited to specific values of the two resistors, and may be determined by those skilled in the art according to practical situations.

With continued reference to fig. 6, in this implementation, when the first power module 1 is in a powered-up or continuously powered state, the power-down detection sub-module 41 connected thereto is also in a powered-up or continuously powered state. At this time, the power failure detection sub-module 41 controls the voltage value of the first end of the second switch V2 and the voltage value of the second end of the second switch V2, so that the voltage difference between the second end and the first end of the second switch V2 cannot reach the voltage difference that can turn on the second switch V2, and the second switch V2 is in the off state. Taking the connection manner shown in fig. 5 as an example of the power failure detection submodule 41, the power failure detection submodule 41 can control the voltage value of the first end of the second switch V2 through the first resistor R1, the second resistor R2, the fourth resistor R4 and the fifth resistor R5, and can control the voltage value of the second end of the second switch V2 through the third resistor R3, the fourth resistor R4 and the first energy storage element P1. Since the second switch V2 is in the off state, the second power-down timing control module 5 is also in the off state under the control of the second switch V2 in the switch sub-module 42.

When the first power supply module 1 is powered down, the power-down detection sub-module 41 connected thereto also starts to be powered down. At this time, the power-down speed of the first end of the second switch V2 and the power-down speed of the first power module 1 remain identical. However, since the first energy storage element P1 is connected to the second end of the second switch V2, the first energy storage element P1 starts to discharge to the second end of the second switch V2 when the first power module 1 is powered down, which makes the power-down speed of the second end of the second switch V2 slower than that of the first end. As the power-down time passes, the voltage difference between the second terminal voltage and the first terminal of the second switch V2 gradually expands until the voltage difference required for turning on the second switch V2 is reached. At this time, the second switch V2 is turned on. Under the control of the second switch V2, the second power-down timing control module 5 turns on a power-down path of the corresponding power-down module 6, so that the power-down module 6 discharges the second power module 3, and further, components connected with the second power module 3 are powered down.

The power-down module 6 is configured to control the N second power modules 3 to power down under the control of the power-down detection module 4 and the second power-down timing control module 5 when the first power module 1 is powered down.

Based on the above, the power-down module 6 has at least the following 3 implementations:

implementation 1: the power down module 6 includes: a third switch V3, a tenth resistor R10, an eleventh resistor R11, and a diode VD.

Fig. 7 is a schematic diagram of a fifth power timing control circuit provided by the present application, as shown in fig. 7, in this case, the internal connection relationship of the power-down module 6 may be, for example:

the first end of the third switch V3 is the first end of the power-down module 6, the second end of the third switch V3 is connected with the first end of the tenth resistor R10 and the first end of the eleventh resistor R11 respectively, the second end of the eleventh resistor R11 is connected with the first end of the diode VD, the second end of the tenth resistor R10 is the second end of the power-down module 6, the second end of the diode VD is the third end of the power-down module 6, and the third end of the third switch V3 is the fourth end of the power-down module 6. Since the third end of the third switch V3 is grounded, in this implementation, the power-down module 6 includes two power-down paths, that is, a power-down path formed by the tenth resistor R10 and the third switch V3, and a power-down path formed by the eleventh resistor R11, the diode VD, and the third switch V3, respectively.

The third switch V3 is configured to control the power-down path of the power-down module 6 to be turned on under the control of the second power-down timing control module 5 when the first power module 1 is powered down. The third switch V3 may be, for example, an N-type transistor or an N-type MOS transistor, and it should be understood that fig. 7 is a schematic diagram taking the third switch V3 as an N-type transistor as an example, when the third switch V3 is an N-type transistor, a base electrode of the transistor may be, for example, a first terminal of the third switch V3, an emitter electrode may be, for example, a third terminal of the third switch V3, and a collector electrode may be, for example, a second terminal of the third switch V3. It should be understood that, when the third switch V3 is another component, reference may be made to a connection manner when the third switch V3 is a P-type triode, which is not described herein.

The second end of the tenth resistor R10 may be connected to, for example, an EN interface of the voltage control converter in the second power module 3, and the second end of the diode VD may be connected to, for example, a port through which the corresponding second power module 3 outputs the operating voltage of the corresponding component.

For example, when the first power module 1 is in the power-on or continuous power-on state, the power-down detection module 4 is in the off state, and under the control of the power-down detection module 4, the second power-down timing control module 5 controls the voltage at the first end of the third switch V3 of the power-down path of the power-down module 6 to be 0, so that the conduction condition of the third switch V3 cannot be satisfied, and then the third switch V3 is in the off state. Therefore, at this time, the power-down path formed by the tenth resistor R10 and the third switch V3, and the power-down path formed by the eleventh resistor R11, the diode VD, and the third switch V3 are all in a non-conductive state, and the power-down module 6 cannot control the second power module 3 to power down, and the second power module 3 is in a powered-up or continuously powered state.

When the first power supply module 1 is powered down, the power-down detection module 4 starts to be turned on, so that the second power-down time sequence control module 5 connected with the power-down detection module is powered up. Under the control of the second power-down timing control module 5, the voltage at the first end of the third switch V3 rises, and when the on voltage threshold of the third switch V3 is reached, the third switch V3 is turned on. Further, the power-down path formed by the tenth resistor R10 and the third switch V3, and the power-down path formed by the eleventh resistor R11, the diode VD, and the third switch V3 are turned on. At this time, the EN pin of the voltage conversion controller connected to the tenth resistor R10 starts to be powered down rapidly, so that the voltage of the EN pin is smaller than the preset voltage threshold, and the voltage conversion controller stops converting the voltage output by the first power module 1 into the working voltage of the component; meanwhile, the voltage output end of the second power supply module 3 connected with the diode VD also starts to be powered down rapidly, so that the rapid release of the stored power of the second power supply module 3 is realized.

Under the implementation mode, as two power-down paths exist, one power-down path can realize the rapid release of the voltage of the EN pin of the voltage conversion controller EN of the second power supply module 3, so that the voltage conversion controller can rapidly stop voltage conversion; the other can realize the quick release of electricity to the second power module 3 in, consequently, can be under the double-barrelled through above-mentioned mode, and then can realize the quick power down to the second power module 3 of realization that can be more quick after third switch V3 switches on for second power module 3 is as early as possible in first power module 1 power down, reduces the possibility that the current flows backward the problem and takes place.

Implementation 2: the power down module 6 only includes: a third switch V3, and a tenth resistor R10.

Fig. 8 is a schematic diagram of a sixth power timing control circuit provided by the present application, as shown in fig. 8, in this case, the internal connection relationship of the power-down module 6 may be, for example:

the first end of the third switch V3 is the first end of the power-down module 6, the second end of the third switch V3 is connected with the first end of the tenth resistor R10, the second end of the tenth resistor R10 is the second end of the power-down module 6, and the third end of the third switch V3 is the fourth end of the power-down module 6. In this implementation, the power-down module 6 includes 1 power-down path in total, that is, the power-down path formed by the tenth resistor R10 and the third switch V3. The specific power-down implementation may refer to the above implementation, and will not be described herein.

In this implementation manner, since the voltage of the EN pin of the voltage conversion controller of the second power module 3 can be rapidly released, the voltage conversion controller can rapidly stop the voltage conversion, so that the second power module 3 can be rapidly powered down, and the possibility of current backflow problem is reduced.

Implementation 3: the power down module 6 only includes: a third switch V3, an eleventh resistor R11, and a diode VD.

Fig. 9 is a schematic diagram of a seventh power timing control circuit provided by the present application, as shown in fig. 9, at this time, the internal connection relationship of the power-down module 6 may be, for example:

the first end of the third switch V3 is the first end of the power-down module 6, the second end of the third switch V3 is connected with the first end of the eleventh resistor R11, the second end of the eleventh resistor R11 is connected with the first end of the diode VD, the second end of the diode VD is the third end of the power-down module 6, and the third end of the third switch V3 is the fourth end of the power-down module 6. In this implementation, the power-down module 6 includes 1 power-down path in total, that is, a power-down path formed by the eleventh resistor R11, the diode VD, and the third switch V3. The specific implementation manner may refer to the first implementation manner, and will not be described herein.

In this implementation manner, since the release of the stored power of the second power module 3 can be quickly realized, the quick power-down of the second power module 3 can be realized, and the possibility of current backflow problem is reduced.

The first power-down time sequence control module 2 is used for controlling the power-down speed of the corresponding first power module 1, and the second power-down time sequence control module 5 is used for controlling the power-down speed of the corresponding second power module 3, so that the second power module 3 finishes power-down earlier than the first power module 1.

The first power-down timing control module 2 may include at least one second energy storage element P2 connected in parallel. Fig. 10 is a schematic diagram of an eighth power timing control circuit according to the present application, as shown in fig. 10, the second energy storage device P2 may include a capacitor Ca and a capacitor Cb, for example. The number of second energy storage elements P2 and the total energy storage capacity of all second energy storage elements P2 are related to the required power down time of the first power supply module 1. Illustratively, the power down speed of the first power module 1 is reduced because the second energy storage element starts to discharge when the first power module 1 is powered down. Therefore, if it is required to extend the power-down time of the first power module 1, the number of the parallel second energy storage elements P2 may be increased and/or the total energy storage energy of all the second energy storage elements P2 may be increased.

In this implementation manner, if the power-down time of the first power module 1 is prolonged, it can be further ensured that the second power module 3 completes power-down earlier than the first power module 1, so as to avoid the occurrence of the current backflow problem.

The second power-down timing control module 5 is exemplarily described below.

Fig. 11 is a schematic diagram of a ninth power timing control circuit according to the present application, as shown in fig. 11, in some embodiments, the second power-down timing control module 5 may include: an eighth resistor R8, a ninth resistor R9, and a first capacitor C1.

With continued reference to fig. 11, at this time, the internal connection relationship of the second power-down timing control module 5 may be, for example:

the first end of the eighth resistor R8 is the first end of the second power-down time sequence control module 5, and the second end of the eighth resistor R8 is the second end of the second power-down time sequence control module 5; the second end of the eighth resistor R8 is connected to the first end of the ninth resistor R9 and the first end of the first capacitor C1, respectively, and the second end of the ninth resistor R9 and the second end of the first capacitor C1 are grounded.

The eighth resistor R8 and the ninth resistor R10 are voltage dividing resistors, and are used together with the first capacitor C1 to control the conduction speed of the power-down path of the power-down module 6, that is, to control the power-down speed of the second power module 3 through the power-down module 6.

In this connection, when the first power module 1 is in a power-on or continuous power supply state, the power-down detection module controls the connected power-down module 6 to be in a non-conductive state through the second power-down timing control module 5, and the power-down module 6 does not discharge the second power module 3.

When the second power module 3 starts to power down, the power down detection module controls the conduction speed of the power down module 6 through the second power down time sequence control module 5.

Illustratively, with continued reference to fig. 11, the power down detection module 4 is turned on when the first power module 1 is powered down. At this time, since the eighth resistor R8 is a voltage dividing resistor with respect to the power-down module 6, the larger the resistance value of the eighth resistor is, the longer the voltage dividing is, the longer the first terminal of the power-down module 6 reaches the voltage required for conduction. That is, the resistance of the eighth resistor is inversely related to the turn-on speed of the power-down module 6. The ninth resistor R9 is a parallel resistor with respect to the power-down module 6, and the voltage values of the two ends of the ninth resistor R9 are the same as the voltage values of the two ends of the power-down module 6, so that the larger the resistance value of the ninth resistor R9 is, the shorter the time for the first end of the power-down module 6 to reach the voltage required for power-on. That is, the resistance of the ninth resistor R9 is integrally related to the turn-on speed of the power-down module 6. In addition, the larger the first capacitor C1 is, the slower the first terminal of the power-down module 6 reaches the voltage value required for conduction. Therefore, the on time of the power-down path of the power-down module 6 can be controlled by adjusting the sizes of the eighth resistor R8, the ninth resistor R9, and the first capacitor C1.

Therefore, when the first power supply module 1 is powered down, on one hand, the first power-down time sequence control module 2 controls and prolongs the power-down speed of the corresponding first power supply module 1; on the other hand, the second power-down timing control module 5 controls the power-down speed of the corresponding second power module 3, so that the second power module 3 can complete power-down earlier than the first power module 1. In addition, when the power supply time sequence control circuit comprises a plurality of second power supply modules 3, corresponding second power failure time sequence control modules 5 and power failure modules 6, on one hand, the power failure speed of the first power supply is controlled to be relatively longer through the first power failure time sequence control modules 2, and the power failure can be realized after the power failure of all the second power supply modules 3 is completed, on the other hand, the power failure of the plurality of second power supplies can be realized according to different power failure time sequences by adjusting the sizes of the resistors and the capacitors in the second power failure time sequence control modules 5, on the other hand, the problem of current backflow is avoided, on the other hand, the power failure time sequence control of the plurality of second power supply modules 3 and corresponding components can be realized, the application scene of the power supply time sequence control circuit is enlarged, the deployment is convenient, the operation is simple, and the multistage control of the plurality of second power supply modules 3 and the corresponding components is realized.

The power supply time sequence control circuit provided by the embodiment of the application comprises a first power supply module 1, N second power supply modules 3, a first power failure detection module 4, and a second power failure time sequence control module 5 and a power failure module 6 corresponding to each second power supply module 3. The power-down detection module 4 is configured to detect whether the first power module 1 starts to power down, and when detecting that the first power module 1 starts to power down, control the second power-down timing control module 5 to conduct a power-down path of the corresponding power-down module 6, so that the power-down module 6 discharges the second power module 3; the second power-down timing control module 5 is configured to control a power-down speed of the corresponding second power module 3, so that the second power module 3 completes power-down earlier than the first power module 1.

Through this power sequence control circuit, on the one hand, can be when first power module 1 loses the power, control second power module 3 earlier than first power module 1 accomplishes the discharge, avoids appearing the problem that the electric current was reversed and irritated, and then causes the damage of voltage conversion controller among the second power module 3 and other components and parts. On the other hand, the power supply time sequence control circuit provided by the embodiment of the application can realize the multi-stage control of a plurality of second power supply modules 3 and corresponding components, namely, can realize the control of the power supply time sequences of the plurality of second power supply modules 3 by connecting a plurality of second power supply time sequence control modules 5 and power supply modules 6 corresponding to each second power supply module 3 in parallel, expands the application scene of the power supply time sequence control circuit provided by the application, and can better meet various use requirements.

In addition, the power supply time sequence control circuit is applied to power-down time sequence control, is not influenced by the power supply time sequence control circuit applied to power-up time sequence control when the circuit is powered on or the first power supply module 1 continuously supplies power, can be flexibly matched with any power supply time sequence control circuit for power-up time sequence control, and has wide application scene, strong application flexibility and high availability.

Fig. 12 is a schematic diagram of a tenth power timing control circuit according to the present application, and the working principle of the power timing control circuit will be described below by taking fig. 12 as an example. Fig. 12 is a schematic diagram of an example in which the second switch V2 is a P-type transistor and the third switch V3 is an N-type transistor.

As shown in fig. 12, when the first power module 1 is in the power-on or continuous power-on state, the power timing control circuit controls the voltage difference between the second end and the first end of the transistor V2 through the first to fifth resistors R5, the second capacitor C2 and the third capacitor C3, respectively, so that the voltage difference required for turning on the transistor V2 cannot be reached, and the transistor V2 is in the off state. Since the transistor V2 is in the off state, the voltage at the first end of the transistor V3 cannot reach the on voltage threshold, and therefore the transistor V3 is in the off state, and the circuit from the second end to the third end of the transistor V3 is open. At this time, the second power supply module 3 cannot be powered down through the power-down path constituted by the tenth resistor R10 and the transistor V3, and the power-down path constituted by the eleventh resistor R11, the diode VD, and the transistor V3. The second power module 3 continuously outputs working voltage to the corresponding components for the components to work.

When the first power module 1 is in the power-down state, the voltage at the first end of the triode V2 drops rapidly, and the voltage at the second end drops at a lower speed than the voltage at the first end of the triode V2 under the action of the second capacitor C2 and the third capacitor C3. Therefore, as time passes, the difference between the voltage at the second terminal and the voltage at the first terminal of the transistor V2 gradually expands until the voltage difference required for turning on the transistor V2 is reached, and the transistor V2 is turned on. When the transistor V2 is turned on, under the control of the eighth resistor R8, the ninth resistor R9, and the first capacitor C1, the voltage value at the first end of the transistor V3 reaches the voltage required for the turn-on after a certain time, and the transistor V3 is turned on. At this time, the circuit from the second terminal to the third terminal of the transistor V3 forms a path, and the current can flow to the third terminal through the second terminal of the transistor V3. That is, the second power module 3 may be powered down by a power-down path formed by the tenth resistor R10 and the transistor V3, and a power-down path formed by the eleventh resistor R11, the diode VD, and the transistor V3, so as to realize rapid discharge of the second power module 3 and the corresponding components.

Meanwhile, under the action of the capacitor Ca and the capacitor Cb, the first power supply module 1 can be powered down slowly, so that the power down time of the first power supply module 1 can be controlled to be longer through the first power down time sequence control module 2, the second power supply module 3 is controlled to be powered down earlier than the first power supply module 1 through the second power down time sequence control module 5, the power down process can be powered down according to a certain time sequence only through the first power down time sequence control module 2 and the second power down time sequence control module 5, the influence of other factors such as the number of capacitors connected in parallel with the second power supply module 3 is avoided, and the problem of current backflow can be avoided.

In addition, the power supply time sequence control circuit provided by the application can control a plurality of second power supply modules 3 in parallel, can realize the multistage control of the second power supply modules 3 and corresponding components and parts while avoiding current backflow, and has flexible application, convenient deployment and strong usability.

Fig. 13 is a schematic diagram of a power-down timing of a power timing control module according to the present application, where the schematic diagram is a schematic diagram of a power timing control circuit including 3 second power modules 3 respectively corresponding to a component a, a component B, and a component C, as shown in fig. 13, t ₀ -t ₁ At the moment, the first power module 1 is in a continuous power supply state, and correspondingly, the second power module 3 corresponding to the component A, the second power module 3 corresponding to the component B and the second power module 3 corresponding to the component C are in a continuous power supply state. t is t ₁ At the moment, the first power module 1 starts to be powered down, and under the control of the power-down time sequence control circuit, the second power module 3 corresponding to the component A is powered down at t ₂ Power-down is started at the moment and is rapidly carried out at t ₄ The power failure is completed at any time; the second power module 3 corresponding to component B is at t ₃ Power-down is started at the moment and is rapidly carried out at t ₅ The power failure is completed at any time; the second power module 3 corresponding to component C is at t ₄ Power-down is started at the moment and is rapidly carried out at t ₆ And (5) finishing power failure at any time. After the second power module 3 corresponding to the component a, the second power module 3 corresponding to the component B, and the second power module 3 corresponding to the component C are powered down, the first power module 1 is powered down at t ₇ And (5) finishing power failure at any time. It is to be understood that t ₇ At a time later than t ₄ Time t ₅ Time of day, t ₆ The moment, namely all the second power modules 3 finish the power failure earlier than the first power module 1 under the control of the power timing control circuit. I.e. byAccording to the power supply time sequence control circuit provided by the application, in the power-down time sequence control process, the second power supply module 3 can finish power down earlier than the first power supply module 1, so that the problem of current backflow is avoided; the power-down time sequence control of a plurality of second unit modules and components connected with the second unit modules can be realized, namely the multistage control can be realized, and the operation is simple, the deployment is convenient, and the cost is lower; furthermore, the power supply time sequence control circuit provided by the application is not influenced by the power supply time sequence control circuit applied to the power-on process, flexible deployment can be realized, and the application scene of the power supply time sequence control circuit is enlarged.

Fig. 14 is a schematic diagram of an eleventh power timing control circuit according to the present application, as shown in fig. 14, in some embodiments, the power timing control module further includes: and a power-on time sequence control module 7. In this case, the connection relationship of the power supply timing control circuit may be, for example:

The first power module 1 is connected with a first end of a power-on time sequence control module 7, and a second end of the power-on time sequence control module 7 is connected with a first end of the second power module 3.

The present application is not limited to the circuit configuration of the power-on timing control module 7, and may be, for example, any of the power-on timing control circuits mentioned in the prior art.

Under the connection, when the main board is powered on, the power-on time sequence control module 7 controls the power-on speed of the corresponding second power module 3 when detecting that the first power module 1 starts to be powered on, so that the second power module 3 is later than the first power module 1 to complete power-on; when the motherboard is powered down, the first power module 1 performs power-down timing control on the second power module 3 through the power timing control circuit for power-down timing control provided in the above embodiment of the present application, so that the second power module 3 may be powered down earlier than the first power module 1. By the method, the power supply time sequence control module for power-down time sequence control can be isolated from the power-on time sequence control module. That is, the power-on time sequence control module does not influence the normal operation of the power supply time sequence control circuit for performing power-off time sequence control, so that the first power supply module 1 and the second power supply module 3 can be powered on or powered off according to the preset time sequence when power is on or powered off, the problems of current backflow and the like are avoided, and the circuit is protected, so that the normal working requirements of display equipment and the like are met.

The specific resistance of the resistor included in the power supply control circuit is not limited in the present application, and may be set by those skilled in the art according to actual situations.

The present application also provides a display device, which may be, for example, a television, an electronic computer, or the like, including the power supply timing control circuit in any of the above embodiments.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

The foregoing description, for purposes of explanation, has been presented in conjunction with specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the embodiments to the precise forms disclosed above. Many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles and the practical application, to thereby enable others skilled in the art to best utilize the embodiments and various embodiments with various modifications as are suited to the particular use contemplated.

Claims

1. A power supply timing control circuit, the power supply timing control circuit comprising: the power-down detection device comprises a first power supply module, a first power-down time sequence control module, N second power supply modules, a power-down detection module, a second power-down time sequence control module and a power-down module, wherein the second power-down time sequence control module corresponds to each second power supply module;

2. The circuit of claim 1, wherein the power down detection module comprises: a power down detection sub-module and a switch sub-module; the first end of the power-down detection sub-module is the first end of the power-down detection module, the second end of the power-down detection sub-module is connected with the first end of the switch sub-module, the third end of the power-down detection sub-module is connected with the second end of the switch sub-module, and the third end of the switch sub-module is the second end of the power-down detection module;

3. The circuit of claim 2, wherein the power down detection sub-module comprises: the first switch, at least one first energy storage element, a first resistor, a second resistor and a third resistor;

4. A circuit according to claim 3, wherein the power down detection sub-module further comprises a fourth resistor and/or a fifth resistor;

5. The circuit of claim 2, wherein the switch sub-module comprises: a second switch, a sixth resistor and a seventh resistor;

6. The circuit of any of claims 1-5, wherein the first power down timing control module comprises: at least one second energy storage element connected in parallel.

7. The circuit of any of claims 1-5, wherein the second power down timing control module comprises: an eighth resistor, a ninth resistor and a first capacitor;

8. The circuit of any of claims 1-5, wherein the power down module comprises: a third switch, a tenth resistor, an eleventh resistor and a diode;

9. The circuit of any one of claims 1-5, wherein the power supply timing control circuit further comprises: a power-on time sequence control module;

10. A display device comprising the power supply timing control circuit according to any one of claims 1 to 9.