JP2001104611A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To retain necessary data at the occurrence of unforeseen power-off such as a power failure to resume a game from the state at power-off at, the release of a power supply and positively retain the data when retaining the necessary data. SOLUTION: In power failure occurrence interruption processing, a CPU first sets disable and then puts all output ports in the OFF state. The CPU stores the contents of each register in a backup RAM area if necessary and sets a power-off flag. The CPU further sets the suitable initial value in a backup check data area of the backup RAM area and takes exclusive OR successively on the initial value and the data of the backup RAM area to set the final computed value into a backup parity data area. The CPU then sets an RAM access inhibiting state and sends out a halt command.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine such as a pachinko game machine or a coin game machine in which a game is played in response to a player's operation. It relates to a gaming machine in which a game is performed.

[0002]

2. Description of the Related Art As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a winning area such as a winning opening provided in the game area, a predetermined number of prize balls are obtained. Are paid out to players.
Furthermore, a variable display unit capable of changing the display state is provided,
There is a configuration in which a predetermined game value is provided to a player when a display result of the variable display unit has a predetermined specific display mode.

[0003] When the display result of the variable display section for displaying a special symbol is a combination of a predetermined specific display mode, it is usually called a "big hit". In addition, the game value is a right to make the state of the variable prize ball device provided in the game area of the gaming machine advantageous for a player who is easy to win a hit ball, or a right for the player to be in an advantageous state. Or to generate.

[0004] When a big hit occurs, for example, a big winning opening is opened a predetermined number of times, and the state shifts to a big hit game state in which a hit ball is easy to win. Then, in each open period, when a predetermined number (for example, 10) of winning prizes is won, the winning prize opening is closed. The number of opening of the special winning opening is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and if the opening time elapses even if the number of winnings does not reach a predetermined number, the winning opening is closed. If the predetermined condition (for example, winning in the V zone provided in the special winning opening) is not satisfied at the time when the special winning opening is closed, the big hit gaming state ends.

[0005] In addition, among the combinations of display modes other than the "big hit" combination, at a stage where some of the display results of the plurality of variable display portions have not been derived and displayed yet, the display results have already been derived and displayed. The state in which the display mode of the variable display unit that satisfies the display condition that is a combination of the specific display modes is called “reach”. If the display result of the identification information variably displayed on the variable display unit does not satisfy the condition of “reach”, the result is “out” and the variable display state ends. A player plays a game while enjoying how to generate a big hit.

When a game ball wins a winning opening provided on the game board, a predetermined number of award balls are paid out. Since the progress of the game is controlled by the game control means mounted on the main board, the number of winning balls based on the winning is determined by the game control means,
Sent to the prize ball control board. Hereinafter, the game control means and other control means may be referred to as game device control means, respectively.

[0007]

As described above, various types of gaming machine control means including game control means are mounted on a gaming machine. Generally, each gaming machine control means is constituted by a microcomputer. That is, a program is stored in a ROM or the like, and data that temporarily occurs in control or data that changes as the control progresses is stored in the RAM. Then, when a power-off state occurs due to a power failure or the like in the gaming machine, data in the RAM is lost. Therefore,
At the time of recovery from a power failure or the like, the player must return to the initial state (for example, the state when the game machine is first turned on at the game store for the day), which may be disadvantageous to the player. . For example, if a power failure occurs during a jackpot game and the gaming machine returns to the initial state, the player will not be able to enjoy the benefits based on the occurrence of the jackpot.

In order to avoid such a situation, necessary data is stored in a RAM which is held by a backup power supply when an unexpected power failure such as a power failure occurs, and is stored when the power is restored. The game may be resumed by restoring the data that was being played. However, if the method of saving when the power is turned off is wrong, the RA held by the backup power
Incorrect data is stored in M, and the game state is restored based on the incorrect data. In such a case, the game returns to a state different from the original game state, and an unexpected disadvantage may be given to the player.

Therefore, the present invention saves necessary data when an unexpected power failure such as a power failure occurs, allows the game to be resumed from the state at the time of the power failure when the power is restored, and ensures that the necessary data is saved when the required data is saved. It is an object of the present invention to provide a gaming machine capable of storing data in a game machine.

[0010]

A gaming machine according to the present invention comprises:
A game machine capable of giving a game result value to a player as a result of performing a predetermined game, and in which when the power is turned on, the content immediately before the power is turned off is held, and the game state is returned based on the held data. It is possible to perform state return control, a gaming machine control board on which a gaming machine control means for controlling a gaming machine provided for a game is mounted, and a power supply voltage drop is monitored so that a predetermined Power supply monitoring means for performing a detection output, wherein the gaming device control means stores a gaming device control microcomputer and fluctuation data generated when the gaming device control microcomputer performs control, and at least a predetermined period from the time of power-off. Storage means capable of being in a storage content holding state in which the storage content immediately before the power is turned off is stored. Running time predetermined power-off processing for the gaming state return based on the detected output of the monitoring means, and sets the halt status at the final part of the time of power-off process. Note that the game result value is a concept indicating payout of a game ball or an increase in a score in the case of an image-type gaming machine.

The power-off processing may include register saving processing.

[0012] The power-off processing may include processing for preventing access to the storage means.

The power supply monitoring means detects a voltage drop of the predetermined potential power supply, and a detection output of the power supply monitoring means is connected to an interrupt terminal of the gaming machine control microcomputer on the gaming machine control board. The power-off process may be performed based on an input to the interrupt terminal.

A second power supply monitoring means for detecting a voltage drop of the power supply voltage after a predetermined period of time when the power supply monitoring means detects the voltage drop is provided.
The system may be configured to be reset during the halt state in response to the input of the detection output from the second power supply monitoring unit.

In the gaming machine, the power supply monitoring means is provided on a power supply board which is provided separately from the gaming machine control board and generates each voltage used in the gaming machine control board. The configuration provided on the device control board may be used.

The power-off processing includes processing for storing check data obtained as a result of an operation related to the storage contents of the storage means in the storage means, and the gaming machine control microcomputer performs processing based on the check data when power is restored. A check may be performed, and if the check result is normal, the game state return control may be performed.

The gaming machine control microcomputer may be configured to execute an initialization process if the check result is not normal.

The power supply monitoring means and the second power supply monitoring means monitor the same power supply voltage, and the detection voltage of the second power supply monitoring means is set lower than the detection voltage of the power supply monitoring means. Is also good.

The power supply voltage monitored by the power supply monitoring means is a power supply voltage immediately after conversion from AC to DC. When the power supply voltage decreases to a predetermined value, the power supply monitoring means determines that the power supply voltage has decreased. May be configured.

[0020]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of the pachinko gaming machine 1 as viewed from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. 3 is a rear view of the pachinko gaming machine 1 as viewed from the back. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine. Further, the present invention can be applied to an image-type gaming machine or a slot machine.

As shown in FIG. 1, the pachinko gaming machine 1
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing prize balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided. Behind the glass door frame 2,
The game board 6 is detachably attached. A game area 7 is provided on the front of the game board 6.

In the vicinity of the center of the game area 7, a variable display section 9 for variably displaying a plurality of types of symbols and a 7-segment L
A variable display device 8 including a variable display 10 using an ED is provided. In this embodiment, the variable display section 9 has three symbol display areas of “left”, “middle”, and “right”. On the side of the variable display device 8, a passing gate 11 for guiding a hit ball is provided. The hit ball that has passed through the passing gate 11 is guided to the starting winning opening 14 via the ball exit 13. In a passage between the passage gate 11 and the ball outlet 13, there is a gate switch 12 for detecting a hit ball that has passed through the passage gate 11. In addition, the winning ball that entered the starting winning port 14 is
It is guided to the back of the game board 6 and is detected by the starting port switch 17. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. The variable winning ball device 15 is opened by the solenoid 16.

An opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state) is provided below the variable winning ball apparatus 15. In this embodiment, the opening and closing plate 20 serves as a means for opening and closing the special winning opening. The winning ball that enters one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by the V count switch 22. The winning ball from the opening / closing plate 20 is detected by the count switch 23. Variable display device 8
A start winning prize storage display 18 having four display sections for displaying the number of winning balls entering the starting winning prize port 14 is provided below. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. Then, each time the variable display of the variable display unit 9 is started, the number of the lit display units is reduced by one.

The gaming board 6 is provided with a plurality of winning ports 19 and 24, and the winning of the game balls to the winning ports 19 and 24 is detected by the winning port switches 19a and 24a. At the left and right sides of the game area 7, there are provided decorative lamps 25 which are displayed blinking during the game, and at the lower part there is an out port 26 for absorbing hit balls which have not won. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. A gaming effect LED 2 is provided on the outer periphery of the gaming area 7.
8a and gaming effect lamps 28b and 28c are provided.

In this example, one of the speakers 27
Is provided with a prize ball lamp 51 which is lit when a prize ball is paid out, and a ball out lamp 52 which is lit when a supply ball is out is provided near the other speaker 27. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming table 1 and enables lending of balls by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card can be used. If there is a fraction (less than 100 yen) in the balance information recorded in the card, the fraction is displayed. Fraction display switch 1 for displaying on a frequency display LED provided near hit ball supply tray 3
52, a connecting stand direction indicator 15 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to
3. Card insertion indicator 154 indicating that a card has been inserted into card unit 50, card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back of card insertion slot 155 A card unit lock 156 is provided to release the card unit 50 when checking the mechanism of the writer.

The hit ball fired from the hitting ball launching device enters the game area 7 through the hitting rail, and thereafter, the game area 7
Come down. When a hit ball is detected by the gate switch 12 through the passage gate 11, the display number of the variable display 10 is changed continuously. Further, when a hit ball enters the starting winning opening 14 and is detected by the starting opening switch 17, the symbol in the variable display section 9 starts rotating if the symbol can be changed. If it is not possible to start changing the symbol, the start winning memory is increased by one.

The rotation of the image in the variable display section 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols, the game shifts to a big hit game state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. Then, when a hit ball wins in the specific winning area while the opening and closing plate 20 is opened and is detected by the V count switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. Generation of the continuation right is permitted a predetermined number of times (for example, 15 rounds).

If the combination of images in the variable display section 9 at the time of stoppage is a combination of big hit symbols with probability fluctuation, the probability of the next big hit becomes high. That is, a high probability state, which is more advantageous for the player, is obtained. Also, when the stop symbol on the variable display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the variable display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. On the back of the variable display device 8, as shown in FIG. 2, a prize ball tank 38 is provided above the mechanism plate 36, and when the pachinko gaming machine 1 is installed on the gaming machine installation island, a prize ball is provided from above. Premium ball tank 3
8 is supplied. The prize ball in the prize ball tank 38 reaches the ball payout device through the guide gutter 39.

On the mechanism plate 36, a variable display control unit 29 for controlling the variable display section 9 via the relay board 30, and a game control board (main board) covered with a board case 32 and mounted with a game control microcomputer and the like. ) 31, a relay board 33 for relaying a signal between the variable display control unit 29 and the game control board 31, and a prize ball control board on which a prize ball control microcomputer for controlling the payout of prize balls is mounted. 37 are installed. Further, a ball is hit on the lower part of the mechanism plate 36 by using the rotating force of the motor in the game area 7.
Ball launching device 34 that launches on a game effect lamp / LE
D28a, 28b, 28c, a prize ball lamp 51 and a lamp control board 35 for sending signals to the ball out lamp 52 are provided.

FIG. 3 is a rear view of the gaming board of the pachinko gaming machine 1 as viewed from the rear. The ball that passed through the induction gutter 39
As shown in FIG. 3, the ball cut detectors 187a, 187
b, and reaches the ball dispensing device 97 via the ball supply gutters 186a and 186b. The prize ball paid out from the ball payout device 97 is supplied to the hit ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the communication port 45. On the side of the communication port 45, an excess ball passage 46 communicating with the excess ball tray 4 provided on the front of the pachinko gaming machine 1 is formed. A large number of prize balls based on the prize are paid out, and the ball supply tray 3 becomes full. Finally, after the prize balls reach the communication port 45, further prize balls are paid out. It is led to the ball tray 4. When the prize ball is further paid out, the sensing lever 47 is set to the full switch 4.
By pressing 8, the full tank switch 48 is turned on. In this state, the rotation of the stepping motor in the ball discharging device 97 stops, the operation of the ball discharging device 97 stops, and the driving of the hitting ball firing device 34 also stops as necessary. In addition,
In this embodiment, a ball payout device 97 in which game balls are paid out by rotation of a stepping motor is illustrated as a ball payout device that pays out game balls by driving an electric drive source. A ball payout device having a structure of sending out a ball may be used, or a ball payout device having a structure in which a stopper is removed by driving an electric drive source and payout is performed by the weight of the game ball may be used.

Signals from the winning opening switches 19a and 24a, the starting opening switch 17 and the V count switch 22 are sent to the main board 31 in order to perform the prize ball payout control.
When the starting port switch 17 is turned on, the CPU 56 of the main board 31 knows that a winning corresponding to the payout of six winning balls has occurred. Further, when the count switch 23 is turned on, it is known that a winning corresponding to the payout of 15 prize balls has occurred. Then, when the winning opening switch is turned on, it is known that a winning corresponding to the payout of 10 prize balls has occurred. In this embodiment, for example, a game ball that has won the winning opening 24 is detected by the winning opening switch 24 a provided in the winning ball flow path from the winning opening 24, and the game ball that has won the winning opening 19 is detected. Is
It is detected by a winning opening switch 19a provided in a winning ball flow path from the winning opening 19.

FIG. 4 is a block diagram showing an example of a circuit configuration of the main board 31. FIG. 4 also shows the prize ball control board 37, the lamp control board 35, the sound control board 70, the emission control board 91, and the display control board 80.
The pachinko machine 1 is provided on the main board 31 according to the program.
, A switch circuit 58 for giving signals from the gate switch 12, the starting port switch 17, the V count switch 22, the count switch 23, and the winning port switches 19a, 24a to the basic circuit 53, and a variable winning ball device. A solenoid circuit 59 for driving a solenoid 16 for opening and closing the opening 15 and a solenoid 21 for opening and closing the opening and closing plate 20 in accordance with a command from the basic circuit 53; A lamp / LED circuit 60 for driving the lamp 10 and the decorative lamp 25 is mounted.

According to the data supplied from the basic circuit 53, jackpot information indicating occurrence of a jackpot, effective start information indicating the number of start winning balls used to start image display of the variable display section 9, and probability fluctuation have occurred. And an information output circuit 64 that outputs probability change information or the like indicating the fact to a host computer such as a hall management computer.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 as an example of a storage means used as a work memory, a CPU 56 for performing a control operation according to a control program, and an I / O port unit 57. including. In this embodiment, the ROM 54,
The RAM 55 is built in the CPU 56. That is,
The CPU 56 is a one-chip microcomputer.
The one-chip microcomputer has at least R
It is sufficient if the AM 55 is built-in.
The / O port section 57 may be externally mounted or built-in. The I / O port unit 57 is a terminal capable of inputting and outputting information in the microcomputer.

Further, the main board 31 has an initial reset circuit 65 for resetting the basic circuit 53 when the power is turned on.
And an address decode circuit 67 that decodes an address signal provided from the basic circuit 53 and outputs a signal for selecting one of the I / O ports in the I / O port unit 57. Although there is switch information input from the ball dispensing device 97 to the main board 31, FIG.
Then they are omitted.

A hit ball launching device that hits and fires a game ball is driven by a drive motor 94 controlled by a circuit on a launch control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

FIG. 5 is a block diagram showing an example of a configuration around the CPU 56 for power supply monitoring and power supply backup. As shown in FIG. 5, a voltage drop signal from a first power supply monitoring circuit (first power supply monitoring means) mounted on a power supply board is connected to an interrupt terminal (IRQ terminal) of the CPU 56. The first power supply monitoring circuit is a circuit that monitors the voltage of any one of various DC power supplies used by the gaming machine and detects a drop in the power supply voltage. Therefore, CPU5
No. 6 can confirm the occurrence of power interruption by interrupt processing.

A second power supply monitoring circuit 90 is provided on the main board 31.
3 is installed. In this example, in the second power supply monitoring circuit 903, the power supply monitoring IC 904 has a power supply voltage equal to the power supply voltage monitored by the first power supply monitoring circuit.
A 30V power supply voltage is monitored, and a low level voltage drop signal is generated when the voltage value falls below a predetermined value. Then, for example, the detection voltage (voltage at which a voltage drop signal is output) of the first power supply monitoring circuit mounted on the power supply board is increased by +16.
V, and the detection voltage of the second power supply monitoring circuit 903 is +8 V
And In such a configuration, since the same voltage is monitored, the difference between the timing at which the first voltage monitoring circuit outputs the voltage drop signal and the timing at which the second voltage monitoring circuit outputs the voltage drop signal is desired. Can be reliably set in the predetermined period. The desired predetermined period is a period from the start of the power-down processing in response to the voltage drop signal from the first power supply monitoring circuit to the completion of the power-off processing.

The voltage drop signal from the second power supply monitoring circuit 903 is input to the reset terminal of the CPU 56 after being logically ORed with the initial reset signal from the initial reset circuit 65. Accordingly, when the initial reset signal from the initial reset circuit 65 is at a low level, or when the voltage drop signal from the second power supply monitoring circuit 903 is at a low level, the CPU 56 is in the reset state ( Non-operating state).

The reset I of the initial reset circuit 65
When the power of the gaming machine is turned on and the voltage of the + 5V power supply rises, the C651 sets the output signal to a high level when the + 5V power supply voltage exceeds a predetermined value. That is, the initial reset signal is turned off.

While power is not supplied from the +5 V power supply, which is the driving power supply of the CPU 56 and the like, at least a part of the RAM is backed up by the backup power supply supplied from the power supply board, and the contents are maintained even if the power supply to the gaming machine is cut off. Is saved. Then, when the +5 V power supply is restored, a reset signal is issued from the initial reset circuit 65, and the CPU 56 returns to the normal operation state. At that time, since the necessary data is backed up, it is possible to return to the gaming state at the time of the occurrence of the power failure when recovering from a power failure or the like.

FIG. 6 shows the circuit configuration in the display control board 80 by using the CRT 82 as an example of the variable display section 9 and the output ports (ports A and B) 571 and 572 of the main board 31.
FIG. 9 is a block diagram shown together with an output buffer circuit 63. The output port 571 outputs 8-bit data, and the output port 572 outputs a 1-bit strobe signal (INT signal).

The display control CPU 101 controls the control data R
It operates according to the program stored in the OM 102, and receives a display control command via the input buffer circuit 105 when a strobe signal is input from the main board 31 via the noise filter 107 and the input buffer circuit 105. As the input buffer circuit 105, for example, a general-purpose IC
74HC244 can be used. In addition,
When the display control CPU 101 does not include an I / O port, the input buffer circuit 105 and the display control CP
An I / O port is provided between U101.

Then, the display control CPU 101 controls display of a screen displayed on the CRT 82 in accordance with the received display control command. Specifically, a command corresponding to the display control command is given to the VDP 103. VDP103
Reads necessary data from the character ROM 86. The VDP 103 generates a CRT 8 according to the input data.
2 is generated, and the image data is stored in the VRAM 87. Then, the image data in the VRAM 87 is converted into R, G, B signals, converted into analog signals by the DA converter 104, and output to the CRT 82.

FIG. 6 also shows a reset circuit 83 for resetting the VDP 103, an oscillation circuit 85 for supplying an operation clock to the VDP 103, and a character ROM 86 for storing frequently used image data. The frequently used image data stored in the character ROM 86 is, for example, a person, an animal, or an image composed of characters, graphics, or symbols displayed on the CRT 82.

FIG. 7 is a block diagram showing components related to the prize ball, such as the components of the prize ball control board 37 and the ball payout device 97. As shown in FIG. 7, the detection signal from the full tank switch 48 is transmitted to the main board 3 via the relay board 71.
1 is input to the I / O port 57. Full tank switch 4
Reference numeral 8 denotes a switch that detects whether the surplus ball tray 4 is full.

The detection signals from the cut-out ball detection switch 167 and the cut-out ball switch 187 (187a, 187b) are transmitted to the main board 3 via the relay board 72 and the relay board 71.
1 is input to the I / O port 57. The out-of-ball detection switch 167 is a switch for detecting a shortage of replenishment balls in the prize ball tank 38, and the out-of-ball switch 187 is a switch for detecting the presence or absence of a prize ball in the prize ball passage.

The CPU 56 of the main board 31 indicates that the detection signal from the ball out detection switch 167 or the ball out switch 187 indicates that the ball is out, or the detection signal from the full switch 48 indicates the full state. If it is, a prize ball control command for instructing ball lending is sent. When receiving the award ball control command instructing the ball lending prohibition, the award ball control CPU 371 of the award ball control board 37 stops the ball lending process.

Further, the detection signal from the prize ball count switch 301A is also input to the I / O port 57 of the main board 31 via the relay board 72 and the relay board 71. The prize ball count switch 301A is connected to the ball payout device 97.
Is provided in the prize ball mechanism portion of the prize ball and detects a prize ball actually paid out.

When there is a prize, the output ports (ports G, H) 577, 578 of the main board 31 are provided on the prize ball control board 37.
, A prize ball control command indicating the number of prize balls is input. The output port 577 outputs 8-bit data, and the output port 578 outputs a 1-bit strobe signal (INT signal). The award ball control command indicating the number of award balls is input to the I / O port 372a via the input buffer circuit 373. The CPU 371 for controlling the prize ball includes an I / O port 37.
A prize ball control command is input via 2a, and the ball payout device 97 is driven according to the prize ball control command to perform a prize ball payout. In this embodiment, the CPU 37 for controlling the prize ball
Reference numeral 1 denotes a one-chip microcomputer having at least a RAM.

The prize ball control CPU 371 is connected to the output port 3
Via 72g, a ball lending number signal indicating the lending ball number is output to the terminal board 160, and a buzzer drive signal is output to the buzzer board 75. A buzzer is mounted on the buzzer board 75. Further, an error signal is output to the error display LED 374 via the output port 372e.

Further, the input port 3 of the prize ball control board 37
The detection signal of the detection signal of the winning ball count switch 301A is input to 72b via the relay board 72. The drive signal from the prize ball control board 37 to the payout motor 289 is
The output is transmitted to the payout motor 289 in the winning ball mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72.

The card unit 50 has a microcomputer for controlling the card unit. Also,
The card unit 50 is provided with a fraction display switch 152, a connection board direction indicator 153, a card insertion indicator lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected to a frequency display LED, a ball lending switch, and a return switch provided near the hit ball supply tray 3.

From the balance display board 74 to the card unit 50
In response to the player's operation, a ball lending switch signal and a return switch signal are provided via the prize ball control board 37. In addition, the balance display board 74 is provided from the card unit 50.
, A card balance display signal indicating the balance of the prepaid card and a ball lending possible display signal are given via the prize ball control board 37. Between the card unit 50 and the prize ball control board 37, a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal)
A pachinko machine operation signal (PRDY signal) is exchanged via the I / O port 372f.

When the power of the pachinko gaming machine 1 is turned on,
The prize ball control CPU 371 of the prize ball control board 37 outputs a PRDY signal to the card unit 50. When the card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the microcomputer for controlling the card unit outputs a BRDY signal to the prize ball control board 37. When a predetermined delay time elapses from this point, the microcomputer for controlling the card unit outputs a BRQ signal to the prize ball control board 37. The CPU 37 for controlling the prize ball on the prize ball control board 37
1 drives the payout motor 289 and pays out a predetermined number of lending balls to the player. Then, when the payout is completed, the prize ball controlling CPU 371 outputs an EXS signal to the card unit 50.

As described above, all signals from the card unit 50 are input to the prize ball control board 37. Therefore, regarding the ball lending control, the card unit 5
No signal is input from 0 to the main board 31, and there is no room for a signal to be incorrectly input from the card unit 50 side to the basic circuit 53 of the main board 31. Although the main board 31 and the prize ball control board 37 are provided with a solenoid and a driver circuit for driving a motor or a lamp, these circuits are omitted in FIG.

FIG. 8 is a block diagram showing an example of the configuration of the power supply board 910. The power supply board 910 includes a main board 31, a display control board 80, a sound control board 70, and a lamp control board 35.
The game device control board such as the prize ball control board 37 is installed independently of the game machine control board, and generates a voltage used by each game machine control board and mechanical components in the gaming machine. In this example, AC24
V, DC + 30V, DC + 21V, DC + 12V and DC + 5V. Further, the capacitor 916 serving as a backup power supply is DC + 5V, that is, I
C is charged from a power supply line for driving C and the like.

The transformer 911 converts an AC voltage from an AC power supply to 24V. AC 24V voltage is applied to connector 9
15 is output. Further, the rectifier circuit 912 includes an AC24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
The C converter 913 has + 21V, + 12V and + 5V.
V is generated and output to the connector 915. Connector 91
5 is connected to, for example, a relay board, from which electric power of a voltage required for each gaming machine control board and mechanical components is supplied. A power switch 918 for stopping and starting power supply to the gaming machine is provided on the input side of the transformer 911.

+5 V from DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 supplies power to the backup RAM (power-backed-up RAM, that is, a storage unit that can be in a storage content storage state) of the gaming machine control board when the power supply to the gaming machine is cut off, so that the storage state can be maintained. Backup power supply. Also,
A diode 917 for preventing backflow is inserted between the + 5V line and the backup + 5V line.

As a backup power supply, a battery that can be charged from a +5 V power supply may be used. In the case of using a battery, a rechargeable battery is used which runs out of capacity when power is not supplied from a + 5V power supply for a predetermined time.

The power supply board 910 has the first
The power supply monitoring IC 902 constituting the power supply circuit of FIG. The power supply monitoring IC 902 detects the occurrence of power interruption by introducing a +30 V power supply voltage and monitoring the +30 V power supply voltage. Specifically, when the + 30V power supply voltage becomes equal to or lower than a predetermined value (+ 16V in this example), a voltage drop signal is output assuming that power supply is cut off. In addition, +30
The V power supply voltage is a voltage immediately after conversion from AC to DC. The voltage drop signal from the power supply monitoring IC 902 is supplied to the main board 31, the prize ball control board 37, and the like.

The predetermined value for the power supply monitoring IC 902 to detect the power-off is lower than the normal voltage, but is a voltage at which the CPU on each game device control board can operate for a while. Further, the power supply monitoring IC 902 is higher than the voltage for driving the CPU (+5 V in this example), and
Since the configuration is such that the voltage immediately after the conversion from AC to DC is monitored, the monitoring range can be expanded for the voltage required by the CPU. Therefore, more precise monitoring can be performed. Furthermore, the monitoring voltage is +30
When V is used, since the voltage supplied to various switches of the gaming machine is +12 V, prevention of erroneous switch-on detection upon momentary power interruption can be expected. That is, + 30V
By monitoring the voltage of the power supply, it is possible to detect a decrease in + 12V generated after the generation of + 30V before the voltage starts dropping. Therefore, when the voltage of the + 12V power supply decreases, the switch output comes to the on state. However, if the + 30V power supply voltage that drops faster than + 12V is monitored and the power cutoff is recognized, the power supply is turned on before the switch output turns on. It is possible to enter a state of waiting for restoration and to enter a state where the switch output is not detected.

Further, since the power supply monitoring IC 902 is mounted on the power supply board 910 separate from the gaming machine control board, the first power supply monitoring circuit supplies a voltage drop signal to the plurality of gaming machine control boards. Can be. Regardless of the number of gaming machine control boards that require a voltage drop signal, it is sufficient that only one first power supply monitoring unit is provided, so that each gaming machine control unit in each gaming machine control board performs power supply return control described later. Does not significantly increase the cost of the gaming machine.

Next, the operation of the gaming machine will be described. FIG.
9 is a flowchart showing a main process executed by the CPU 56 on the main board 31. When the power to the gaming machine is turned on, in the main processing, the CPU 56 first checks whether or not the power has been restored from the power failure (step S1). Whether or not recovery from a power failure has occurred is confirmed by, for example, a power-off flag set in the backup RAM area when the power is turned off.

That is, when the power of the gaming machine is turned on again while the power of the RAM area is backed up, the RAM
Since the state at the time of power-off is stored, the power-off flag is also accurately stored. When the power of the gaming machine is turned on in a state where the power of the RAM area is not backed up, R
Since the content of AM is undefined, the value of the power-off flag is not correct. Therefore, it is possible to confirm whether or not recovery from a power failure has occurred according to the set state of the power-off flag. Even if the power-off flag is set when the power is turned on to the gaming machine in a state where the power is not backed up, it is erroneously determined by the parity diagnosis that will be described later that the power has been restored from the power failure. Is prevented from being determined.

If it is time to recover from a power failure, the CP
U56 executes a power failure recovery process described later (step S4). If it is not time to recover from the power failure, the CPU 56
Executes a normal initialization process (steps S1 and S1).
2). Thereafter, in the main process, the process shifts to a loop process in which the monitoring of the timer interrupt flag (step S6) is confirmed. In the loop, a display random number update process (step S5) is also executed.

In the normal initialization process, as shown in FIG. 10, the register and RAM are cleared (step S2).
a) and the initial setting (timeout is 2 ms) of the timer register provided in the CPU 56 so that the timer is periodically interrupted every 2 ms after the necessary initial value setting processing (step S2b) is performed. And a setting for operating the repetition timer) is performed (step S2c). That is, in step S2c, a process of activating a timer interrupt and a process of setting a timer interrupt interval are executed.

Therefore, in this embodiment, the CPU 56
Is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is 2 ms
Is set to Then, as shown in FIG. 11, when a timer interrupt occurs, the CPU 56 sets a timer interrupt flag (step S11).

When detecting that the timer interrupt flag has been set in step S6, the CPU 56 resets the timer interrupt flag (step S6).
7), a game control process is executed (step S9). According to the above control, in this embodiment, the game control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the game control process is executed in the main process.
The game control process may be executed by a timer interrupt process.

FIG. 12 is a flowchart showing a game control process. In the game control process, the CPU 56 first performs a process of setting a display control command sent to the display control board 80 in a predetermined area of the RAM 55 (display control data setting process: step S21), and then executes the display control command. Output processing is performed (display control data output processing: step S22).

Next, processing for outputting the contents of the storage area for various output data to each output port is performed (data output processing: step S23). Further, an output data setting process for setting output data such as big hit information, start information, and probability variation information output to the hall management computer in the storage area is performed (step S24). Further, various abnormality diagnosis processes are performed by the self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S25).

Next, a process for updating each counter indicating a random number for determination, such as a random number for big hit determination, used for game control is performed (step S26).

Further, the CPU 56 performs a special symbol process (step S27). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Further, a normal symbol process is performed (step S28). In the normal symbol process process, a corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

Further, the CPU 56 includes a switch circuit 58
, The state of the gate sensor 12, the starting port sensor 17, the count sensor 23, and the winning port switches 19a and 24a are input, and it is determined whether or not each of the winning ports and the winning device has a winning (switch processing: step S29). .
The CPU 56 further performs a process of updating a display random number such as a random number that determines the type of stop symbol (step S3).
0).

Further, the CPU 56 performs signal processing with the award ball control board 37 (step S31). That is,
When a predetermined condition is satisfied, a prize ball control command is output to the prize ball control board 37. The prize ball control CPU mounted on the prize ball control board 37 drives the ball payout device 97 according to the prize ball control command.

As described above, the main processing includes the processing for determining whether or not to shift to the game control processing.
Since a flag is set to determine whether or not to shift to the game control process in the timer interrupt process based on the timer interrupt that is periodically generated by the 56 internal timers, all the game control processes are reliably executed. Is done. In other words, until all of the game control processes have been executed, it is not determined whether or not to shift to the next game control process, so it is guaranteed that all processes in the game control process will be completed. ing.

In the conventional general game control process, the game machine is forcibly returned to the initial state by an external interrupt that occurs periodically. Explaining in accordance with the example shown in FIG. 12, for example, even during the process of step S31, the process is forcibly returned to the process of step S21. In other words, there is a possibility that the next game control process will be started before all the processes in the game control process are completed.

Here, the CPU 56 of the main board 31
Is executed in response to a flag set in a timer interrupt process based on a timer interrupt that is periodically generated by an internal timer of the CPU 56, but the signal is periodically (for example, every 2 ms). A hardware circuit which generates the signal may be provided, a signal from the circuit may be introduced to an external interrupt terminal of the CPU 56, and a flag for determining whether or not to shift to the game control process based on the interrupt signal may be set. Good. Even in such a configuration, the flag is not determined until all of the game control processing is executed, so that execution of all the processing during the game control processing is guaranteed to be completed.

FIG. 13 is a flowchart showing an example of a power failure occurrence interrupting process executed in response to an interrupt based on a voltage drop signal from the first power supply monitoring circuit of the power supply board 910. In the power failure occurrence interruption process, the CPU 56 first sets the interruption prohibition (step S41). In the power failure interrupt generation process, a checksum generation process is performed to ensure that the contents of the RAM are preserved. If another interrupt process is performed during that process, the voltage may drop to a level at which the CPU cannot operate before the checksum generation process is completed. The setting is made so that no interrupt occurs.

Next, the CPU 56 turns off all output ports (step S42). Then, if necessary, the contents of each register are stored in the backup RAM area (step S43). Further, a power-off flag is set (step S44). In addition, backup RAM
An appropriate initial value is set in the backup check data area of the area (step S45), exclusive OR is sequentially performed on the initial value and the data in the backup RAM area (step S46), and the final operation value is converted to the backup parity data. The area is set (step S47). Thereafter, the RAM access is prohibited (step S4).
8). When the power supply voltage decreases, the levels of various signal lines may become unstable and the contents of the RAM may be corrupted. However, if the RAM access is prohibited in this manner, the data in the backup RAM may be corrupted. There is no.

Next, the CPU 56 executes the halt instruction (H
ALT instruction) (step S49). That is, the CPU itself is set to a state where it does not operate except for reset release or interrupt generation. However, since the interrupt is prohibited in step S41, no interrupt occurs. Therefore, before the operation is disabled from the outside by the reset signal from the power supply monitoring IC 904 shown in FIG. 5, the operation is internally stopped. Therefore, when the power is turned off, the operation of the CPU 56 is reliably stopped. As a result, the RAM
The access prohibition control and the operation stop control can reliably prevent the contents of the RAM from being destroyed due to an abnormal operation that may occur as the power supply voltage decreases.

In the present embodiment, the power failure occurrence interrupt processing is configured to issue a halt instruction at the last part, but the program may be in a loop state.

As described above, the power-off flag set before the RAM access is prohibited is used to determine whether or not to recover from a power failure when the power is turned on. Further, the processing of steps S41 to S49 is completed before the second power supply monitoring unit generates the voltage drop signal.
In other words, the detection voltages of the first voltage monitoring means and the second voltage monitoring means are set so that the detection is completed before the second power supply monitoring means generates the voltage drop signal.

FIG. 14 shows a power failure recovery process (step S4).
6 is a flowchart illustrating an example of the above. In the power failure recovery processing, the CPU 56 first performs data check (parity check in this example) of the backup RAM area (step S51). If the power is restored after an unexpected power failure, the data in the backup RAM area should have been saved, and the check result becomes normal.
If the check result is not normal, since the internal state cannot be returned to the state at the time of power failure, the same initialization processing as the initialization processing (step S2) executed at the time of power-on without power recovery is executed. (Steps S52 and S5
4).

If the check result is normal, the CPU 56
Performs the game state restoring process for returning the internal state to the state at the time of power-off (step S53), and clears the power-off flag (step S55).

Here, in step S1, it is confirmed whether or not the power is restored from the power failure. If the power is restored from the power failure, the parity check is performed. First, the parity check is executed and the check result is normal. Otherwise, it is determined that it is not the recovery from the power failure, and the initialization processing of step S2 is executed, and if the check result is normal, the game state return processing may be performed. That is, it may be determined based on the result of the parity check whether recovery from a power failure has occurred.

FIG. 15 is an explanatory diagram for explaining a backup parity data creating method. However, FIG.
In the example shown in FIG.
The size of the data in the M area is 3 bytes. In the power failure generation process based on the power supply voltage drop, as shown in FIG. 15A, initial data (00H in this example) is set in the backup check data area. Next, "00
The exclusive OR of “H” and “F0H” is calculated, and the result is exclusive ORed with “16H”. Further, an exclusive OR of the result and “DFH” is obtained. Then, the result (“39H” in this example) is set in the backup parity data area.

When the power is turned on again, the parity diagnosis is performed in the power failure recovery processing. FIG. 15B is an explanatory diagram showing an example of the parity diagnosis. If all the data in the backup area is stored as it is, the data as shown in FIG. 15A is set in the backup area when the power is turned on again.

In the process of step S51, the CPU 5
6 is the data set in the backup parity data area of the backup RAM area (in this example, “39”).
H)) as initial data, a process of sequentially taking an exclusive OR for each data in the backup data area is performed.
If all the data in the backup area is stored as it is, the final calculation result is “00H”, that is, the same as the data set in the backup check data area. If a bit error has occurred in the data in the backup RAM area, the final calculation result is “00”.
H ".

Therefore, the CPU 56 compares the final operation result with the data set in the backup check data area, and if they match, determines that the parity diagnosis is normal. If they do not match, it is determined that the parity diagnosis is abnormal.

As described above, in this embodiment, the game control means is provided with the storage means (backup RAM in this example) which is backed up for a predetermined period of time even if the power of the game machine is turned off. At the time of insertion, the CPU 56 (specifically, a program executed by the CPU 56) is configured to perform a game state restoration process (step S53) for restoring the game state based on the backup data if the storage means is in the backup state. .

In this embodiment, the first power supply monitoring means is mounted on the power supply board 910 as shown in FIG. 8, and the second power supply monitoring means is mounted on the main board 31 as shown in FIG. It is installed. When the power supply voltage decreases, the second power supply monitoring means (in this example, the power supply monitoring IC 9)
04) is set to generate a voltage drop signal later than the first power supply monitoring means (power supply monitoring IC 902 in this example) generates a voltage drop signal. Further, a voltage drop signal from the second power supply monitoring means is input to a reset terminal of the CPU 56.

Then, the CPU 56 enters the halt state after executing the power failure generation processing (power-off processing) based on the voltage drop signal from the first power supply monitoring means (power supply monitoring IC 902). In the state
It will enter the reset state. That is, the CPU 56
Operation stops completely. In the halt state, the input / output state becomes unstable because the +5 V power supply voltage value gradually decreases, but since the CPU 56 is in the reset state, abnormal operation based on the undefined data is prevented.

As described above, in this embodiment, the CPU
56 is configured to enter the halt state in response to the input of the detection output from the first power supply monitoring means and to be reset in response to the input of the detection output from the second power supply monitoring means. It is possible to reliably store data at the time of disconnection, and prevent disadvantages from being brought to the player.

In this embodiment, the power monitoring I
Although C902 and 904 monitor the same power supply voltage, they may monitor different power supply voltages. For example, the first power supply monitoring circuit of the power supply board 910 may monitor the + 30V power supply voltage, and the second power supply monitoring circuit of the main board 31 may monitor the + 5V power supply voltage. The power supply monitoring IC 90 of the main board 31 is configured such that the timing at which the second power supply monitoring circuit generates the low-level voltage drop signal is later than the timing at which the first power supply monitoring circuit generates the voltage drop signal.
4, a threshold level (voltage level for generating a voltage drop signal) is set. For example, the threshold is 4.25V. 4.25V is lower than the normal voltage,
6 is a voltage that can operate for a while.

In the above embodiment, the CPU 56
Detected the first voltage drop signal from the power supply board (voltage drop signal from the first power supply monitoring means) via the maskable external interrupt terminal (IRQ terminal). A non-maskable interrupt terminal (NMI terminal) may be introduced. In that case, the power-off process is executed in the NMI process. Further, the first voltage drop signal from the power supply board via the input port 570 may be detected. In that case, the input port is monitored in the main processing.

When the first voltage drop signal from the power supply board is detected via the IRQ terminal, an IRQ interrupt mask is set at the start of the game control process in step S10 of the main process, and the game control process is started. At the end, the IRQ interrupt mask may be released. In such a case, an interruption occurs before and after the start of the game control process, so that the game control process is not interrupted halfway.
Therefore, there is no possibility that the command transmission is interrupted when the award ball control command is transmitted to the award ball control board 37 or the like. Therefore, even when a power failure occurs, the transmission of the prize ball control command or the like is surely completed.

Next, display control of the variable display section 9 will be described. FIG. 16 is an explanatory diagram illustrating a configuration example of display control command data using 8-bit data. As shown in FIG. 16, for example, the upper 4 bits of the 8 bits indicate the type of control, and the lower 4 bits indicate the specific control content. For example, in this example, the upper 4 bits are [0,
[0, 0, 1], the type of variation or the like is indicated by the numerical value of the lower 4 bits. The upper four bits are [1, 0, 0,
0], [1,0,0,1] or [1,0,1,0], a left symbol, a middle symbol, or a right symbol, which is variably displayed on the variable display section 9 with the lower four bits of the numerical value. A stop symbol is indicated.

The upper 4 bits are [1,1,0,1].
If it is, it indicates that it is a demo screen display command. If the upper 4 bits are [1,1,1,0], it indicates that the command is an error display command. The upper four bits are [1,1,1,
1] indicates that it is an all symbol stop command (confirmation command). In these commands, the lower 4
The bit is set to 0, for example.

In this embodiment, the CPU of the main board 31
Reference numeral 56 denotes a display control board 80 which displays a command indicating a variation type and a command indicating a left and right middle stop symbol at the start of symbol variation.
To send to. Display control CPU 10 of display control board 80
1 can specify the fluctuation time of the symbol by the command indicating the fluctuation type. If a plurality of types of variation modes corresponding to the specified variation time are prepared, the display control CPU 101 determines which variation mode to use. Thus, the main board 3
The first CPU 56 only transmits information capable of specifying a change time and information capable of specifying a fixed symbol at the start of the change, and specific symbol change control is realized by the control of the display control CPU 101. The CPU 5 of the main board 31
6 sends a confirmation command to the display control board 80 after the change time elapses.

FIG. 17 shows the main board 31 to the display control board 8.
FIG. 9 is an explanatory diagram showing a configuration example of a display control command sent to 0. As shown in FIG. 17, the display control command is 8
Bit data and a 1-bit strobe signal (INT
Signal).

FIG. 18 is a flowchart showing an example of a special symbol process program executed by the CPU 56. The special symbol process process shown in FIG. 18 is a specific process of step S27 in the game control process shown in FIG. When performing the special symbol process process, the CPU 56 performs the processing shown in FIG. 1 according to the value of the special symbol process flag.
8, any one of steps S300 to S309 is performed. In each process, the following processes are performed.

Special symbol change waiting process (step S30)
0): The start winning port 14 (in this embodiment, the winning port of the variable winning ball device 15) is hit and the start port sensor 17 is turned on. When the starting port sensor 17 is turned on, the starting winning memory number is + if the starting winning memory number is not full.
1 is done. Then, a big hit determination random number is extracted.

Special symbol determination processing (step S301):
When the state in which the variable display of the special symbol can be started, the number of start winning prize stored is confirmed. If the starting prize memory number is not 0,
It is determined whether to be a big hit or an out-of-big hit according to the value of the extracted big hit determination random number. Stop symbol setting process (step S302): A stop symbol for the left and right middle symbols is determined.

Reach operation setting processing (step S30)
3): Whether or not to perform the reach operation is determined according to the value of the reach determination random number, and the fluctuation time of the reach operation is determined according to the value of the reach random number.

All symbols change start processing (step S30)
4): In the variable display section 9, control is performed so that all symbols start to change. At this time, with respect to the display control board 80,
Information that can specify the final stop symbol and the fluctuation time in the left and right is transmitted.

All symbols stop wait processing (step S30)
5): After a predetermined time has elapsed, a determination command is transmitted so that all symbols displayed on the variable display section 9 are stopped.

Big hit display processing (step S306): When the stop symbol is a combination of big hit symbols, control is performed so that the display control command data of the big hit display is sent to the display control board 80 and the internal state (process flag) ) Is updated so as to shift to step S307. Otherwise, the internal state is changed to step S309.
Update to move to. The combination of the big hit symbols is a combination in which the right and left middle symbols are aligned. Also,
The display control CPU 101 of the game control board 80 displays a big hit on the variable display unit 9 according to the display control command data. The jackpot display is made to notify the player of the occurrence of the jackpot.

Opening process of opening the special winning opening (step S30)
7): Control for opening the special winning opening is started. Specifically, the counter and the flag are initialized, and the solenoid 21 is driven to open the special winning opening.

Processing during opening of the special winning opening (step S30)
8): Control for transmitting display control command data of the special winning opening round display to the display control board 80, processing for confirming establishment of the closing condition of the special winning opening, and the like are performed. If the closing condition of the special winning opening is satisfied, the internal state is updated to shift to step S307 unless the end condition of the big hit gaming state is satisfied. If the jackpot gaming state end condition is satisfied, the internal state is updated to shift to step S309.

Big hit end processing (step S309):
A display for notifying the player that the jackpot gaming state has ended is performed. When the display is completed, the internal flags and the like are returned to the initial state, and the internal state is updated so as to shift to step S300.

A module (step S22 in FIG. 12) that performs processing for transmitting a display control command in the game control program in accordance with the processing of each of the above steps outputs the corresponding display control command data to the output port and Turn on the strobe signal.

FIG. 19A is an explanatory diagram showing an example of the transmission timing of each control command relating to the symbol variation in the variable display section 9. In this embodiment, the C
When starting the symbol variation, the PU 56 sends a variation start command and a symbol designation command indicating a fixed symbol of the left and right middle symbols to the display control board 80.

When the symbol variation is determined, a variation stop command (determination command) is sent to the display control board 80. The display control CPU 101 mounted on the display control board 80 performs display control according to the variation mode specified by the variation start command. The change start command includes information indicating the change time.

FIG. 19B is an explanatory diagram showing an example of the transmission timing of each control command related to the big hit game executed when the display result of the variable display section 9 is a predetermined big hit symbol. In this embodiment, the CPU of the main board 31
56 sends a big hit start command to the display control board 80 when the big hit game starts. After a lapse of a predetermined time, a one-round (1R) designation command is transmitted. Upon receiving the big hit start command, the display control CPU 101 performs display control at the start of the big hit. When the first round designation command is received, the first round display is performed.

Thereafter, the CPU 56 of the main board 31 sequentially sends commands indicating each round to the display control board 80. The CPU of the display control board 80 performs corresponding display control according to these commands.

At the end of the big hit game, the CPU 56 of the main board 31 sends a big hit end command to the display control board 80. Upon receiving the big hit end command, the display control CPU 101 sets the control state to a game waiting state after a predetermined time.

FIG. 20 is a flowchart showing a display control data output process (step S22) in the game control process shown in FIG. In the display control data output process, the CPU 56 determines whether a port A output request has been set (step S581). The port A output request is set in the display control data setting process (step S21) in response to a command output request from a special symbol process process or the like.

If the port A output request has been set, the port A output request is reset (step S58).
2) Output the contents of the port A storage area to the output port (output port A) 571 (step S583). Also,
The port A output counter is incremented by 1 (step S
584), and sets bit 7 of the output port (port B) 572 to 0 (step S585).

If the port A output request has not been set, it is determined whether the value of the port A output counter is 0 (step S586). If the value of the port A output counter is not 0, the value of the port A output counter is 2
Is determined (step S587). Port A
If the value of the output counter is not 2, that is, it is 1, the value of the port A output counter is increased by 1 (step S588).

If the value of the port A output counter is 2, the value of the port A output counter is cleared (step S589), and the output port (output port B) 5 is cleared.
The bit 7 of 72 is set to 1 (step S590).

Bit 7 of output port B is a port for outputting a strobe signal (INT signal) applied to display control board 80. Also, bits 0 to 7 of output port A
Is a port for outputting display control command data.
In this embodiment, the display control data output process shown in FIG. 20 is executed once every 2 ms. Therefore,
By the data output process shown in FIG. 20, when the display control command data is output as shown in FIG. 21, the INT signal goes low (on state) for 4 ms.

Note that the ON period of 4 ms of the INT signal is an example, and the ON period may be shorter or longer. Although the display control command of one byte is illustrated here, the length of the display control command is not limited to one byte, and a display control command longer than one byte may be used.

Next, the game state restoring process will be described. FIG. 22 is a flowchart showing an example of the game state restoration process performed in the power failure restoration process shown in FIG. In this example, if it is necessary to restore the contents of the register, the CPU 56 restores the value stored in the backup RAM to the register (step S61). And
The game state at the time of a power outage is confirmed based on the data stored in the backup RAM. For example, the gaming state can be confirmed by the value of the special symbol process flag corresponding to the progress of the special symbol process.

When the game state is a symbol change (step S62), a display control command indicating a left and right stopped symbol and an error display control command which is an example of a special display command are sent to the display control board 80. Control is performed (steps S63, S64). If the game state is not changing symbols, control is performed to send the display control command and the finalization command indicating the last left and right middle stop symbols before the power failure occurred to the display control board 80 (step S65). , S66). The information about the left and right middle stop symbols transmitted last before the power failure occurs is stored in the backup RAM of the main board 31.

FIG. 23 is an explanatory diagram showing an example of the control state when the power is restored after a power failure has occurred. In FIG. 23, the variable display state is the display control C of the display control board 80.
This is realized by the PU 101.

FIG. 23A shows an example in which the power is restored after a power failure occurs during the symbol change. In this case, at the time of power restoration, a display control command and an error display command indicating a left and right middle stop symbol are transmitted from the main board 31 (FIG. 2).
Steps S63 and S64 in 2). Display control CP
Upon receiving the error display command, U101 performs an error display as a special display on the variable display unit 9. In addition, the game control means on the main board 31 performs a game state in which symbols are changing at the time of restoration from power failure, specifically, all symbol stop waiting processing in the special symbol process processing (step S30 in FIG. 18).
Since the state returns to the state of 6), the determination command is sent to the display control board 80 when the fluctuation period ends.

Upon receiving the confirmation command, the display control CPU 101 displays the left and right stopped symbols while displaying an error. When the next display control command is received, the error display is stopped. The next display control command is, for example, a big hit start command when it is determined to be a big hit, and when it is determined not to be a big hit, the main board 31 at the start of the next symbol change. Is a command indicating the start of fluctuation (a command capable of specifying a fluctuation time). Further, in the case where the game control means sends out a demo screen command when no winning in the start winning port 14 occurs continuously for a predetermined period, the error display is stopped when the demo screen command is received. You may.

In the main board 31, various parameters used at the start of the fluctuation are stored in the backup RAM. Therefore, the display results (fixed symbols) and the like in the fluctuations after the restoration of the power supply are the same as the display results and the like that would have been made in the fluctuations interrupted by the power failure. Therefore, there is no disadvantage to the player.

FIG. 23 (B) shows an example in which the power is restored after a power failure occurs during the big hit game. In this case, when the power is restored, a display control command indicating a left and right middle stop symbol and a confirmation command are transmitted from the main board 31 (steps S65 and S66 in FIG. 22).

In this case, the game control means executes the game state during the jackpot game at the time of restoration of the power failure, specifically, the special winning process opening process or the special winning opening opening process in the special symbol process process (step S308 in FIG. 18). Or S3
07), a display control command relating to the jackpot game indicating the number of rounds and the like is appropriately displayed on the display control board 80.
To send to. The display control CPU 101 can return the control state to the state of the big hit game in response to a command related to the big hit game.

In the main board 31, various parameters during the big hit game (number of times of opening the special winning opening, number of winning balls of the special winning opening, etc.) are stored in the backup RAM. Therefore, since the game state for the player also returns to the state before the power failure, there is no disadvantage to the player.

FIG. 23 (C) shows an example in which the game waiting state is restored after a power failure occurs. In this case, when the power is restored, a display control command indicating the left and right middle stop symbols and a confirmation command are transmitted from the main board 31 (FIG. 22).
In steps S65 and S66). Display control CPU
101 can display on the variable display unit 9 the middle left and right symbols displayed immediately before the occurrence of the power failure based on a display control command indicating the middle left and right symbols. That is, the display state can be returned to the state before the occurrence of the power failure.

Next, the operation of the display control CPU 101 will be described. FIG. 24 is a flowchart showing the operation of the display control CPU 101 in the display control board 80. The display control CPU 101 enters a loop state after initializing output ports and work areas and performing initial processing such as timer setting (step S101). In the initial processing, a timer is set such that a timer interrupt occurs every 500 μs and 2 ms. Therefore, in the loop state, if a timer interruption of 500 μs occurs, a timer interruption processing of 500 μs is performed (step S10).
2) When a 2 ms timer interrupt is applied, a 2 ms timer interrupt process is performed (step S103). In addition, 500μ
The display control command receiving process is performed in the s timer interrupt process, and the display control process is performed in the 2 ms timer interrupt process.

FIG. 25 is a flowchart showing a timer interruption process of 2 ms. When a timer interrupt of 2 ms occurs, the display control CPU 101 performs an initial process such as starting a timer so that the next 2 ms interrupt occurs (step S111), and then performs a display control process process (step S112). Execute.

FIG. 26 is a flowchart showing a display control command reading process executed in the 500 μs timer interrupt process. In the display control command reading process, the display control CPU 101 reads the bit 7 of the input port assigned to the strobe signal (INT signal).
Then, it is determined whether or not the bit 7 is turned on (low level) (step S501). If it is turned on, display control command data is read from the input port assigned to input of the display control command data (step S502). As described above, the INT signal goes low when the CPU 56 of the main board 31 outputs new display control command data.

If the INT signal is off, the display communication counter is cleared (step S506). The display communication counter is used to count the number of times display control command data is received when the INT signal is on.

When the INT signal is on, the received display control command data is transmitted immediately before (500 μs before).
It is determined whether the received command data is the same as the received command data (step S503). If they are not the same, the display communication counter is cleared (step S506). If they are the same, it is checked whether the display communication counter has reached a predetermined maximum value (MAX) (step S504).

If it has not reached the maximum value, the value of the display communication counter is incremented by 1 (step S505). Here, the maximum value is a value larger than a value (3 in this example) for determining that the display control command data has been reliably received, and is used for the purpose of counting the number of receptions in 4 ms, for example. Can be

Next, the display control CPU 101 checks whether or not the value after the display communication counter has become "3" (step S507). If it is "3", the received data is stored in the received command storage area (step S509). Then, the received data is stored in the work area (step S510). The data stored in the work area is used in step S503 in the next interrupt processing.

As described above, in this embodiment, when the same display control command data is received, for example, three times in succession, the display control CPU 101 determines that the display control command has been received, and sets the communication end flag. set.
Then, when the communication end flag is set, processing such as pattern change and display switching of the background / character is performed based on the display control command stored in the received command storage area.

FIG. 27 shows a display control process in the timer interrupt process shown in FIG. 25 (step S112).
It is a flowchart which shows. In the display control process, step S7 is performed according to the value of the display control process flag.
Any one of the processes from 20 to S870 is performed. In each process, the following processes are performed.

Display control command reception waiting processing (step S720): The contents of the work area in which the reception command is set are read out according to the ON of the communication end flag, and
It is confirmed whether a display control command or the like capable of specifying the fluctuation time has been received.

Reach operation setting processing (step S75)
0): Determine which pattern of a plurality of variation modes corresponding to a received display control command (for example, a command specifying a reach type) that can specify the variation time is used.

All symbols change start processing (step S78)
0): Control is performed so that the change of the middle left and right symbols is started.

Symbol change processing (step S810): Controls the switching timing of each change state (change speed, background, character) constituting the change pattern, and monitors whether or not the final command is sent from the main board 31. I do. Also, stop control of the left and right symbols is performed.

All symbols stop wait setting processing (step S84)
0): At the end of the fluctuation time, if a display control command instructing to stop all the symbols has been received, the control of stopping the fluctuation of the symbols and displaying the final stopped symbol (fixed symbol) is performed.

Big hit processing (step S870): After the end of the fluctuation time, the control of the big hit notification display, the round display during the big hit game, the certain variable big hit display, or the normal big hit display is performed.

FIG. 28 is a flowchart showing an example of the display control command reception waiting process (step S720). In the display control command reception waiting process, the display control CPU 101 confirms whether or not a display control command capable of specifying the fluctuation time has been received (step S751).
If it has been received, the error display on the variable display section 9 is erased (step S752), and the value of the display control process flag is set to a value corresponding to the reach operation selection process (step S753). Therefore, the reach operation selection process is performed thereafter.

When the display control CPU 101 receives the display control command indicating the left and right middle stop symbol (step S754), it stores information indicating the left and right middle stop symbol (step S755). If an error display command has been received (step S756), the variable display unit 9
Is displayed (step S757). When the confirmation command is received (step S758), the stored stop symbol is displayed on the variable display unit 9 (step S759).

When a command transmitted during the big hit game is received (step S760), the error display on the variable display section 9 is deleted (step S761), and the value of the display control process flag corresponds to the big hit processing. The value is set (step S762). Therefore, the big hit center is executed thereafter. The command transmitted during the big hit game is, for example, a command indicating the number of rounds or a command indicating the number of winning prize holes.

Also, when a demo screen command is received (step S763), the display control CPU 101
The error display is deleted (step S764). When receiving the demonstration screen command, the display control CPU 101 deletes the error display and displays the demonstration screen on the variable display unit 9.

Since the display control CPU 101 performs the same processing at the time of normal power-on and at the time of restoration from a power failure, at the time of restoration from a power failure, the display control process flag is initialized, and the display control process is executed by the display control command. It will be in the state of waiting for reception. As shown in FIG. 23A, when a power failure occurs during a symbol change and the power is restored from the power failure, an error display command and a display control command indicating a stopped symbol in the left and right are transmitted from the main board 31. . Then, when the fluctuation time has elapsed, a confirmation command is transmitted.

In the display control board 80, the display control C
When the PU 101 confirms that the display control command indicating the left and right middle stop symbol has been received in step S754 shown in FIG. 28, the PU 101 stores the information indicating the stop symbol, and stores the information in step S754.
If it is confirmed at 756 that an error display command has been received, an error is displayed. Then, when it is confirmed in step S758 that the confirmation command has been received, the stored stop symbol is displayed. Here, the error display is not deleted. The error display is deleted when a display control command capable of specifying a fluctuation time, a command during a big hit game, or the like is received (steps S752, S761).

[0157] Therefore, when a power failure occurs and the gaming state is recovered, the error display is continuously displayed on the variable display section 9 for a while. Therefore, the player or the like can easily recognize that the power failure has occurred and the gaming state has been recovered. Then, the information on the stop symbols of the left and right middle symbols received from the main board 31 at the start of the fluctuation before the occurrence of the power failure has been erased on the display control board 80 due to the power failure, but has been reset from the main board 31 at the time of recovery from the power failure. Since the command indicating the stop symbol of the middle symbol is transmitted, the right and left middle stop symbols can be displayed on the variable display section 9 at a predetermined timing.

When a power failure occurs during the big hit game and the power is restored from the power failure, as shown in FIG. 23B, a display control command and a decision command indicating the left and right middle stop symbols are transmitted from the main board 31. Is done. Then, in the game control means on the main board 31, the game state is restored to the state at the time of the occurrence of the power failure, so that the control during the big hit game is resumed and the display control command relating to the big hit game is transmitted. On the display control board 80, when the display control CPU 101 receives the display control command related to the big hit game, the display control process flag sets the value of the display control process flag to the value of the big hit processing, and returns the control state to the big hit processing (step S762). . Since a display control command indicating the left and right middle stop symbols is transmitted when the power failure is restored, the display control CP
U101 can display a regular left and right middle stop symbol on the variable display unit 9.

Then, when a power failure occurs in the game waiting state and the power is restored, as shown in FIG. 23C, a display control command and a fixation command indicating the left and right middle stop symbols from the main board 31. Is sent. Display control C
The PU 101 stores the information indicating the stop symbol when confirming that the display control command indicating the left and right middle stop symbol has been received in step S754, and displays the stop symbol in the variable display unit when confirming that the confirmation command has been received in step S758. 9 is displayed. As described above, since the display control command indicating the left and right middle stop symbols is transmitted when the power failure is restored, the display control CPU 101 can display the normal left and right middle stop symbols on the variable display unit 9.

FIG. 29 is an explanatory diagram showing an example of the display state of the variable display section 9 under the control described above. FIG. 29 (A)
As shown in FIG. 29, when a power failure occurs when the symbol fluctuates and then the symbol is restored, an error is displayed on the variable display section 9 as shown in FIG. Then, when the change command is received from the main board 31 after the fluctuation period ends, a stop symbol is displayed. Thereafter, in this example, when a command indicating the start of fluctuation for the next fluctuation start is received, the error display is erased.

Next, the operation of the prize ball control means when a power failure occurs will be described. FIG. 30 is a block diagram showing an example of a configuration around the CPU 371 for controlling the prize ball for power supply monitoring and power supply backup. As shown in FIG. 30, the voltage drop signal from the first power supply monitoring circuit (first power supply monitoring means) mounted on the power supply board 910 is transmitted to the prize ball control CP.
It is input to the interrupt terminal (IRQ terminal) of U371.
Therefore, the prize ball control CPU 371 can confirm the occurrence of power interruption by the interrupt processing.

While power is not being supplied from the + 5V power supply which is the driving power supply for the prize ball control CPU 371 and the like, at least a part of the built-in RAM of the prize ball control CPU 371 uses the backup power supplied from the power supply board 910 as a backup. Backed up by connecting to the terminal,
The contents are preserved even if the power to the gaming machine is turned off. When the + 5V power supply is restored, the initial reset circuit 935
Generates a reset signal from the CPU for controlling the prize ball.
371 returns to the normal operating state. At that time, since the necessary data is backed up, it is possible to return to the gaming state at the time of the occurrence of the power failure when recovering from a power failure or the like.

In the configuration shown in FIG. 30, the prize ball control board 37
Is equipped with a second power supply monitoring circuit 933. In this example, in the second power supply monitoring circuit 933, the power supply monitoring IC 934 monitors the + 30V power supply voltage which is the same as the power supply voltage monitored by the first power supply monitoring circuit on the power supply board 910, and the voltage value is set to a predetermined value. When the value falls below the value, a low level voltage drop signal is generated. Second power supply monitoring circuit 933
Is provided, the second power supply monitoring circuit 933 is provided.
Detection voltage (voltage at which a voltage drop signal is output)
Is lower than the detection voltage of the first power supply monitoring circuit mounted on the power supply board 910.

The voltage drop signal from the second power supply monitoring circuit 933 is logically ORed with the initial reset signal from the initial reset circuit 935, and then input to the reset terminal of the prize ball control CPU 371. Therefore, the CPU for controlling the prize ball
371 indicates a reset state (non-operating state) when the initial reset signal from the initial reset circuit 935 is at a low level, or when the voltage drop signal from the second power supply monitoring circuit 933 is at a low level. State).

FIG. 31 shows the main board 31 to the prize ball control board 3.
7 is an explanatory diagram showing an example of a bit configuration of a prize ball control command transmitted to No. 7; FIG. As shown in FIG. 31, the upper 4 bits in one byte are used as a control designating section, and the lower 4 bits are used as an area indicating the number of prize balls.

As shown in FIG. 32, if the bits 7, 6, 5, and 4 are "0, 1, 0, 0" in the control designation section, it indicates that the command is a payout number designation command. ,
"0, 1" indicates a payout designation command.
The payout number designation command is sent to the prize ball control board 37 immediately after the CPU 56 of the main board 31 detects a winning.

Bits 7, 6, 5, and 4 are "1, 0, 0,
The ball-out designation command of “0” is transmitted from the main board 31 when it is detected that there is no more supply ball. The firing stop designation command in which the bits 7, 6, 5, and 4 are "1, 0, 0, 1" indicates that the surplus ball tray 4 is full and the full switch 48 is turned on (the full tank state). (When the flag is turned on).

The award ball control command is output from the main board 31 to the award ball control board 37 as 1-byte (8 bits: award ball control commands D7 to D0) data. The winning ball control commands D7 to D0 are output in positive logic. When the award ball control commands D7 to D0 are output, a negative logic award ball control INT signal is output.

In this embodiment, as shown in FIG. 33, when the prize ball control commands D7 to D0 are output from the main board 31, the prize ball control INT signal goes low for 5 μs or more. The prize ball control INT signal is transmitted to the prize ball control board 37.
Is connected to the interrupt terminal of the CPU 371 for controlling the prize ball. Therefore, when there is an interrupt, the award ball control CPU 371 transmits the award ball control commands D7 to D0 to the main board 31.
And recognizes that it has been sent from the CPU, and performs a prize ball control command receiving process in the interrupt process.

Note that the command configuration shown in FIG. 31 is an example, and another configuration may be used. For example, the upper and lower bits in one byte may be reversed from the configuration shown in FIG.

FIG. 34 is a flowchart showing the main processing of the award ball control CPU 371. In the main processing,
The winning ball control CPU 371 first performs an initial value setting process such as clearing the RAM area (step S701).
If data is set in the RAM area (backup RAM area) of the built-in RAM where the power is backed up, those areas are not cleared. After that, in this embodiment, the CPU 371 for controlling the prize ball.
Shifts to a loop process for checking the monitoring of the timer interrupt flag (step S702).

In the initialization processing of step S701, if the value of the total number storage described later is not 0, the non-backup RAM area is cleared. Then, setting for restarting the prize ball is performed. For example, a flag during processing of a prize ball is set. If the backup RAM area is an area irrespective of the number of prize balls, those addresses may be designated and cleared. Furthermore, in addition to these processes, initial settings of a timer register provided in the CPU for controlling a prize ball 371 so that a timer interrupt is periodically performed every 2 ms (setting that the timeout is 2 ms and setting of the repetition timer operating) ) Is performed. That is, a process of activating a timer interrupt and a process of setting a timer interrupt interval are executed.

Therefore, in this embodiment, the internal timer of the award ball control CPU 371 is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. Then, as shown in FIG. 35, when a timer interrupt occurs, the CPU 371 for controlling the prize ball.
Sets the timer interrupt flag (step S71)
1).

The prize ball control CPU 371 proceeds to step S7.
In 02, when it is detected that the timer interrupt flag is set, the timer interrupt flag is reset (step S703), and a prize ball control process is executed (step S705). With the above control, in this embodiment, the prize ball control process is started every 2 ms. In this embodiment, only the flag is set in the timer interruption processing, and the winning ball control processing is executed in the main processing. However, the winning ball control processing may be executed in the timer interruption processing.

FIG. 36 is an explanatory diagram showing an example of use of a RAM built in the CPU 371 for controlling a prize ball. In this example,
A total number storage (for example, 2 bytes) is formed in the backup RAM area. The total number storage stores the total number of payouts instructed from the main board 31 side.

FIG. 37 is a flowchart showing a prize ball control command receiving process by the interrupt process. The award ball control INT signal from the main board 31 is input to the interrupt terminal of the award ball control CPU 371. Therefore, when the award ball control INT signal from the main board 31 is turned on, the award ball control CP
U371 is interrupted, and the reception processing of the award ball control command shown in FIG. 37 is started.

In the award ball control command receiving process, the award ball control CPU 371 first reads 1-byte data from the input port assigned to the input of the award ball control command data (step S852). If the read data is a payout number instruction command (step S8)
53), the number specified by the payout number instruction command is added to the total number storage (step S855). Otherwise, a communication end flag is set (step S85).
4). In this example, the communication end flag is a flag indicating that a command other than the payout number instruction command has been received.

As described above, the CPU 371 for controlling the prize ball mounted on the prize ball control board 37 is
The number of award balls included in the payout number instruction command sent from 6 is stored in the backup RAM area (total number storage).

FIG. 38 shows a prize ball control process (step S71).
It is a flowchart which shows 1). In the prize ball control processing, the prize ball control CPU 371 checks whether or not the total number storage is not 0 (step S511). If the total number storage is not 0, the award ball control CPU 371 performs an award ball payout process (step S512). In the prize ball payout process, if the payout motor 289 is not turned on, it is turned on, and the detection output of the prize ball count switch 301A is used to confirm whether or not the game balls have been paid out. When it is confirmed that one payout has been made (step S513), the value of the total number storage is decremented by one (step S513).
514). When the value of the total number storage becomes 0 (step S515), the payout motor 289 is turned off (step S516).

The contents of the total number storage are maintained by the backup power supply of the power supply board 910 for a predetermined period even if the power of the gaming machine is turned off. Therefore, when the power is restored during the predetermined period, the award ball control CPU 371 can continue the award ball payout process based on the contents of the total number storage.

When the power is turned on, the CPU 371 for controlling the prize ball can determine whether to perform the normal initialization processing or restore the state during the prize ball simply by checking the data in the backup RAM area. That is, with a simple judgment,
The prize ball processing can be restarted for the unpaid prize balls.

Note that the prize ball control CPU 371 manages the number of prize balls instructed from the main board 31 as a total number in the total number storage, but for each prize ball number (for example, 15, 10 or 6).
). For example, a number counter corresponding to each prize ball number is provided, and when a payout number designation command is received, the number counter corresponding to the number designated by the command is incremented by one. When the payout of each prize ball is completed, the corresponding number counter is decremented by one. Also in this case, each number counter is formed in the backup RAM area. Therefore, even if the power of the gaming machine is turned off, if the power is restored during the predetermined period, the prize ball control CPU 371 can continue the prize ball payout process based on the content of each number counter.

FIG. 39 shows that the CPU 371 for controlling the prize ball controls the first
7 is a flowchart showing a power failure occurrence interrupt process executed in response to an interrupt from a power monitoring unit. Power supply board 901
When the power supply monitoring IC 902 detects a drop in the power supply voltage, the voltage drop signal indicates a voltage drop, and the power failure occurrence interrupt processing is started. In the power failure occurrence interruption processing, the prize ball control CPU 371 sets interruption prohibition (step S
801), the RAM access is prohibited (step S802), and a halt instruction (HALT instruction) is issued (step S803).

That is, the CPU itself is set to a state where it does not operate except for reset release or occurrence of an interrupt. Therefore,
Before being externally disabled by a reset signal from the power supply monitoring IC 934 shown in FIG. 30, the internal operation is stopped. Thus, the operation of the award ball control CPU 371 is reliably stopped when the power is turned off. As a result, the RAM access prohibition control and the operation stop control described above can reliably prevent the contents of the RAM from being destroyed due to an abnormal operation that may occur as the power supply voltage decreases. .

FIG. 40 is a flowchart showing a part of the initialization process (step S701) executed by the CPU 371 for controlling the prize ball when the power is turned on. When the power is turned on or the power is restored, the CPU 371 for controlling the prize ball
First, it is checked whether the value of the total number storage formed in the backup RAM area is not 0 (step S901). If it is 0, it means that there were no unpaid prize balls at the time of the previous power-off, so that normal initialization processing is performed. That is, the register and the entire RAM area are cleared (step S903), and the stack pointer is initialized (step S904).

If the value of the total number storage is not 0, an address is designated to clear the register and the non-backup RAM area (step S905). Then, setting for restarting the prize ball is performed. For example, a flag during processing of a prize ball is set (step S906). If the backup RAM area is an area irrespective of the number of prize balls, those addresses may be designated and cleared.

As described above, the CPU 371 for controlling the prize ball
When the power is turned on, it is possible to determine whether to perform the normal initial setting process or to restore the state during the prize ball only by checking the data in the backup RAM area. In other words, the prize ball processing can be restarted for the unpaid prize balls by a simple judgment.

In this embodiment, the prize ball control C
PU371 is a maskable external interrupt terminal (IRQ terminal)
Although the first voltage drop signal from the power supply board (voltage drop signal from the first power supply monitoring means) is detected, the first voltage drop signal is introduced to the non-maskable interrupt interrupt terminal (NMI terminal). Is also good. In that case, the power failure occurrence processing shown in FIG. 39 is executed by the NMI processing. Further, the first voltage drop signal may be detected through the input port. In that case, the input port is monitored in the main processing executed by the award ball control CPU 371.

In the above embodiment, the first voltage drop signal from the power supply board 910 was input to the interrupt terminals of the main board 31 and the prize ball control board 37. However, as shown in FIG. On the control board 37, a delay circuit 936 may be provided before the interrupt terminal. In such a configuration, the timing at which the CPU 56 of the main board 31 recognizes that the first power supply monitoring means has detected the voltage drop is determined by the timing at which the CPU 371 for controlling the prize ball of the prize ball control board 37 recognizes. Faster than.

CPU 56 and CPU 371 for controlling prize balls
Perform the power-off processing in response to the first voltage drop signal, respectively.
The power-off process is started earlier than 1. That is, the game control process by the CPU 56 stops earlier than the stop of the prize ball control process by the CPU 371 for award ball control. Then, the prize ball control command transmitted during the game control process is:
Even when the power is cut off, the prize ball control CP
It is received at U371. The prize ball control CPU 371 stores the number of prize balls based on the received prize ball control command in the backup RAM area, so that the prize ball number is retained even during a power failure and is processed after restoration of the power failure. Therefore, the delay circuit 936
Is provided, the prize ball payout based on the winning detected by the game control means is more reliably performed. Therefore,
It is possible to more effectively prevent the disadvantage from being given to the player.

Also, the first voltage drop signal may be delayed by software without providing the delay circuit 936. For example, the award ball control CPU 371 does not immediately start the interrupt processing when an interrupt based on the first voltage drop signal occurs, but starts a timer and continues the main processing. When the timer times out, the processing of steps S801 to S803 shown in FIG. 39 is executed.

In the above-described embodiment, the case where the RAM is used as the storage means has been described.
Any other storage means than the RAM may be used as long as the storage means can be electrically rewritten.

Further, here, the prize ball control means has been exemplified as a game device control means other than the game control means.
The display control means, the sound control means, and the lamp control means may also be provided with a second power supply monitoring means.

The pachinko gaming machine 1 of each of the above embodiments
Is a first-class pachinko gaming machine in which a predetermined game value can be given to a player when a stop symbol of a special symbol variably displayed on the variable display portion 9 based on a start winning prize is a predetermined symbol combination. However, if there is a prize in a predetermined area of the electric accessory that is opened based on a winning start, a second-type pachinko gaming machine that can give a predetermined game value to a player, or is variably displayed based on a starting prize. The present invention can be applied to a third-type pachinko gaming machine in which a predetermined right is generated or continued when there is a prize for a predetermined electric accessory which is opened when a symbol combination of a predetermined symbol is released.

[0195]

As described above, according to the present invention, the gaming machine is controlled by the gaming machine control microcomputer based on the detection output of the power supply monitoring means for monitoring the decrease of the power supply voltage. The power-off process is executed and the halt state is set at the final part of the power-off process, so that the contents of the storage means may be destroyed due to a decrease in the power supply voltage. Can be reliably prevented,
There is an effect that data can be surely saved when the power is turned off.

In the case where the processing at the time of power-off includes the processing of saving the register, when the game state is restored when the power is restored, all the data necessary for the return can be saved.

When the processing at the time of power-off includes processing for preventing access to the storage means, it is possible to more reliably prevent data in the storage means from being destroyed at the time of power-off.

A detection output of the power supply monitoring means is connected to an interrupt terminal of the gaming machine control microcomputer, and the gaming machine control microcomputer is configured to execute a power-off process based on an input to the interrupt terminal. In this case, the power-off process can be executed reliably without increasing the load on the software.

A second power supply monitoring means for detecting a voltage drop of the power supply voltage after a predetermined period of time when the power supply monitoring means detects the voltage drop is provided.
In the case where the system is configured to be reset during the halt state in response to the input of the detection output from the second power supply monitoring means, the operation of the microcomputer is also stopped externally by the system reset. More reliable data storage can be performed at the time of disconnection.

The power supply monitoring means is provided on a power supply board which is provided separately from the gaming machine control board and generates each voltage used in the gaming machine control board, and the second power supply monitoring means is provided on the gaming machine control board. When provided, the detection output can be supplied to the plurality of gaming machine control boards from the power supply monitoring means of the power supply board, so that the cost of the gaming machine does not increase so much.

The power-off processing includes processing for storing check data obtained as a result of an operation related to the storage contents of the storage means in the storage means, and the gaming machine control microcomputer performs a check based on the check data when the power is restored. If the check result is normal, if the game state return control is configured, it is possible to check whether the data has been destroyed based on the check data when the power is restored, and the saved data Can be improved in reliability.

If the gaming machine control microcomputer is configured to execute the initialization process if the check result is not normal, the gaming state may be restored based on abnormal data. Is prevented.

The power supply monitoring means and the second power supply monitoring means monitor the same power supply voltage. If the detection voltage of the second power supply monitoring means is set lower than the detection voltage of the power supply monitoring means, The difference between the timing at which the power supply monitoring means generates the detection output and the timing at which the second power supply monitoring means generates the detection output can be reliably set to a desired predetermined period.

The power supply voltage monitored by the power supply monitoring means is the power supply voltage immediately after the conversion from AC to DC. When the power supply voltage drops to a predetermined value, the power supply monitoring means determines that the power supply voltage has dropped. In this case, the monitoring range can be expanded for the voltage required by the gaming machine control microcomputer, and more precise monitoring can be performed.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is a front view of the gaming board of the pachinko gaming machine as viewed from the front.

FIG. 3 is a rear view of the pachinko gaming machine as viewed from the rear.

FIG. 4 is a block diagram showing a circuit configuration example of a game control board (main board).

FIG. 5: C for power supply monitoring and power supply backup
FIG. 3 is a block diagram illustrating a configuration example around a PU.

FIG. 6 is a block diagram illustrating a circuit configuration example of a display control board.

FIG. 7 is a block diagram illustrating a circuit configuration example of a winning ball control board.

FIG. 8 is a block diagram illustrating a configuration example of a power supply board.

FIG. 9 is a flowchart illustrating a main process executed by a CPU on a main board.

FIG. 10 is a flowchart illustrating initialization processing.

FIG. 11 is a flowchart showing a 2 ms timer interrupt process.

FIG. 12 is a flowchart showing a game control process.

FIG. 13 is a flowchart showing a power failure occurrence interruption process.

FIG. 14 is a flowchart illustrating a power failure recovery process.

FIG. 15 is an explanatory diagram for describing a backup parity data creation method.

FIG. 16 is an explanatory diagram showing a configuration example of display control command data.

FIG. 17 is an explanatory diagram illustrating a configuration example of a display control command.

FIG. 18 is a flowchart showing an example of a special symbol process processing program.

FIG. 19 is an explanatory diagram illustrating an example of transmission timing of each control command from the main board.

FIG. 20 is a flowchart illustrating display control data output processing.

FIG. 21 is a timing chart showing a state of output of display control command data.

FIG. 22 is a flowchart illustrating an example of a game state restoration process.

FIG. 23 is an explanatory diagram illustrating an example of a control state when the power is restored after a power failure occurs.

FIG. 24 is a flowchart illustrating main processing executed by a display control CPU.

FIG. 25 is a flowchart showing a 2 ms timer interrupt process of the display control CPU.

FIG. 26 is a flowchart showing a display data reading process of the display control CPU.

FIG. 27 is a flowchart showing a display control process executed by the display control CPU.

FIG. 28 is a flowchart showing a display control command reception waiting process in the display control process process.

FIG. 29 is an explanatory diagram illustrating an example of a display state of the variable display unit.

FIG. 30 is a block diagram showing an example of a configuration around a CPU for controlling a prize ball for power supply monitoring and power supply backup.

FIG. 31 is an explanatory diagram showing a configuration example of a winning ball control command.

FIG. 32 is an explanatory diagram showing a bit configuration of a winning ball control command.

FIG. 33 is a timing chart showing how the award ball control command data is output.

FIG. 34 is a flowchart showing a main process executed by a winning ball control CPU.

FIG. 35 is a flowchart showing a timer interrupt process of a winning ball control CPU.

FIG. 36 is an explanatory diagram showing an example of a configuration of a RAM in the winning ball control means.

FIG. 37 is a flowchart showing a command receiving process of the winning ball control CPU.

FIG. 38 is a flowchart showing a prize ball control process.

FIG. 39 is a flowchart showing a power failure generation process executed by the winning ball control CPU.

FIG. 40 is a flowchart illustrating an example of initialization processing of a winning ball control CPU.

FIG. 41 is a block diagram showing another configuration example around a CPU for controlling a prize ball for power supply monitoring and power supply backup.

[Explanation of symbols]

 1 Pachinko gaming machine 31 Main board 37 Prize ball control board 53 Basic circuit 56 CPU 80 Display control board 101 Display control CPU 371 Prize ball control CPU 902, 904 Power supply monitoring ICs 903, 933 Second power supply monitoring circuit 910 Power supply substrate

Claims (10)

[Claims] 1. A game machine capable of providing a game result value to a player as a result of performing a predetermined game, wherein a game immediately before power-off is held when power is turned on, based on the held data. It is possible to perform a game state return control for returning the state, and to monitor a decrease in the power supply voltage by monitoring a game apparatus control board on which a game apparatus control unit for controlling a game apparatus provided for the game is mounted. Power supply monitoring means for performing a predetermined detection output at the time of a voltage drop, wherein the gaming device control means stores a gaming device control microcomputer, and fluctuation data generated when the gaming device control microcomputer performs control, and a power supply. Storage means capable of being in a storage content holding state in which storage contents immediately before power-off are held for at least a predetermined period from the time of power-off. A computer configured to execute predetermined power-off processing for returning to a game state based on a detection output of the power monitoring means, and to set a halt state at a final part of the power-off processing. . 2. The gaming machine according to claim 1, wherein the power-off processing includes register save processing. 3. The gaming machine according to claim 1, wherein the power-off processing includes processing for preventing access to the storage means. 4. A power supply monitoring unit detects a voltage drop of a predetermined potential power supply, and a detection output of the power supply monitoring unit is connected to an interrupt terminal of a gaming machine control microcomputer on a gaming machine control board, 4. The gaming machine according to claim 1, wherein the microcomputer executes a power-off process based on an input to the interrupt terminal. 5. A power supply monitoring means for detecting a voltage drop of the power supply voltage after a predetermined period of time when the power supply monitoring means detects the voltage drop, wherein the gaming machine control microcomputer comprises: a second power supply monitoring means. 5. The system is reset during a halt state in response to the input of a detection output from the controller.
The gaming machine described. 6. The power supply monitoring means is provided on a power supply board which is provided separately from the gaming machine control board and generates each voltage used in the gaming machine control board. The gaming machine according to claim 5, wherein the gaming machine is provided on a substrate. 7. The power-off processing includes processing for storing check data obtained as a result of an operation related to the storage contents of the storage means in the storage means. 7. The gaming machine according to claim 1, wherein a check based on the game is performed, and if the check result is normal, a game state return control is performed. 8. The gaming machine control microcomputer,
8. The gaming machine according to claim 7, wherein an initialization process is executed if the check result is not normal. 9. The power supply monitoring means and the second power supply monitoring means monitor the same power supply voltage, and the detection voltage of the second power supply monitoring means is lower than the detection voltage of the power supply monitoring means. The gaming machine according to claim 6. 10. The power supply voltage monitored by the power supply monitoring means is:
10. The gaming machine according to claim 5, wherein the power supply voltage is a power supply voltage immediately after conversion from AC to DC, and wherein the power supply monitoring means determines that the power supply voltage has dropped when the power supply voltage drops to a predetermined value.