JP2001100658A - Method for manufacturing electro-optic device and electro-optic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate the planarization of pixel electrodes of an electro-optic device, such as a liquid crystal display device, and to suppress the degradation in manufacturing yield by accompanying a planarization treatment. SOLUTION: TFTs (30) are formed on a TFT array substrate (10). A dense insulating film is formed thereon by subjecting the film to a thermal baking treatment at a high temperature above 700 deg.C and is then planarized by a polishing treatment, by which a first interlayer insulating film (4) is formed. Grooves (4a) are dug in this first interlayer insulating film in the regions going to be formed with data lines (6a). The data lines (6a) are embedded in these grooves so as to be connected to the source of the TFTs through contact holes (5). The data lines are formed of a low melting metal having an excellent time constant. Further, a second layer insulating film (7) is formed thereon and the pixel electrodes (9a) are formed thereon so as to be connected to the drains of the TFTs via the contact holes (8).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an electro-optical device and a technical field of the electro-optical device, and more particularly, to a method of manufacturing a thin film transistor between a substrate and a pixel electrode.
sistor: hereinafter, appropriately referred to as TFT), thin-film diode (T
An electro-optic type in which pixel switching elements such as hin film diodes (hereinafter, appropriately referred to as TFDs) and wirings such as data lines, scanning lines, and capacitor lines connected thereto are stacked and formed via an interlayer insulating film. It belongs to the technical field of the device manufacturing method and the electro-optical device.

[0002]

2. Description of the Related Art Conventionally, in this type of electro-optical device, an electro-optical material such as liquid crystal is sandwiched between a pair of substrates, and one substrate is provided with a plurality of pixel electrodes in a matrix.
Here, if there is a step or unevenness on the surface of the pixel electrode, a display defect due to a liquid crystal alignment defect or the like is caused. More specifically,
Such steps and irregularities become steps and irregularities on the surface of the alignment film provided on the pixel electrode surface, causing uneven rubbing at the time of the rubbing treatment, and causing poor alignment of the liquid crystal defined by the rubbing treatment. Eventually, the image display quality is degraded. Usually, in order to minimize rubbing unevenness due to such steps and unevenness, rubbing processing is performed along the largest step (for example, a step along the data line) determined depending on the device configuration in the pixel portion. Is done. However, when the rubbing process is performed in this manner, especially in the case of a double-plate type color projector using three electro-optical devices in combination as three light valves, three light valves are used to combine three lights. Because one of the light valves is used in reverse, the color unevenness due to the rubbing unevenness that is invisible to a single light valve is increased by combining the three light valves, and the visible color is increased. This leads to an uneven situation.

For this reason, it is preferable to planarize the surface of the uppermost interlayer insulating film, which serves as a base film for a pixel electrode, on one substrate. That is, if the uppermost interlayer insulating film is planarized, rubbing unevenness can be basically reduced. Further, also in the case of the above-mentioned double-plate type color projector, a rubbing direction which can make the tendency of uneven rubbing the same between one light valve used in reverse and two other light valves is selected. Because of this, it is also possible to suppress the above-described effect of increasing display unevenness during photosynthesis.
In addition, if an alignment film having no steps is provided, good vertical alignment is possible, which leads to high-contrast display.

Therefore, conventionally, the surface of the uppermost interlayer insulating film is formed from a flattening film obtained by spin-coating an organic film such as an organic SOG (Spin On Glass) or an organic polyimide film.

[0005]

However, in the case of flattening by the technique of spin-coating an organic film, there is a fundamental problem that the organic film is significantly deteriorated by light during use of the apparatus. In particular, in the case of a projector application using strong light, this problem becomes very serious.

[0006] Therefore, CMP (Chemical Mechanical Polishing) used in the technical field of semiconductor manufacturing equipment and the like.
g) It is conceivable to apply a polishing technique such as processing to planarize an interlayer insulating film in this type of electro-optical device.

However, if the interlayer insulating film in this type of electro-optical device is polished by a CMP process or the like, cracks occur in the interlayer insulating film at the time of polishing, and the defective product rate increases. is there. Furthermore, since the polishing amount is different between the vicinity of the center and the vicinity of the periphery of the mother substrate, it is difficult to perform uniform film thickness control, and it is finally difficult to manufacture a device of a constant quality. There are points. In particular, in the case of a high-definition electro-optical device, the driving frequency becomes extremely high and the wiring pitch becomes finer. Therefore, a data line for supplying an image signal is generally made of Al ( Aluminum) film. However, since Al is a low melting point metal, heat treatment at 500 ° C. or higher cannot be performed after the formation of the data line. Therefore, a dense interlayer insulating film sufficiently subjected to thermal firing at a higher temperature cannot be generally formed. As a result, since the non-dense interlayer insulating film has to be polished, the above-mentioned problem that cracks occur during polishing and the problem that uniform thickness control is difficult are very serious problems in practical use. Becomes

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and provides a high-quality image in which a pixel electrode can be relatively easily planarized and a reduction in manufacturing yield due to the planarization process can be suppressed. It is an object to provide a method for manufacturing an electro-optical device capable of displaying and an electro-optical device manufactured by the method.

[0009]

In order to solve the above-mentioned problems, a method of manufacturing an electro-optical device according to the present invention includes a step of forming a pixel switching element on a substrate, and a step of forming one pixel above the pixel switching element. A step of forming an interlayer insulating film, a step of flattening the one interlayer insulating film, a step of forming a groove in the flattened interlayer insulating film, and a step of contacting one contact hole in the groove. Forming a data line so as to be connected to one terminal of the pixel switching element,
Forming another interlayer insulating film on the data line; and forming a pixel electrode on the other interlayer insulating film so as to be connected to another terminal of the pixel switching element via another contact hole. And a step.

According to the method of manufacturing an electro-optical device of the present invention, first, a pixel switching element such as a TFT element or a TFD element is formed on a substrate, and an interlayer is provided above the pixel switching element. An insulating film is formed.
Therefore, at this point, a step is formed on the surface of the one interlayer insulating film due to the pixel switching element and its wiring existing between the substrate and the one interlayer insulating film. Subsequently, one interlayer insulating film is planarized. Next, a groove is formed in a region where a data line is to be formed in one planarized interlayer insulating film by etching or the like. A data line is formed in the groove so as to be connected to one terminal (for example, a source in a TFT) of the pixel switching element via one contact hole. Next, another interlayer insulating film is formed on the data line. Finally, another terminal (for example, another terminal) of the pixel switching element is formed on another interlayer insulating film thus formed through another contact hole.
A pixel electrode is formed so as to be connected to the drain of the TFT).

As described above, even when a data line is formed from a low melting point metal such as Al after flattening one interlayer insulating film, the data line is not formed for one interlayer insulating film. The heat treatment can be performed irrespective of the melting point of the material. That is, it is possible to form one dense interlayer insulating film by thermal firing performed before forming the data lines. As a result, even if a single dense interlayer insulating film is flattened by polishing or the like, the possibility of cracks being generated by polishing or the like is reduced, and finally the yield of non-defective devices can be improved. In addition, since one dense interlayer insulating film is flattened, the difference in the amount of polishing between the vicinity of the center and the periphery of the mother substrate is reduced,
The thickness of one interlayer insulating film after planarization can be made uniform within the mother substrate surface. In addition, since the data line is buried in the groove formed in the thus planarized one interlayer insulating film, even after the data line is formed, the entire surface of the one interlayer insulating film including the data line is formed. The step due to the existence of the data line hardly occurs. Therefore, a step in another interlayer insulating film formed thereon is further reduced as compared with the case where the data line is not embedded in the groove as described above.

As a result, according to the method of manufacturing an electro-optical device of the present invention, a pixel electrode can be relatively easily flattened, and a material having an excellent time constant can be used for a high-definition electro-optical device. It is possible to suppress a decrease in manufacturing yield due to the planarization process while using the data line. As a result, it is possible to manufacture an electro-optical device capable of displaying a particularly high-definition image using a pixel electrode having almost no step.

In one aspect of the method of manufacturing an electro-optical device according to the present invention, in the step of forming the groove, the etching controlled in time such that the depth of the groove corresponds to the thickness of the data line is performed. It is applied to one interlayer insulating film.

According to this aspect, the depth of the trench dug in the flattened interlayer insulating film is controlled by the time management of the etching so as to correspond to the thickness of the data line. That is, ideally, a groove having a depth to bury the data line without any step is dug by the etching. As a result, the step after forming the data line can be reduced by the relatively easy control of the time management of the etching.
From the viewpoint of improving the accuracy of controlling the depth of the groove, dry etching is preferable, but wet etching can also be used.

In another aspect of the method of manufacturing an electro-optical device according to the present invention, in the step of forming the one interlayer insulating film, a lower insulating film which is hardly etched by a predetermined type of etchant is formed. Forming the one interlayer insulating film having a multilayer structure by forming an upper insulating film having a thickness corresponding to the thickness of the data line, which is relatively easily etched on the lower insulating film, In the step of forming the groove, the upper insulating film is etched using the predetermined type of etchant until the lower insulating film is reached.

According to this aspect, first, in the step of forming one interlayer insulating film, a lower insulating film which is hard to be etched is formed. Then, an upper insulating film which is easily etched and has a thickness corresponding to the thickness of the data line is formed thereon. Thus, one interlayer insulating film having a multilayer structure is formed. Next, in the step of forming a groove, etching is performed on the upper insulating film in a region where the data line is to be formed, and the etching is continued until the lower insulating film is reached. Here, since the thickness of the upper insulating film corresponds to the thickness of the data line, the depth of the groove corresponds to the thickness of the data line. That is, ideally, a groove having a depth to bury the data line without a step is dug by the etching. As a result, the relatively easy and reliable control of the thickness of the upper insulating film, which can be formed by, for example, sputtering or vapor deposition, makes it possible to planarize the entire surface of the data line and the one interlayer insulating film in which the data line is embedded. Can be promoted.

In another aspect of the method of manufacturing an electro-optical device according to the present invention, before the step of forming the one interlayer insulating film, at least a stopper film functioning as a stopper for a predetermined type of etchant is provided on the data line. Forming the one interlayer insulating film in a region where the data line is to be formed, and forming the one interlayer insulating film having a thickness corresponding to the thickness of the data line. In the step of forming the groove, the one interlayer insulating film is etched using the predetermined type of etchant until reaching the stopper film in a region where the data line is to be formed.

According to this aspect, before the step of forming one interlayer insulating film, a stopper film for etching is formed at least in a region where a data line is to be formed. Next, in a step of forming one interlayer insulating film, one interlayer insulating film having a thickness corresponding to the thickness of the data line is formed thereon. Thereby, one interlayer insulating film in which the stopper layer is provided in the lower layer is formed. Then, in the step of forming the groove, in the region where the data line is to be formed, the etching is performed on one interlayer insulating film, and the etching is continued until reaching the stopper film. Then, when the stopper film is exposed, the etching is stopped, and a groove reaching the stopper film is formed in one interlayer insulating film. Here, since the thickness of one interlayer insulating film corresponds to the thickness of the data line, the depth of the groove corresponds to the thickness of the data line. That is, ideally, a groove having a depth to bury the data line without a step is dug by the etching. As a result, for example, by relatively easy and highly reliable control of controlling the thickness of one interlayer insulating film that can be formed by sputtering, vapor deposition, or the like,
Moreover, by controlling the etching depth using the stopper film,
Flattening on the entire surface of the data line and the one interlayer insulating film in which the data line is embedded can be further promoted.

In another aspect of the method of manufacturing an electro-optical device according to the present invention, in the step of forming the data line, the data line is formed in the groove by a damascene method.

According to this aspect, since the data line is formed in the groove by the damascene method, the data line can be buried completely in the space in the groove and the upper surface of the one interlayer insulating film around the groove. And a data line having an extremely smooth continuous upper surface can be formed. As a result,
Other interlayer insulating films formed on the data lines are formed as extremely flat films.

In one aspect of the method of manufacturing an electro-optical device according to the present invention, the step of flattening includes a step of flattening by a polishing process.

According to this aspect, one interlayer insulating film is flattened by the polishing process. In this case, even if a dense one interlayer insulating film that can be formed by thermal baking performed before forming the data line is flattened by the polishing process, the possibility that cracks are generated by the polishing is reduced. Also, since one dense interlayer insulating film is flattened by polishing,
The difference in the amount of polishing between the vicinity of the center and the periphery of the mother substrate is also reduced.

For example, such a polishing process may be a CMP process. In this case, in particular, even if a dense one interlayer insulating film that can be formed by thermal baking is flattened by the CMP treatment, the possibility of cracking is reduced.

In another aspect of the method of manufacturing an electro-optical device according to the present invention, the one interlayer insulating film includes a silicon oxide film.

According to this aspect, it is possible to form a dense one interlayer insulating film by performing thermal baking on the one interlayer insulating film including the silicon oxide film. Further, the one interlayer insulating film including the silicon oxide film can be satisfactorily planarized while reducing the occurrence of cracks due to polishing or the like.

For example, the step of forming one such interlayer insulating film may include the step of forming the silicon oxide film using TEOS (tetra-ethyl-ortho-silicate) as a raw material. In this manner, one interlayer insulating film made of a silicon oxide film is formed using TEOS as a raw material. If TEOS is used as a raw material, it becomes possible to stack one interlayer insulating film, which becomes dense by performing thermal firing, very thickly. For this reason, even if the step caused by the presence of the pixel switching element and the like is relatively large, it is possible to sufficiently planarize using the one interlayer insulating film.

In another aspect of the method of manufacturing an electro-optical device according to the present invention, the step of forming the one interlayer insulating film and the step of flattening the semiconductor substrate may include a step of 700
The method further includes a step of performing a heat treatment at a temperature of not less than ° C.

According to this aspect, after forming one interlayer insulating film made of a silicon oxide film using TEOS as a raw material, the one interlayer insulating film is subjected to a heat treatment at 700 ° C. or higher. That is, a very dense film can be obtained by subjecting a silicon oxide film made of TEOS to thermal baking at 700 ° C. or higher. In addition, since the data line is formed after the heat treatment and the planarization, there is no problem even if the data line is formed from a material that is melted by the heat treatment at 700 ° C. or more.

In another aspect of the method of manufacturing an electro-optical device according to the present invention, the method further includes a step of forming a non-light-transmitting film which covers the data line at least partially as viewed in plan.

According to this aspect, the non-light-transmitting film that covers the data line at least partially as viewed in plan is formed. Such a non-light-transmitting film is formed between the substrate and the pixel switching element, between the pixel switching element and one interlayer insulating film, between one interlayer insulating film and another in the laminated structure of the electro-optical device. It may be formed between an interlayer insulating film and a counter substrate facing the substrate. Due to the non-light-transmitting film formed in this way, due to a step caused by the presence or absence of the data line formed on one interlayer insulating film, a display defect portion such as light leakage in an image display area along the data line, It can be hidden by the non-light transmitting film. As a result, a high-contrast image can be displayed.

In the aspect of forming the non-light-transmitting film, between the step of forming the pixel switching element and the step of forming the pixel electrode, the step of forming the non-light-transmitting film is performed simultaneously with the step of forming the non-light-transmitting film. The method may further include a step of forming a conductive film for connecting the pixel electrode and another terminal of the pixel switching element from the same film as the non-light-transmitting film.

According to this structure, simultaneously with the step of forming the non-light-transmitting film and from the same film as the non-light-transmitting film, the other terminals of the pixel electrode and the pixel switching element (for example,
A conductive film for connecting to the drain of the TFT is formed. That is, since the conductive film allows the pixel electrode and the other terminal of the pixel switching element to be relayed, the opening of the contact hole is facilitated and the contact can be easily performed as compared with a case where both are directly connected by a deep contact hole. The diameter of the hole can be reduced. Accordingly, even when one interlayer insulating film to be planarized is thickly formed, the opening of the contact hole does not pose a problem.

In the aspect of forming the non-light-transmitting film, at least the channel region and the channel region of the thin-film transistor constituting the pixel switching element are formed simultaneously with the step of forming the non-light-transmitting film and from the same film as the non-light-transmitting film. The method may further include a step of forming a light-shielding film that covers the junction between the channel region and the drain region in plan view.

In this case, at least simultaneously with the step of forming the non-light-transmitting film and from the same film as the non-light-transmitting film, at least the channel region of the thin film transistor constituting the pixel switching element and the channel region and the drain region A light-shielding film is formed to cover the joint portion in plan view. In other words, the light-shielding film can prevent a leak current due to light of the thin film transistor due to a photoelectric effect in the channel region and the junction.

In this aspect of forming the non-light-transmitting film, in the step of forming the non-light-transmitting film, the non-light-transmitting film and the pixel electrode overlap each other at least partially in plan view. A light transmitting film may be formed.

With this configuration, since the non-light-transmitting film and the pixel electrode overlap at least partially in plan view, the overlapping non-light-transmitting film at least partially defines the contour of the opening region of each pixel. Can be specified.

In this case, in particular, in the step of forming the data line and the step of forming the pixel electrode, the data line and the pixel electrode are formed so as not to at least partially overlap with each other in plan view. The pixel electrode may be formed.

In this case, since the data line and the pixel electrode do not at least partially overlap in plan view, the data line and the pixel electrode face each other via another interlayer insulating film. Parasitic capacitance can be extremely reduced. As a result, the image quality can be improved by preventing a change in the signal level supplied to the data line and reducing image unevenness on the display. Further, a step caused by the presence or absence of the data line formed on one interlayer insulating film can be offset to some extent or almost completely by the presence or absence of the pixel electrode. Conversely, since the data line and the pixel electrode do not overlap in a plan view, there is a gap between the data line and the pixel electrode through which light can pass.However, this gap can be hidden by the non-light-transmitting film. There is no display defect such as light leakage between the line and the pixel electrode.

In another aspect of the method of manufacturing an electro-optical device according to the present invention, between the step of forming the groove and the step of forming the data line, the one contact hole is opened and the data line is simultaneously opened. The method further includes a step of forming an opening portion serving as an alignment mark when forming the hole.

According to this aspect, when one contact hole is opened in one planarized interlayer insulating film, an opening portion serving as an alignment mark for forming a data line is also opened simultaneously. Drilled. That is, an alignment mark is opened in one of the planarized interlayer insulating films, and when the Al film or the like is formed on the entire surface, a depression is formed in the Al film or the like corresponding to the alignment mark.
Using this as a positioning reference, a data line can be formed.

In another aspect of the method of manufacturing an electro-optical device according to the present invention, in the step of forming the groove, a part of a peripheral circuit is formed from the same film as the data line with respect to the flattened interlayer insulating film. In the step of forming the data line in the region where the data line is to be formed, a part of the peripheral circuit is also formed in the groove from the same film as the data line.

According to this aspect, the step in the peripheral region of the substrate provided with the peripheral circuit is flattened by forming a part of the peripheral circuit in the groove. If such a step exists in the peripheral area, the tip of the rubbing device is not affected by the step at the time of rubbing, so that the image display area cannot be rubbed smoothly, and image unevenness due to rubbing occurs. Therefore, if the peripheral circuit is also flattened as in this embodiment, rubbing can be performed uniformly on the substrate according to the degree of flattening, image unevenness due to rubbing can be reduced, and finally high quality An electro-optical device capable of displaying an image can be realized.

In this aspect, in the step of forming the pixel switching element, the other part of the peripheral circuit is also formed on the substrate, and in the step of forming the one interlayer insulating film, the other part of the peripheral circuit is formed. The one interlayer insulating film may be formed on the portion.

By manufacturing as described above, of the peripheral circuits,
The rubbing is performed on the substrate because not only the flattening of the portion formed of the same film as the data line but also the flattening of one interlayer insulating film on the other portion formed of the same film as the film forming the pixel switching element is performed. Can be performed uniformly, and image unevenness due to rubbing can be further reduced.

In order to solve the above-mentioned problems, an electro-optical device according to the present invention comprises: a pixel switching element on a substrate; an interlayer insulating film formed above the pixel switching element and flattened; A data line buried in a groove formed in the planarized one interlayer insulating film and connected to one terminal of the pixel switching element via one contact hole; and a data line formed on the data line. And a pixel electrode formed on the other interlayer insulating film and connected to another terminal of the pixel switching element via another contact hole.

According to the electro-optical device of the present invention, the one interlayer insulating film is formed above the pixel switching element and is flattened. The data line is formed on one interlayer insulating film, and is connected to one terminal of the pixel switching element via one contact hole. The pixel electrode is formed on another interlayer insulating film, and is connected to another terminal of the pixel switching element via another contact hole.

Therefore, the electro-optical device of the present invention can be suitably manufactured by the above-described method of manufacturing an electro-optical device of the present invention, has relatively low cost, has high device reliability, and has particularly high-definition images. Display becomes possible.

In one embodiment of the electro-optical device of the present invention, the substrate further includes a peripheral circuit formed of the same film as the data line and including a portion buried in the groove.

According to this aspect, the step in the peripheral region of the substrate provided with the peripheral circuit is flattened by forming a part of the peripheral circuit in the groove. By preventing the occurrence of rubbing streaks, image unevenness due to rubbing streaks can be reduced, and ultimately, high-quality image display becomes possible.

The operation and other advantages of the present invention will become more apparent from the embodiments explained below.

[0051]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) The structure of an electro-optical device according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix forming an image display area of an electro-optical device. FIG. FIG. 3 is a cross-sectional view taken along the line AA ′ of FIG. 2 and FIG. 4 is a cross-sectional view taken along the line BB ′ of FIG. 2. . In FIGS. 3 and 4, the scale of each layer and each member is made different so that each layer and each member have a size recognizable in the drawings.

In FIG. 1, a plurality of pixels which are formed in a matrix and form an image display area of the electro-optical device according to the present embodiment include a pixel electrode 9a and a TFT 30 for controlling the pixel electrode 9a in a matrix. A plurality of data lines 6a to which image signals are supplied are connected to the T
It is electrically connected to the source of FT30. The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 6a for each group. good. The scanning line 3a is connected to the gate of the TFT 30.
Are electrically connected to each other, and scan signals G1, G2,...
It is configured to apply in this order in a line-sequential manner. The pixel electrode 9a is electrically connected to the drain of the TFT 30. By closing the switch of the TFT 30, which is a switching element, for a certain period, the image signals S1, S2,... Write at a predetermined timing. The image signals S1, S2,..., Sn of a predetermined level written in the liquid crystal as an example of the electro-optical material via the pixel electrode 9a are transmitted between the pixel electrode 9a and a counter electrode (described later) formed on a counter substrate (described later). For a certain period. The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gray scale display. In the normally white mode,
In accordance with the applied voltage, the incident light cannot pass through the liquid crystal portion. In the normally black mode, the incident light can pass through the liquid crystal portion in accordance with the applied voltage. Light having a contrast according to the image signal is emitted from the optical device. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode.

In FIG. 2, a plurality of transparent pixel electrodes 9 are arranged in a matrix on a TFT array substrate of the electro-optical device.
a (the outline is indicated by a dotted line portion 9a ′), and the data line 6a, the scanning line 3a, and the capacitor line 3b are provided along the vertical and horizontal boundaries of the pixel electrode 9a. The data line 6a is electrically connected via a contact hole 5 to a source region described later in the semiconductor layer 1a made of, for example, a polysilicon film. The pixel electrode 9a is electrically connected to a drain region described later in the semiconductor layer 1a via the contact hole 8. In addition, the channel region 1 of the semiconductor layer 1a, which is indicated by a hatched region falling rightward in FIG.
The scanning line 3a is arranged so as to face a ′, and the scanning line 3a functions as a gate electrode. As described above, pixel switching TFTs 30 in which the scanning lines 3a are opposed to each other as gate electrodes in the channel region 1a 'are provided at intersections of the scanning lines 3a and the data lines 6a.

The capacitance line 3b has a main line extending substantially linearly along the scanning line 3a, and a protruding portion protruding upward in the drawing along the data line 6a from a portion intersecting the data line 6a.

Next, as shown in the cross-sectional view of FIG. 3, the electro-optical device includes a TFT array substrate 10 constituting an example of one transparent substrate and an example of the other transparent substrate disposed to face the TFT array substrate 10. And the opposing substrate 20 that constitutes it. TFT
The array substrate 10 is made of, for example, a quartz substrate, a glass substrate, or a silicon substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate. The pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film 16 on which a predetermined alignment process such as a rubbing process is performed is provided above the pixel electrode 9a. The pixel electrode 9a is made of, for example, ITO (Indium Tin O
xide) A transparent conductive film such as a film. Also, the alignment film 16
Is composed of, for example, an organic film such as a polyimide film.

On the other hand, a counter electrode 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 on which a predetermined alignment process such as a rubbing process is performed is provided below the counter electrode 21. I have. The counter electrode 21 is made of, for example, a transparent conductive film such as an ITO film. The alignment film 22 is made of an organic film such as a polyimide film.

Each pixel electrode 9 is provided on the TFT array substrate 10.
A pixel switching TFT 30 that controls switching of each pixel electrode 9a is provided at a position adjacent to the pixel electrode 9a.

As shown in FIG. 3, the opposing substrate 20 is provided with a light-shielding film 23 in a non-opening region of each pixel. For this reason, incident light from the side of the counter substrate 20 is applied to the channel region 1 of the semiconductor layer 1 a of the pixel switching TFT 30.
a ′, the lightly doped source region 1b and the lightly doped drain region 1
It does not invade c. Further, the light-shielding film 23 has a function of improving contrast, preventing color mixture of color materials when a color filter is formed, and the like.

[0060] Between the TFT array substrate 10 and the opposing substrate 20, which are configured as described above and are arranged so that the pixel electrode 9a and the opposing electrode 21 face each other, an electric space is formed in a space surrounded by a sealing material described later. Liquid crystal, which is an example of an optical material, is sealed, and a liquid crystal layer 50 is formed. The liquid crystal layer 50 has the alignment film 16 in a state where no electric field is applied from the pixel electrode 9a.
A predetermined orientation state is obtained by means of and. The liquid crystal layer 50
For example, it is composed of a liquid crystal in which one or several kinds of nematic liquid crystals are mixed. The sealing material is an adhesive made of, for example, a photo-curing resin or a thermosetting resin for bonding the TFT array substrate 10 and the opposing substrate 20 around them,
A gap material (spacer) such as glass fiber or glass beads is mixed to make the distance between the two substrates a predetermined value.

Further, a base insulating film 12 is provided between the TFT array substrate 10 and the plurality of pixel switching TFTs 30.
Is provided. The base insulating film 12 is formed on the entire surface of the TFT array substrate 10 to prevent deterioration of the characteristics of the pixel switching TFT 30 due to roughness at the time of polishing the surface of the TFT array substrate 10 or contamination remaining after washing. Having. The base insulating film 12 is made of, for example, NS.
It is made of a highly insulating glass such as G (non-doped silicate glass), PSG (phosphosilicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), a silicon oxide film, a silicon nitride film, or the like.

In this embodiment, the semiconductor layer 1a extends from the high-concentration drain region 1e to form a first storage capacitor electrode 1f, and a part of the capacitor line 3b opposed to the first storage capacitor electrode 1f serves as a second storage capacitor electrode. The insulating thin film 2 including the film is connected to the scanning line 3a.
The storage capacitor 70 is formed by extending from a position facing the first dielectric film and forming a first dielectric film sandwiched between these electrodes.

In FIG. 3, the pixel switching TFT
Reference numeral 30 denotes an LDD (Lightly Doped Drain) structure, and includes a scanning line 3a and a channel region 1 of a semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a.
a ', an insulating thin film 2 including a gate insulating film for insulating the scanning line 3a from the semiconductor layer 1a, a data line 6a, a low-concentration source region 1b and a low-concentration drain region 1c of the semiconductor layer 1a, and a high-concentration source of the semiconductor layer 1a. A region 1d and a high-concentration drain region 1e are provided. A corresponding one of the plurality of pixel electrodes 9a is connected to the high-concentration drain region 1e via the contact hole 8. Also, scanning line 3
A first interlayer insulating film 4 having a contact hole 5 leading to the high-concentration source region 1d and a contact hole 8 leading to the high-concentration drain region 1e is formed on the capacitor line 3a and the capacitor line 3b. Further, the data line 6a and the first
On the interlayer insulating film 4, a second interlayer insulating film 7 in which a contact hole 8 to the high concentration drain region 1e is formed. The above-described pixel electrode 9a is provided on the upper surface of the second interlayer insulating film 7 configured as described above.

As shown in FIG. 4, a data line 6a is provided in a non-opening area of each pixel located in a gap between pixel electrodes 9a adjacent to each other on the left and right in FIG. A portion along the data line 6a in the outline of the opening region is defined, and light leakage in the non-opening region is prevented by the data line 6a. In addition, a storage capacitor 70 is formed below the data line 6a, and the non-opening area is effectively used.

In this embodiment, in particular, as shown in FIGS. 3 and 4, the upper surface of the first interlayer insulating film 4 is flattened, and the TFTs 30 located below the first interlayer insulating film 4
The first interlayer insulating film 4 is configured to absorb a step on the underlying surface due to the presence of the storage capacitor 70, the scanning line 3a, and the capacitor line 3b. That is, the first interlayer insulating film 4 is first piled up to a thickness equal to or more than the step of the base surface in a later-described manufacturing process, and after a thermal baking treatment, a polishing treatment such as a CMP method is used to polish the first lowest portion. Polished until
Further, the surface is completely polished by polishing to such a thickness that the scanning lines 3a and the capacitance lines 3b are not exposed.

Then, the data line 6a is connected to the high-concentration source region 1d of the TFT 30 via the contact hole 5 in the groove 4a dug in the first interlayer insulating film 4 thus flattened. Are formed.

In particular, in such a manufacturing process, after the first interlayer insulating film 4 is flattened, the first interlayer insulating film 4 has no relation to the melting point of Al which is a low melting point metal forming the data line 6a. In addition, since the heat treatment is performed at 700 ° C. or more, the first interlayer insulating film 4 is configured as a dense insulating film. As a result, when the first interlayer insulating film 4 is flattened by the polishing process, the possibility of occurrence of cracks is reduced,
Finally, a high non-defective product rate is realized. Further, since the dense first interlayer insulating film 4 is flattened, the difference in the amount of polishing between the vicinity of the center and the vicinity of the periphery of the mother substrate is reduced, and the film of the first interlayer insulating film 4 after the flattening is formed. The thickness is made uniform within the mother substrate surface.

In addition, as shown in FIGS. 3 and 4, the grooves 4 formed in the first interlayer insulating film 4 thus planarized.
Since the data line 6a is buried in a, almost no level difference due to the presence of the data line 6a occurs on the entire surface of the first interlayer insulating film 4 including the data line 6a. Accordingly, the step in the second interlayer insulating film 7 formed thereon is further reduced by almost the thickness of the data line 6a as compared with the case where the data line 6a is not embedded in the groove 4a.

As a result, according to the present embodiment, the data line 6a is made of a low melting point metal material such as Al having an excellent time constant, but is subjected to a high-temperature thermal sintering process irrespective of the melting point. As a result, a reduction in the manufacturing yield due to the planarization process on the densified first interlayer insulating film 4 is suppressed, and a low-cost and high-definition electro-optical device is finally realized.

Further, the first interlayer insulating film 4 is planarized as described above, and the data lines 6 are formed in the trenches 4a dug in the first interlayer insulating film 4.
Since the rubbing process may be performed on the alignment film 16 formed on the pixel electrode 9a in which a is buried and has almost no step, the rubbing direction is not restricted by the step direction. For this reason, in particular, TN (Tw
When a liquid crystal is used, by rubbing in a direction of 45 degrees with respect to the direction of the data line 6a (the vertical direction in FIG. 2), the liquid crystal is also used in an inverted manner in the above-mentioned multi-plate type color projector. Since the clear viewing direction can be made the same between one light valve and the other two light valves, it is also possible to prevent a situation where color unevenness is increased by combining three light valves. . Further, an electro-optical device having such a configuration is referred to as a VA (Vertica).
When applied to a liquid crystal device of the (ly Aligned) mode, highly accurate vertical alignment can be obtained by the pixel electrode 9a having almost no step.

In the first embodiment described above, the pixel switching TFT 30 preferably has an LDD structure as shown in FIG. 3, but implants impurity ions into the low-concentration source region 1b and the low-concentration drain region 1c. It may have an offset structure which is not performed, or a self-aligned TFT in which impurity ions are implanted at a high concentration by using a gate electrode formed of a part of the scanning line 3a as a mask to form a high concentration source and drain region in a self-aligned manner. There may be. In this embodiment, the pixel switching TFT 3
Although only one gate electrode is disposed between the high-concentration source region 1d and the high-concentration drain region 1e, two or more gate electrodes may be disposed between them. When a TFT is formed with a dual gate or a triple gate or more as described above, a leak current at a junction between a channel and a source / drain region can be prevented, and a current in an off state can be reduced.

In this embodiment, each contact hole (8
The planar shape of (5) may be circular, square, or other polygonal shapes. The circular shape is particularly useful for preventing cracks in the interlayer insulating film around the contact hole. Then, in order to obtain a good electrical connection, it is preferable that wet etching is performed after dry etching to slightly taper each of these contact holes.

(Manufacturing Process of First Embodiment) Next, a manufacturing process of the TFT array substrate constituting the electro-optical device according to the first embodiment having the above-described configuration will be described with reference to FIGS. Will be explained. FIG. 5 is a process diagram showing each layer on the TFT array substrate side in each process corresponding to the AA ′ section of FIG. 2 as in FIG. 6 to 8 are process diagrams showing a specific example of a method of forming the groove 4a in the process (d) of FIG. FIG. 9 is a process chart showing a specific example of a method of forming the data line 6a in the process (e) of FIG.

First, as shown in step (a) of FIG. 5, a TFT is formed on a TFT array substrate 10 by using a thin film forming technique.
30 and a storage capacitor 70 are formed.

More specifically, first, a TFT array substrate 10 such as a quartz substrate, a hard glass substrate, or a silicon substrate is prepared, and a TEOS gas, a TEB (Tetra. NSG, PSG, BSG, B using Ethyl boat rate) gas, TMOP (Tetra methyl oxy phosphate) gas, etc.
It is composed of a silicate glass film such as PSG, a silicon nitride film, a silicon oxide film, etc., and has a thickness of about 500 to 2000 n.
The underlying insulating film 12 of m is formed. Next, the base insulating film 12
An amorphous silicon film is formed thereon by low-pressure CVD or the like, and a heat treatment is performed thereon, so that a polysilicon film is solid-phase grown. Alternatively, a polysilicon film is directly formed by a low pressure CVD method or the like without passing through the amorphous silicon film. Next, a semiconductor layer 1a having a predetermined pattern including the first storage capacitor electrode 1f as shown in FIG. 2 is formed by subjecting the polysilicon film to a photolithography step, an etching step and the like. Next, an insulating thin film 2 including a first dielectric film for forming a storage capacitor is formed together with the gate insulating film of the TFT 30 by thermal oxidation or the like. As a result, the thickness of the semiconductor layer 1a is about 30 to 150 nm, preferably about 35 to 50 nm, and the thickness of the insulating thin film 2 is about 20 to 150 nm, preferably about 30 to 150 nm. It is about 100 nm thick. Next, a polysilicon film is deposited to a thickness of about 100 to 500 nm by a low pressure CVD method or the like, and P (phosphorus) is thermally diffused to make the polysilicon film conductive. Thus, the scanning lines 3a and the capacitance lines 3b having a predetermined pattern as shown in FIG. 2 are formed. The scanning line 3a
The capacitor line 3b may be formed of a metal alloy film such as a high melting point metal or a metal silicide, or may be a multilayer wiring combined with a polysilicon film or the like. Next, a low-concentration source region 1b and a low-concentration drain region 1c, a high-concentration source region 1d, and a high-concentration drain region 1e are included by doping impurity ions in two steps of low concentration and high concentration.
A pixel switching TFT 30 having an LDD structure is formed.

In parallel with the step (a) in FIG.
Peripheral circuits, such as a data line driving circuit and a scanning line driving circuit, which are formed from the TFT array substrate 10, may be formed in the peripheral portion.

Next, as shown in a step (b) of FIG. 5, the upper surface of the TFT array substrate 10 on which the scanning lines 3a, the capacitance lines 3b, the insulating thin film 2, and the base insulating film 12 are formed is covered.
For example, an interlayer insulating film 4 'made of a silicate glass film such as NSG, PSG, BSG, BPSG, a silicon nitride film, a silicon oxide film, or the like is formed by using a normal pressure or reduced pressure CVD method, a TEOS gas, or the like. Subsequently, the interlayer insulating film 4 '
Is subjected to thermal baking at a temperature of 700 ° C. or more. The film thickness of the interlayer insulating film 4 'is sufficient to absorb such a step on the upper surface of the stacked body, and sufficient so that the scanning lines 3a and the capacitance lines 3b are not exposed even if the trenches 4a are dug after planarization. Set to thickness. Specifically, the thickness is, for example, about 1000 to 2000 nm. In this embodiment, in particular, since thermal baking is performed at 700 ° C. or more, even a relatively thick insulating film having a thickness of about 2000 nm is a high-quality insulating film that is dense and hardly cracks in a subsequent polishing process. Is obtained.
In parallel with or before or after this thermal baking, a heat treatment at about 1000 ° C. may be performed to activate the semiconductor layer 1a.

Next, as shown in step (c) of FIG. 5, the interlayer insulating film 4 'is flattened by a polishing process such as a CMP method.
Specifically, for example, a liquid slurry (chemical polishing liquid) containing silica particles is allowed to flow on a polishing pad fixed on a polishing plate, and the surface of the substrate fixed on the spindle (on the side of the interlayer insulating film 4 ′) Is polished to make the surface of the interlayer insulating film 4 ′ by rotating contact. Before the scanning lines 3a and the capacitance lines 3b are exposed, the polishing process is stopped by time management or by forming an appropriate stopper layer at a predetermined position on the TFT array substrate 10. As a result, the first interlayer insulating film 4 having a thickness of about 500 to 1500 nm and having a flat upper surface is completed.

Next, as shown in step (d) of FIG. 5, a groove 4a is formed in the region where the data line 6a is to be formed in the flattened first interlayer insulating film 4. Here, with reference to FIGS. 6 to 8, a description will be given of various methods of forming the groove 4a in this step (d).

In the method of forming the groove 4a shown in FIG. 6, first, as shown in step (1) of FIG. 6, a resist 600 is formed on the planarized first interlayer insulating film 4, and By a photolithography process and an etching process using a mask corresponding to the plane pattern, a resist 600 having the same plane pattern as the groove 4a is formed. Next, as shown in step (2) of FIG. 6, dry etching such as reactive ion etching and reactive ion beam etching is performed using the etchant 601 through the resist 600. Then, by controlling the time of the dry etching, the depth of the groove 4a to be formed is controlled. Finally, as shown in step (3) of FIG. 6, the first interlayer insulating film 4 having the flattened and trench 4a is completed by removing the resist 600. As described above, by controlling the dry etching time, it is possible to relatively easily dig the groove 4a having a depth to bury the data line 6a without any step. In addition, if the dry etching having high directivity is used, the depth control and the shape control of the groove can be performed with relatively high accuracy even by time management. Good.

In the method of forming the groove 4a shown in FIG. 7, the etchant 6 is formed in the steps (b) and (c) shown in FIG.
01 is hard to be etched by dry etching or wet etching such as reactive ion etching or reactive ion beam etching, and is easily etched by the etchant 601 on the lower insulating film 4L such as a silicon nitride film and the data line 6a. An upper insulating film 4U such as, for example, a silicon oxide film, having a thickness corresponding to the above thickness is formed. That is, it is assumed that one interlayer insulating film 4 having a multilayer structure including the lower insulating film 4L and the upper insulating film 4U is formed before the step (d) in FIG. First, as shown in step (1) of FIG. 7, a resist is stacked on the planarized first interlayer insulating film 4, and a photolithography step using a mask corresponding to the plane pattern of the groove 4a is performed. By the etching process, a resist 600 having the same plane pattern as the groove 4a is formed. Next, as shown in step (2) of FIG. 7, the upper insulating film 4U such as a silicon oxide film which is easily etched by the etchant 601 is etched using the etchant 601 through the resist 600.
Then, after the lower insulating film 4L, such as a silicon nitride film, which is hardly etched by the etchant 601 is exposed,
Stop the etching. Finally, as shown in the step (3) of FIG. 7, the first interlayer insulating film 4, which is flattened and the trench 4a is dug, is completed by removing the resist 600. In this manner, the relatively easy and reliable control of the thickness of the upper insulating film 4U, which can be formed by, for example, sputtering or vapor deposition, makes it possible to relatively easily form the groove 4a having a depth at which the data line 6a is embedded without any step. You can dig into.

In the method of forming the groove 4a shown in FIG. 8, at the stage of the steps (b) and (c) shown in FIG. Alternatively, the data line 6 is easily etched by the etchant 601 on the insulating base 700.
A lower insulating film 4L ′ having a thickness corresponding to the thickness of “a”, such as a silicon oxide film, is formed. First, as shown in step (1) of FIG. 8, a resist is deposited on the flattened lower insulating film 4L ', and corresponds to the plane pattern of the groove 4a (that is, the plane pattern of the data line 6a). Using a mask to be formed, a resist 600 having the same plane pattern as the groove 4a is formed by a photolithography step and an etching step. Next, as shown in step (2) of FIG.
Using 1, etching (dry etching or wet etching such as reactive ion etching, reactive ion beam etching, etc.) is performed on the lower insulating film 4 </ b> L ′ such as a silicon oxide film which is easily etched by the etchant 601. Then, after the base 700 that is difficult to be etched by the etchant 601 is exposed, the etching is stopped. Next, as shown in step (3) of FIG. 8, after removing the resist 600, step (4) of FIG.
As shown in FIG. 5, the entire surface of the lower insulating film 4L 'extending in the groove 4a' and around the groove 4a 'to cover the base 700 exposed at the bottom of the groove 4a' dug in the lower insulating film 4L '. An upper insulating film 4U 'is formed. Thus, the lower insulating film 4 which can be formed by, for example, sputtering or vapor deposition.
With the relatively easy and reliable control of controlling the film thickness of L ′, the groove 4 having a depth that embeds the data line 6a without any step is provided.
a can be dug relatively easily. Moreover, if the groove 4
If the data line 6a is formed directly in the groove 4a ',
Even if problems such as short-circuit, reduced insulation, contamination, corrosion, etc. occur depending on the properties of the base 700 exposed at the bottom of the trench, the electrical insulation effect of the upper insulating film 4U 'formed in the trench 4a' or Such a problem does not occur due to the pollution prevention effect or the like. In this case, the upper insulating film 4U 'may be formed as thin as possible to prevent such a problem.

Next, as shown in step (e) of FIG. 5, a contact hole 5 for electrically connecting the data line 6a and the high-concentration source region 1d of the semiconductor layer 1a is formed in the first interlayer insulating film in which the groove 4a is formed. A hole is formed in the film 4 and the insulating thin film 2. Also,
A contact hole for connecting the scanning line 3a and the capacitance line 3b to a wiring (not shown) in the peripheral region of the substrate can be formed in the same process as the contact hole 5. Subsequently, a low-resistance metal film such as Al or a metal silicide film is deposited to a thickness of about 100 to 500 nm on the first interlayer insulating film 4 by sputtering or the like. The data lines 6a are formed so as to be buried in the grooves 4a having a preset plane pattern.

Here, referring to FIG. 9, this step (e)
A description will be given of a specific example using the damascene method as an example of the method of forming the data line 6a in FIG.

That is, as shown in the step (1) of FIG. 9, the groove 4a and the contact hole 5 are formed on the first interlayer insulating film 4 as shown in the step (2) of FIG. 4a
The Al film 6a 'is stacked by sputtering or the like so as to be thicker than the depth of the Al film. Then, as shown in step (3) in FIG. 9, the Al film 6a 'is polished by CMP polishing or the like, and the polishing is stopped when the Al film 6a' remains only in the groove 4a. Thus, the Al film 6 remaining in the groove 4a
a 'becomes the data line 6a. As described above, when the damascene method is used, the data line 6 can be completely embedded in the space in the groove 4a and has an upper surface that is extremely smoothly continuous with the upper surface of the first interlayer insulating film 4a around the groove 4a. The data line 6a can be formed.

Next, as shown in step (f) of FIG. 5, a second interlayer insulating film 7 is formed on the data line 6a, and the pixel electrode 9 is formed.
A contact hole 8 for electrically connecting a with the high-concentration drain region 1e is formed by dry etching such as reactive ion etching or reactive ion beam etching or wet etching. Subsequently, a transparent conductive film such as an ITO film is deposited on the second interlayer insulating film 7 by sputtering or the like to a thickness of about 50 to 200 nm,
Further, a pixel electrode 9a is formed by a photolithography process, an etching process, and the like. When the electro-optical device is used as a reflection type, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al.

As described above, according to the manufacturing method of the present embodiment, after the first interlayer insulating film 4 is planarized, the groove 4a is formed in the first interlayer insulating film 4, and the data line 6a is formed in the groove 4a. Therefore, Al which is a material of the data line 6a and has an excellent time constant is used.
Despite being a low-melting metal, the first interlayer insulating film 4 can be sufficiently subjected to heat treatment at a high temperature that is unrelated to this melting point. That is, the dense first interlayer insulating film 4 can be formed by the thermal baking in the step (b) performed before the step (e) for forming the data line 6a. As a result, even if the first interlayer insulating film 4 is polished in the step (c), the possibility of occurrence of cracks is reduced, and finally the non-defective product rate can be improved. Further, since the dense first interlayer insulating film 4 is flattened, the difference in the amount of polishing between the vicinity of the center and the periphery of the mother substrate is reduced, and the thickness of the first interlayer insulating film 4 after the flattening is reduced. It can be made uniform within the plane of the substrate. In particular, according to the present manufacturing method, since a polishing process such as a CMP method may be performed as the flattening process, cost increase due to an increase in the number of processes is hardly caused as compared with the conventional manufacturing method. In addition, since the data line 6a is buried in the trench 4a dug in the first interlayer insulating film 4 planarized in the step (c), the first line including the data line 6a is formed even after the data line 6a is formed. There is almost no step due to the presence of the data line 6a on the entire surface of the interlayer insulating film 4. For this reason, at the point of time when the pixel electrode 9a is formed in the step (f), the surface of the second interlayer insulating film 7 serving as the underlying surface can be extremely satisfactorily planarized.

In the manufacturing method of the present embodiment described above, it is particularly preferable that the first interlayer insulating film 4 is formed from a silicon oxide film. With such a structure, it is possible to form a dense first interlayer insulating film 4 by performing thermal baking on the interlayer insulating film 4 ′ made of a silicon oxide film. Further, such a silicon oxide film is formed by TEOS
Is more preferably formed as a raw material. Thus T
If the interlayer insulating film 4 ′ made of a silicon oxide film is formed using EOS as a raw material, the interlayer insulating film 4 ′ that becomes dense by performing thermal baking can be stacked to a thickness of, for example, about 2000 nm. For this reason, even if there is a step difference of, for example, 1000 nm or more due to the existence of the TFT 30, etc., it is possible to sufficiently planarize using the interlayer insulating film 4 'in the steps (b) and (c) of FIG. Becomes In particular, if the interlayer insulating film 4 'is thickly stacked in the step (b) as described above,
Even in the step (c), even if a method in which the planarization process such as the CMP process is stopped by time management is employed, the possibility that the interlayer insulating film 4 'penetrates due to excessive polishing can be reduced. In addition, when forming the interlayer insulating film 4 'made of a silicon oxide film using TEOS as a raw material,
When heat treatment is performed at 700 ° C. or higher, an extremely good insulating film which is very dense and hardly cracked by polishing can be obtained.

In the manufacturing method of the present embodiment described above,
In step (e) of FIG. 5, a contact hole 5 is formed before the data line 6a is formed, and at the same time, an opening portion serving as an alignment mark for forming the data line 6a is formed with TF.
It is preferable to open holes at predetermined positions on the T array substrate 10. However, when an Al film or the like is formed on the entire surface of the flattened first interlayer insulating film 4 by sputtering or the like, the Al film or the like is non-light-transmitting and has a flat surface. Etc. and data lines 6a located below
It is not possible to determine the positional relationship with. However, if an alignment mark (opening portion) is formed in a predetermined position of the second interlayer insulating film 4 thus flattened, the alignment mark is formed when the Al film or the like is formed on the entire surface. Correspondingly, a depression is formed in the Al film or the like. As a result, the data line 6a can be formed using the depression as a positioning reference, which is convenient. In addition, if the alignment mark is formed at the same time as the contact hole 5, an opening process dedicated to the alignment mark is not required, which is extremely advantageous in a manufacturing process.

Note that, at the same time as the step of forming the groove 4a by etching, an opening serving as an alignment mark may be formed.

(Second Embodiment) FIGS. 10 to 12 show the configuration of an electro-optical device according to a second embodiment of the present invention.
This will be described with reference to FIG. FIG. 10 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed, and FIG.
FIG. 12 is a sectional view taken along the line C ′, and FIG. 12 is a sectional view taken along the line DD ′ in FIG. In FIGS. 11 and 12, the scale of each layer and each member is made different so that each layer and each member have a size recognizable in the drawings. In the second embodiment shown in FIGS. 10 to 12, the same components as those in the first embodiment shown in FIGS. 2 to 4 are denoted by the same reference numerals, and description thereof will be omitted.

The second embodiment differs from the first embodiment in the following points, and the other configuration is the same as that of the first embodiment.

That is, as shown in FIGS. 10 and 11, the scanning line 3a in the gap between the vertically adjacent pixel electrodes 9a
(Regions indicated by coarse diagonal lines falling rightward in FIG. 10) are provided with island-shaped conductive barrier layers 80a, and the pixel electrodes 9a relay the barrier layers 80a, It is electrically connected to the high concentration drain region 1e via the contact holes 8a and 8b. Further, as shown in FIGS. 10 and 12, regions along the data lines 6a (regions indicated by coarse oblique lines falling to the right in FIG. 10) in the gaps between the pixel electrodes 9a adjacent to each other on the left and right are respectively provided with barrier layers. 80
b is provided, and the barrier layer 80b and the capacitor line 3b are connected via the contact hole 8c.

As shown in FIGS. 10 to 12, in the second embodiment, a part of the capacitance line 3b facing the first storage capacitor electrode 1f is used as a second storage capacitor electrode and includes a gate insulating film. The first storage capacitor 70a is formed by extending the insulating thin film 2 from a position facing the scanning line 3a to form a first dielectric film sandwiched between these electrodes. On the other hand, a part of the barrier layer 80a facing the second storage capacitor electrode is used as a third storage capacitor electrode, and the second dielectric film 81 is provided between these electrodes to form the second storage capacitor 70b. . The first storage capacitor 70a and the second storage capacitor 70b are connected in parallel via the contact holes 8a and 8b to form the storage capacitor 70. Thus, the second dielectric film 8 constituting the second storage capacitor 70b
1 may be a silicon oxide film, a silicon nitride film, or the like,
It may be composed of a multilayer film. Generally, various known techniques (low-pressure CVD, plasma CVD, thermal oxidation, etc.) used to form the insulating thin film 2 such as a gate insulating film are used.
The second dielectric film 81 can be formed.

As described above, in the second embodiment, the high-concentration drain region 1e and the pixel electrode 9a are electrically connected via the barrier layer 80a, so that one contact hole is formed from the pixel electrode 9a to the drain region. The diameter of each of the contact hole 8a and the contact hole 8b can be made smaller than that in the case of performing the above.

The barrier layers 80a and 80b are
For example, high melting point metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), and Mo
(Molybdenum) and Pb (lead), and are composed of a simple metal, an alloy, a metal silicide, or the like. Thereby, good electrical connection can be obtained between the barrier layer 80a and the pixel electrode 9a via the contact hole 8b.

As shown particularly in FIGS. 10 and 12,
Since the light-shielding barrier layer 80b that covers the data line 6a at least partially as viewed in plan is provided, the data due to the step caused by the presence or absence of the data line 6a formed on the second interlayer insulating film 4 A display defect portion such as light leakage in the image display area along the line 6a can be hidden by the barrier layer 80b. As a result, a high-contrast image can be displayed. Similarly, a display defect portion such as light leakage in an image display area along the scanning line 3a and the capacitance line 3b can be hidden by the barrier layer 80a. As a result, a high-contrast image can be displayed. Further, the barrier layer 80a and the barrier layer 80b can be simultaneously manufactured from the same film, which is advantageous in the manufacturing process. In particular, as shown in FIGS. 10 and 12, the barrier layer 80b and the pixel electrode 9a are formed so as to at least partially overlap with each other in plan view. The left and right contours of the opening area can be defined at least partially.

In the case of manufacturing the electro-optical device according to the second embodiment, the method for manufacturing the electro-optical device according to the first embodiment is performed between the steps (a) and (b) in FIG. Then, the second dielectric film 81 is formed by a low pressure CVD method, a plasma CV
A relatively thin film having a thickness of about 200 nm or less is deposited from a high-temperature silicon oxide film (HTO film) or a silicon nitride film by a method D or the like, and contact holes 8a and 8c are formed in the film by reactive ion etching or reactive ion beam etching. The hole is opened by dry etching or wet etching. Further, a metal alloy film such as a metal such as Ti, Cr, W, Ta, Mo and Pb or a metal silicide is deposited thereon by sputtering to form a conductive film having a thickness of about 50 to 500 nm. The barrier layers 80a and 80b may be formed by performing a photolithography step, an etching step, and the like on the substrate.

In addition, the barrier layers 80a and 80
When forming Ob, a stopper layer for the polishing process may be formed at a predetermined position on the TFT array substrate 10 from the same layer as these. If the stopper layer is formed in this way, the stop control of the CMP process can be performed by the stopper layer instead of the time management. The detection of the surface of the stopper layer in this case includes, for example, a friction detection method for detecting a change in friction coefficient when the stopper layer is exposed, a vibration detection method for detecting vibration generated when the stopper layer is exposed, and a stopper layer. It may be performed by an optical method that detects a change in the amount of reflected light when the light is exposed.

(Third Embodiment) An electro-optical device according to a third embodiment of the present invention will be described with reference to FIGS. FIG. 13 is a view showing the state of FIG.
FIG. 3 is a cross-sectional view of a portion corresponding to the DD ′ cross-sectional view shown in FIG. FIG. 14 is a process chart showing a groove excavation step of controlling the depth of the groove 4a using the barrier layer 80b as a stopper film in the manufacturing method of the third embodiment. In FIG. 13, the scale of each layer and each member is different in order to make each layer and each member a recognizable size in the drawing. In the third embodiment shown in FIGS. 13 and 14, the same components as those in the first or second embodiment shown in FIGS. 2 to 12 are denoted by the same reference numerals, and description thereof is omitted. I do.

The third embodiment differs from the second embodiment in the following points, and the other configuration is the same as that of the second embodiment.

That is, as shown in FIG. 13, the groove 4a in which the data line 6a is embedded reaches the barrier layer 80b.
The upper surface of the barrier layer 80b forms the bottom of the groove 4a.
The data line 6a is embedded in the groove 4a such that the bottom surface of the data line 6a contacts the upper surface of the barrier layer 80b. With this configuration, the barrier layer 80b can function as a redundant wiring for the data line 6a. Therefore, especially when the data line 6a is partially disconnected, the barrier layer 8
Owing to the existence of the redundant wiring composed of 0b, it is not necessary to substantially cause a wiring failure, which is advantageous from the viewpoint of improving the non-defective device rate. In order to make the barrier layer 80b redundant wiring of the data line 6a in this way, it is preferable that the barrier layer 80b be formed so as to overlap the data line 6a over the entire area where the data line 6a is wired as much as possible. . In the third embodiment, the contact hole 8c for electrically connecting the barrier layer 80b and the capacitance line 3b is not provided.

Further, when the bottom of the groove 4a is formed by the barrier layer 80b as in the present embodiment, the barrier layer 80b
Can be used as a stopper film when the trench 4a is dug by etching, which is advantageous from the viewpoint of simplifying the manufacturing process and the device configuration.

That is, as shown in FIG. 14, when the trench 4a is dug in the first interlayer insulating film 4 in the present embodiment, the thickness of the first interlayer insulating film 4 formed on the barrier layer 80b is reduced. After the steps (a) to (c) of FIG. 5 described above in the first embodiment are performed so as to be equal to the depth of 4a,
As shown in step (1) of FIG. 14, a resist is stacked on the planarized first interlayer insulating film 4, and a photolithography step and an etching step using a mask corresponding to the plane pattern of the groove 4a Thereby, a resist 600 having the same planar pattern as the groove 4a is formed. Next, as shown in step (2) of FIG. 14, the etchant 6 is formed by using the etchant 601 through the resist 600.
01 such as a silicon oxide film which is easily etched by
Etching (dry etching such as reactive ion etching, reactive ion beam etching or wet etching) on the interlayer insulating film 4 is performed. Then, the etching is stopped after the barrier layer 80b as a stopper film made of a high melting point metal or the like which is difficult to be etched by the etchant 601 is exposed. Finally, as shown in step (3) of FIG. 14, the first interlayer insulating film 4 having the flattened and trench 4a is completed by removing the resist 600. Moreover, since the bottom of the groove 4a is nothing but the upper surface of the barrier layer 80b, if the data line 6a is formed in the groove 4a as shown in FIG. 5E in the first embodiment, the data line 6a is automatically formed. And a barrier layer 80b.

Furthermore, not using time management but using the barrier layer 80b as a stopper film as described above makes it possible to form the groove 4a.
Can be accurately controlled, and the entire upper surface of the first interlayer insulating film 4 including the data lines 6a can be further flattened.

The stopper film as described above can be formed from the same film as the conductive film or the insulating film having another function in the pixel portion. More specifically, for example, the stopper film can be formed from the same film as the light-shielding conductive layer for defining the pixel opening region. In this case, the light-shielding conductive layer and the like can further have a function as a redundant wiring for the data line 6a. When the stopper film is formed using the same film as the film having other functions as described above, it is advantageous in simplifying a manufacturing process and an apparatus structure as compared with a case where a dedicated stopper film is separately formed. . However, the above-described effects of the present invention can be sufficiently achieved by separately forming a dedicated stopper film.

(Fourth Embodiment) The configuration of an electro-optical device according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 15 is a sectional view taken on line B- in FIG. 2 in the first embodiment.
It is sectional drawing of the TFT array substrate side part corresponding to B 'cross section. In FIG. 15, the scale of each layer and each member is different for each layer or each member in order to make the size recognizable in the drawing. In the fourth embodiment shown in FIG. 15, the same components as those in the first embodiment shown in FIG. 4 are denoted by the same reference numerals, and the description thereof will be omitted.

In FIG. 15, in the fourth embodiment, the first
The difference from the embodiment is that a light shielding film 11a is provided on the TFT array substrate 10 at a position facing the data line 6a. Also, as described above, the TFT array substrate 1
The light-shielding film 11a formed on the TFT 30 includes at least the channel region 1a 'of the TFT 30 and the channel region 1a',
It may be provided at a position that covers the junction of the low-concentration source region 1b and the low-concentration drain region 1c in plan view. By doing so, the light blocking film 11a allows the channel region 1
a ′ and TF at the junction with the source / drain region
A change in the characteristics of T30 can be prevented. In particular, if the light-shielding film 11a is formed between the TFT array substrate 10 and the TFT 30 as described above, it becomes possible to shield light such as return light from the TFT array substrate 10 side. As shown in FIG. 15, the edge of the light-shielding film 11a and the edge of the pixel electrode 9a are slightly overlapped in a plan view, and the edge of the data line 6a and the edge of the pixel electrode 9a are viewed in a plan view. The light-shielding film 11a, the pixel electrode 9a, and the data line 6a are laid out in a plane so as not to overlap. That is, in FIG. 15, with respect to the width W1 of the data line 6a, the interval W2 between the pixel electrodes 9a adjacent to each other on the left and right, and the width W3 of the light shielding film 11a, W1 <W2 <
These are provided so that the relationship of W3 is established.
Other configurations are the same as those in the first embodiment.

As a result, according to the fourth embodiment, the left and right contours of the opening region of each pixel can be defined by the light shielding film 11a overlapping the pixel electrode 9a. At the same time, since the data line 6a and the pixel electrode 9a do not overlap with each other, both of them are in the third interlayer insulating film 7.
Parasitic capacitance generated by facing each other through
The parasitic capacitance between the source and the drain of the TFT 30 can be extremely reduced. As a result, the image quality can be improved by preventing the signal level supplied to the data line 6a from changing and reducing the image unevenness on the display. Note that there is a gap between the data line 6a and the pixel electrode 9a through which light can pass, but this gap is hidden by the light shielding film 11a. Therefore, a display defect such as light leakage does not occur between the data line 6a and the pixel electrode 9a. Also, with this configuration,
The light shielding film 23 (see FIG. 3) need not be provided on the counter substrate 20 side.

In the case of manufacturing the electro-optical device of the fourth embodiment, in the step (a) of FIG. 5 in the method of manufacturing the electro-optical device of the first embodiment, the entire surface of the TFT array substrate 10 is Ti, Cr, W, Ta, Mo and P
b, metal alloy film such as metal silicide, etc., by sputtering, photolithography and etching
A film thickness of about 100 to 500 nm, preferably about 200 n
The light-shielding film 11a having a predetermined pattern with a thickness of m may be formed.

The light-shielding film 11a may extend below the scanning line 3a or the data line 6a and be electrically connected to a constant potential line. According to this structure, the light shielding film 11a is provided for the data line 6a and the TFT 30 which are disposed to face the light shielding film 11a.
The fluctuation of the potential a does not adversely affect. in this case,
As the constant potential line, a constant potential line such as a negative power supply or a positive power supply supplied to a peripheral circuit (eg, a scanning line driving circuit, a data line driving circuit, or the like) for driving the electro-optical device, a ground power supply, A constant potential line supplied to the electrode 21 is exemplified. The planar layout of the light-shielding film 11a may be a lattice along the data lines 6a and the scanning lines 3a,
It may be island-shaped so as to cover the data line 6a and the TFT 30.

(Fifth Embodiment) The structure of an electro-optical device according to a fifth embodiment of the present invention will be described with reference to FIG. FIG. 16 is a sectional view of the second embodiment shown in FIG.
It is sectional drawing of the TFT array substrate side part corresponding to -D 'cross section. In FIG. 16, the scale of each layer and each member is different for each layer or each member in order to make the size recognizable in the drawing. Incidentally, the fifth type shown in FIG.
In the embodiment, the same components as those of the second embodiment shown in FIG. 12 are denoted by the same reference numerals, and the description thereof will be omitted.

In FIG. 16, in the fifth embodiment, the second
Compared with the embodiment, the edge of the light-shielding barrier layer 80b and the edge of the pixel electrode 9a are slightly overlapped in a plan view, and the edge of the data line 6a and the edge of the pixel electrode 9a are viewed in a plan view. These barrier layers 80b and the pixel electrodes 9 are not overlapped.
a and the data lines 6a are laid out in a plane. That is, in FIG. 16, the width W1 of the data line 6a, the interval W2 of the pixel electrodes 9a adjacent to each other on the left and right, and the width W4 of the barrier layer 80b are provided such that the relationship of W1 <W2 <W4 is satisfied. I have. Other configurations are the same as those of the second embodiment.

As a result, according to the fifth embodiment, the right and left contours of the opening region of each pixel can be defined by the barrier layer 80b overlapping the pixel electrode 9a. At the same time, since the data line 6a and the pixel electrode 9a do not overlap with each other, the parasitic capacitance generated when they face each other via the third interlayer insulating film 7, that is, the parasitic capacitance between the source and the drain in the TFT 30 is extremely small. it can. As a result, the data line 6a
The image quality can be improved by preventing the level of the signal supplied to the display from changing and reducing image unevenness on the display. Note that there is a gap between the data line 6a and the pixel electrode 9a through which light can pass, but this gap is hidden by the barrier layer 80b. Therefore, a display defect such as light leakage does not occur between the data line 6a and the pixel electrode 9a. With this configuration, the light-shielding film 23 does not have to be provided on the counter substrate 20 side.

The method of manufacturing the electro-optical device according to the fifth embodiment is substantially the same as that according to the second embodiment, and a description thereof will not be repeated.

(Overall Configuration of Electro-Optical Device) The overall configuration of the electro-optical device in each embodiment configured as described above will be described with reference to FIG. 17 and FIG. Note that FIG.
FIG. 18 is a plan view of the TFT array substrate 10 together with the components formed thereon viewed from the counter substrate 20 side. FIG. 18 is a cross-sectional view taken along the line HH ′ of FIG.

In FIG. 17, a sealing material 52 is provided on the TFT array substrate 10 along the edge thereof. A light-shielding film 53 is provided as a frame that defines the periphery of the region. Seal material 52
In the area outside the data line 6a, the data line driving circuit 101 for driving the data line 6a by supplying the image signal to the data line 6a at a predetermined timing and the external circuit connection terminal 102
A scanning line driving circuit 104, which is provided along one side of the FT array substrate 10 and drives the scanning line 3a by supplying a scanning signal to the scanning line 3a at a predetermined timing, operates along two sides adjacent to this one side. It is provided. If the delay of the scanning signal supplied to the scanning line 3a does not matter, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. Further, the data line driving circuits 101 may be arranged on both sides along the side of the image display area. For example, the odd-numbered data lines supply image signals from a data line driving circuit disposed along one side of the image display area, and the even-numbered data lines extend along the opposite side of the image display area. The image signal may be supplied from the data line driving circuit provided. By driving the data lines 6a in a comb-tooth shape in this manner, the area occupied by the data line driving circuit 101 can be expanded, so that a complicated circuit can be configured. Further, on one remaining side of the TFT array substrate 10, the scanning line driving circuits 1 provided on both sides of the image display area are provided.
A plurality of wirings 105 are provided to connect between the wirings 04. In at least one of the corners of the counter substrate 20, a conductive material 106 for electrically connecting the TFT array substrate 10 and the counter substrate 20 is provided. Then, as shown in FIG. 18, the opposite substrate 20 having substantially the same contour as the sealing material 52 shown in FIG. 17 is fixed to the TFT array substrate 10 by the sealing material 52.

In this embodiment, in particular, the TFT array substrate 1
At least a part of the data line driving circuit 101 and the scanning line driving circuit 104, which are examples of the peripheral circuit formed on 0, is preferably made of the same film as the data line 6a and is buried in the groove 4a similarly to the data line 6a. ing. Therefore, the TF provided with the data line driving circuit 101 and the scanning line driving circuit 104
Since the step in the peripheral region on the T array substrate 10 is flattened by forming at least a part in the groove 4a, rubbing is uniformly performed on the TFT array substrate 10 according to the degree of flattening. And uneven image due to rubbing can be reduced.

In order to form at least a part of the data line driving circuit 101 and the scanning line driving circuit 104 in the groove 4a in the above-described manufacturing process, the first interlayer insulating circuit is formed in the step (d) of FIG. On the film 4, a groove 4a is also formed in a region where at least a part of the data line driving circuit 101 or the scanning line driving circuit 104 is to be formed from the same film as the data line 6a, and in the step (e) of FIG. In the groove 4a, at least a part of the data line driving circuit 101 or the scanning line driving circuit 104 may be formed from the same film as the data line. Further, in the step (a) of FIG.
At the same time as forming the FT 30, the TFT array substrate 10
Other parts (for example, TFTs) of the data line driving circuit 101 and the scanning line driving circuit 104 are also formed thereon, and thereafter, in steps (b) and (c) of FIG. 5, the data line driving circuit 101 and the scanning line driving circuit 104 also has a flattened first
An interlayer insulating film 4 may be formed. By manufacturing in this manner, flattening in the peripheral region is promoted, so that rubbing can be performed uniformly on the TFT array substrate, and image unevenness due to rubbing can be further reduced.

Note that, on the TFT array substrate 10, in addition to the data line driving circuit 101 and the scanning line driving circuit 104, a sampling circuit for applying an image signal to the plurality of data lines 6a at a predetermined timing, a plurality of Data line 6a
A precharge circuit for supplying a precharge signal of a predetermined voltage level prior to the image signal, an inspection circuit for inspecting the quality, defects, and the like of the electro-optical device during manufacturing or shipping. Good.

In each of the embodiments described above with reference to FIGS. 1 to 18, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, TAB (Tape Automated Bonding) The driving LSI mounted on the substrate may be electrically and mechanically connected via an anisotropic conductive film provided on the periphery of the TFT array substrate 10. For example, the TN mode, V
A-mode, PDLC (Polymer Dispersed Liquid Crysta
l) A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to an operation mode such as a mode or a normally white mode / normally black mode.

Since the electro-optical device in each of the embodiments described above is applied to a projector, three electro-optical devices are used as light valves for RGB, respectively.
The light of each color separated via the dichroic mirror for RGB color separation is incident on each light valve as projection light. Therefore, in each embodiment, the opposing substrate 20 is not provided with a color filter. However, an RGB color filter may be formed on the opposing substrate 20 in a predetermined area facing the pixel electrode 9a where the second light-shielding film 23 is not formed, together with the protective film.
In this way, the electro-optical device in each embodiment can be applied to a direct-view or reflective color electro-optical device other than the liquid crystal projector. Furthermore, one pixel 1
A micro lens may be formed so as to correspond to each of them. Alternatively, it is also possible to form a color filter layer with a color resist or the like under the pixel electrode 9a facing the RGB on the TFT array substrate 10. With this configuration, a bright electro-optical device can be realized by improving the efficiency of collecting incident light. Furthermore, a dichroic filter that produces RGB colors using light interference may be formed by depositing a number of interference layers having different refractive indexes on the counter substrate 20. According to the counter substrate with the dichroic filter, a brighter color electro-optical device can be realized.

(Configuration of Electronic Apparatus) An electronic apparatus using the electro-optical device of the above-described embodiment includes a display information output source 1000, a display information processing circuit 1002, a display drive circuit 1004, and a liquid crystal device shown in FIG. Electro-optical device 10 such as
0, a clock generation circuit 1008 and a power supply circuit 1010. The display information output source 1000 is RO
M, a memory such as a RAM, a tuning circuit for tuning and outputting a television signal, and the like.
Based on the clock from 008, display information such as a video signal is output. The display information processing circuit 1002 processes and outputs display information based on the clock from the clock generation circuit 1008. This display information processing circuit 1002
May include, for example, an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, a clamp circuit, or the like. The display driving circuit 1004 includes a scanning side driving circuit and a data side driving circuit, and drives the liquid crystal panel 1006 for display. The power supply circuit 1010 supplies power to each of the above circuits.

As an electronic device having such a configuration, FIG.
And the like.

FIG. 20 is a schematic configuration diagram showing a main part of the projection display device. In the figure, 1102 is a light source, 1108 is a dichroic mirror, 1106 is a reflection mirror, 1122
Is an entrance lens, 1123 is a relay lens, 1124 is an exit lens, 100R, 100G, 10 and B are liquid crystal light modulators, 1112 is a cross dichroic prism, 11
Reference numeral 14 denotes a projection lens. The light source 1102 includes a lamp such as a metal halide and a reflector that reflects light from the lamp. Dichroic mirror 11 that reflects blue light and green light
Reference numeral 08 transmits red light of the light beam from the light source 1102 and reflects blue light and green light. The transmitted red light is reflected by the reflection mirror 1106 and is incident on the liquid crystal light modulator for red light 100R. On the other hand, the green light among the color lights reflected by the dichroic mirror 1108 is reflected by the green light reflecting dichroic mirror 1108 and is incident on the liquid crystal light modulator for green light 100G. On the other hand, the blue light is transmitted to the second dichroic mirror 110.
8 is also transmitted. For blue light, an incident lens 1122 and a relay lens 11 are used to prevent light loss due to a long optical path.
23, a light guiding means 1121 comprising a relay lens system including an emission lens 1124 is provided, through which blue light is incident on the liquid crystal light modulation device 100B for blue light. The three color lights modulated by the respective light modulators enter the cross dichroic prism 1112. This prism is formed by bonding four right-angle prisms, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface. The three color lights are combined by these dielectric multilayer films to form light representing a color image. The combined light is transmitted through a projection lens 1 as a projection optical system.
The image is projected on a screen 1120 by 114, and the image is enlarged and displayed.

The present invention is not limited to the above-described embodiments, but can be appropriately modified without departing from the spirit and spirit of the invention which can be read from the claims and the entire specification. Such an electro-optical device manufacturing method or electro-optical device is also included in the technical scope of the present invention.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit of various elements, wiring, and the like provided in a plurality of pixels in a matrix forming an image display area in an electro-optical device according to a first embodiment.

FIG. 2 is a plan view of a plurality of adjacent pixel groups of a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in the electro-optical device according to the first embodiment.

FIG. 3 is a sectional view taken along line A-A 'of FIG.

FIG. 4 is a sectional view taken along line B-B 'of FIG.

FIG. 5 is a process chart sequentially illustrating a manufacturing process of the electro-optical device according to the first embodiment.

FIG. 6 is a process chart showing a specific example of a method of forming a groove 4a in a process (d) of FIG.

FIG. 7 is a process chart showing another specific example of a method of forming the groove 4a in the step (d) of FIG.

FIG. 8 is a process chart showing another specific example of a method of forming the groove 4a in the process (d) of FIG.

FIG. 9 is a process chart showing a specific example of a method of forming the data line 6a in the step (e) of FIG.

FIG. 10 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in the electro-optical device according to the second embodiment.

11 is a sectional view taken along the line C-C 'of FIG.

12 is a sectional view taken along line D-D 'of FIG.

FIG. 13 illustrates a configuration of an electro-optical device according to a third embodiment.
FIG. 13 is a cross-sectional view of a portion corresponding to the DD ′ cross-sectional view shown in FIG. 12.

FIG. 14 is a process chart showing a groove excavation step of controlling the depth of a groove 4a using a stopper film in the method of manufacturing an electro-optical device according to the third embodiment.

FIG. 15 is a cross-sectional view of the electro-optical device according to the fourth embodiment, taken along line B- in FIG. 2;
It is sectional drawing in the location corresponding to B 'cross section.

FIG. 16 is a sectional view of the electro-optical device according to the fifth embodiment, taken along line D- in FIG. 10;
It is sectional drawing in the location corresponding to D 'cross section.

FIG. 17 is a plan view of a TFT array substrate in the electro-optical device according to each embodiment, together with components formed thereon, viewed from a counter substrate side.

18 is a sectional view taken along the line H-H 'of FIG.

FIG. 19 is an example of an electronic device.

FIG. 20 is an embodiment of a projection display device as an application example using the present embodiment.

[Explanation of symbols]

 1a Semiconductor layer 1a 'Channel region 1b Low-concentration source region 1c Low-concentration drain region 1d High-concentration source region 1e High-concentration drain region 1f First storage capacitor electrode 2 Insulating thin film 3a Scanning line 3b Capacitance line 4 First interlayer insulating film 4a Groove 4U Lower insulating film 4L Upper insulating film 5 Contact hole 6a Data line 7 Second interlayer insulating film 8 Contact hole 8a Contact hole 8b Contact hole 8c: contact hole 9a: pixel electrode 10: TFT array substrate 11a: light shielding film 12: base insulating film 16: alignment film 20: counter substrate 21: counter electrode 22: alignment film 23: light shielding film 30: pixel switching TFT 50: Liquid crystal layer 70: storage capacitor 70a: first storage capacitor 70b: second storage capacitor 80a: barrier layer 80b: barrier layer 81 ... Second dielectric film

Continued on front page F-term (reference) 2H092 JA25 JA29 JA38 JA42 JA44 JB13 JB23 JB32 JB33 JB38 JB51 JB58 JB63 JB69 KA04 KA07 MA05 MA08 MA14 MA15 MA16 MA18 MA19 MA20 MA23 MA27 MA29 MA35 NA19 NA25 PA07 RA05 5C0919 BAA A43 EA03 EA04 EA07 GB01 5F110 AA18 BB01 BB02 CC02 DD02 DD03 DD05 DD12 DD13 DD14 EE04 EE05 EE09 EE14 EE28 EE45 FF02 FF23 GG02 GG13 GG15 GG24 NN44 HL03 HL04 HL05 NN04 HL05 NN14 HL04 NN35 NN40 NN46 NN54 NN72 NN73 PP01 QQ03 QQ04 QQ05 QQ19

Claims (18)

[Claims] A step of forming a pixel switching element on a substrate; a step of forming one interlayer insulating film above the pixel switching element; a step of flattening the one interlayer insulating film; Forming a groove in the planarized one interlayer insulating film; and forming a data line in the groove so as to be connected to one terminal of the pixel switching element via one contact hole. Forming another interlayer insulating film on the data line; and forming a pixel electrode on the other interlayer insulating film so as to be connected to another terminal of the pixel switching element via another contact hole. Forming an electro-optical device. 2. The step of forming the groove, wherein the time-controlled etching is performed on the one interlayer insulating film such that the depth of the groove corresponds to the thickness of the data line. The method for manufacturing an electro-optical device according to claim 1. 3. In the step of forming one interlayer insulating film, a lower insulating film which is hardly etched by a predetermined type of etchant is formed, and the lower insulating film is relatively etched on the lower insulating film. Forming the one interlayer insulating film having a multilayer structure by forming an upper insulating film having a thickness corresponding to the thickness of the data line, wherein the lower insulating film is formed. 2. The method of manufacturing an electro-optical device according to claim 1, wherein the upper insulating film is subjected to etching using the etchant of the predetermined type until the process reaches. 4. The method according to claim 1, further comprising, before the step of forming the one interlayer insulating film, a step of forming a stopper film functioning as a stopper for a predetermined type of etchant at least in a region where the data line is to be formed. Forming the one interlayer insulating film having a thickness corresponding to the thickness of the data line in the step of forming the one interlayer insulating film; forming the data line in the step of forming the groove; 2. The method of manufacturing an electro-optical device according to claim 1, wherein the one interlayer insulating film is etched using the predetermined type of etchant until reaching the stopper film in a predetermined region. 5. The manufacturing of the electro-optical device according to claim 1, wherein in the step of forming the data line, the data line is formed in the groove by a damascene method. Method. 6. The method according to claim 1, wherein the step of flattening includes a step of flattening by a polishing process.
13. The method for manufacturing an electro-optical device according to claim 1. 7. The method of manufacturing an electro-optical device according to claim 1, wherein the one interlayer insulating film includes a silicon oxide film. 8. The method according to claim 1, further comprising, between the step of forming the one interlayer insulating film and the step of planarizing, performing a heat treatment at 700 ° C. or higher on the one interlayer insulating film. A method for manufacturing the electro-optical device according to claim 1. 9. The electro-optical device according to claim 1, further comprising a step of forming a non-light-transmitting film that covers the data line at least partially when viewed in plan. Device manufacturing method. 10. The same film as the non-light-transmitting film having conductivity simultaneously with the step of forming the non-light-transmitting film between the step of forming the pixel switching element and the step of forming the pixel electrode. The method of manufacturing an electro-optical device according to claim 9, further comprising: forming a conductive film for connecting the pixel electrode to another terminal of the pixel switching element. 11. A step of forming the non-light-transmitting film and at the same time from the same film as the non-light-transmitting film, at least a channel region of a thin film transistor constituting the pixel switching element and a junction between the channel region and the drain region The method of manufacturing an electro-optical device according to claim 9, further comprising a step of forming a light-shielding film that covers the surface when viewed in plan. 12. The step of forming the non-light-transmitting film,
The electricity according to any one of claims 9 to 11, wherein the non-light-transmitting film is formed such that the non-light-transmitting film and the pixel electrode overlap at least partially in plan view. A method for manufacturing an optical device. 13. The step of forming the data line and the step of forming the pixel electrode, the step of forming the data line and the pixel electrode such that the data line and the pixel electrode do not at least partially overlap in plan view. The method of manufacturing an electro-optical device according to claim 12, further comprising forming an electrode. 14. An opening portion serving as an alignment mark for forming the data line at the same time as opening the one contact hole between the step of forming the groove and the step of forming the data line. The method of manufacturing an electro-optical device according to claim 1, further comprising a step of forming a hole. 15. In the step of forming the groove, the groove is formed also in a region where a part of a peripheral circuit is to be formed from the same film as the data line in the flattened interlayer insulating film. 15. The electric device according to claim 1, wherein in the step of forming the data line, a part of the peripheral circuit is also formed in the groove from the same film as the data line. A method for manufacturing an optical device. 16. In the step of forming the pixel switching element, another part of the peripheral circuit is also formed on the substrate, and in the step of forming the one interlayer insulating film, another part of the peripheral circuit is formed. The method of manufacturing an electro-optical device according to claim 15, wherein the one interlayer insulating film is also formed. 17. A pixel switching element, a flattened interlayer insulating film formed above the pixel switching element and formed on the substrate, and a flattened interlayer insulating film formed on the substrate. A data line buried in the groove and connected to one terminal of the pixel switching element via one contact hole, another interlayer insulating film formed on the data line, and the other interlayer insulation An electro-optical device, comprising: a pixel electrode formed on the film and connected to another terminal of the pixel switching element via another contact hole. 18. The electro-optical device according to claim 17, further comprising, on the substrate, a peripheral circuit formed of the same film as the data line and including a portion buried in the groove.