JP2001100647A5 - - Google Patents
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- JP2001100647A5 JP2001100647A5 JP1999280824A JP28082499A JP2001100647A5 JP 2001100647 A5 JP2001100647 A5 JP 2001100647A5 JP 1999280824 A JP1999280824 A JP 1999280824A JP 28082499 A JP28082499 A JP 28082499A JP 2001100647 A5 JP2001100647 A5 JP 2001100647A5
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- wiring
- conductive layer
- groove
- portion crossing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000000758 substrate Substances 0.000 claims description 42
- 239000010408 film Substances 0.000 claims description 5
- 239000004973 liquid crystal related substance Substances 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 5
- 239000011229 interlayer Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims 13
- 230000002093 peripheral Effects 0.000 claims 2
- 239000011159 matrix material Substances 0.000 description 1
Description
【００３１】
本発明の基板装置の他の態様では、前記基板の一方の面上に、画素電極並びに該画素電極及び前記配線に電気的に接続されたスイッチング素子を更に備えており、前記溝内に前記配線及びスイッチング素子が少なくとも部分的に埋め込まれることにより前記基板上における平坦化処理が施されている。[0031]
In another aspect of the substrate device of the present invention, a pixel electrode and a switching element electrically connected to the pixel electrode and the wiring are further provided on one surface of the substrate, and the wiring is provided in the groove. And the planarization process on the said board | substrate is given by the switching element being at least partially embedded.
【００３２】
この態様によれば、基板の一方の面上に、配線のみならず、画素電極と、この画素電極及び配線に電気的に接続されたスイッチング素子が設けられているが、配線及びスイッチング素子は、基板に設けられた溝や層間絶縁膜に設けられた溝内に少なくとも部分的に埋め込まれて、基板上における平坦化処理が施されている。従って、スイッチング素子を備えた基板装置における平坦化が良好に図られる。[0032]
According to this aspect, not only the wiring but also the pixel electrode and the switching element electrically connected to the pixel electrode and the wiring are provided on one surface of the substrate, but the wiring and the switching element are At least partially embedded in a groove provided in the substrate or a groove provided in the interlayer insulating film, planarization processing is performed on the substrate. Therefore, the planarization in the substrate device provided with the switching element can be well achieved.
【００３５】
本発明の電気光学装置の一の態様では、前記電気光学物質は、液晶からなり、前記スイッチング素子は、薄膜トランジスタからなり、前記配線は、前記薄膜トランジスタに電気的に接続されたデータ線及び走査線を含む。[0035]
In one aspect of the electro-optical device of the present invention, the electro-optical material is liquid crystal, the switching element is a thin film transistor, and the wiring is a data line and a scanning line electrically connected to the thin film transistor. Including.
【００３６】
この態様によれば、上述した本発明の基板装置と他の基板との間に液晶が挟持されており、データ線及び走査線に電気的に接続された薄膜トランジスタにより画素電極が駆動されるＴＦＴアクティブマトリクス駆動方式の液晶装置が実現される。特に、基板装置における平坦化が良好に図られているため、基板装置の表面段差による液晶の配向不良が低減されており、極めて高品位の画像表示を行うことが可能とされる。しかも上述した本発明の基板装置を用いることで装置信頼性を十分に高めることも可能となる。[0036]
According to this aspect, the TFT active in which the liquid crystal is held between the above-described substrate device of the present invention and another substrate, and the pixel electrode is driven by the thin film transistor electrically connected to the data line and the scanning line. A matrix drive type liquid crystal device is realized. In particular, since the planarization in the substrate device is satisfactorily achieved, the alignment failure of the liquid crystal due to the surface step of the substrate device is reduced, and it is possible to perform the image display with extremely high quality. Moreover, by using the above-described substrate device of the present invention, the device reliability can be sufficiently improved.
Claims (15)
前記基板の一方の面に溝が設けられており、該溝内に前記配線が部分的に埋め込まれており、
前記配線は、前記溝により生じる段差を横切る部分を有し、該段差を横切る部分は前記配線の他の部分と比べて幅広に形成されていることを特徴とする基板装置。A substrate and a wire disposed on one side of the substrate;
A groove is provided on one surface of the substrate, and the wiring is partially embedded in the groove;
The substrate device, wherein the wire has a portion crossing a step caused by the groove, and a portion crossing the step is formed wider than other portions of the wire.
前記段差を横切る部分において、前記第１導電層からなる配線部分上に、島状且つ幅広の第２導電層が重ねられていることを特徴とする請求項５に記載の基板装置。The wiring portion extending from one end side of the portion crossing the step and the wiring portion extending from the other end side of the portion crossing the step are integrally formed from the same first conductive layer,
The substrate device according to claim 5, wherein an island-shaped wide second conductive layer is superimposed on the wiring portion including the first conductive layer at a portion crossing the step.
前記溝に代えて又は加えて、前記層間絶縁膜の前記配線に対向する側の面に溝が設けられていることを特徴とする請求項１から８のいずれか一項に記載の基板装置。An interlayer insulating film interposed between the substrate and the wiring is further provided on one surface of the substrate,
The substrate device according to any one of claims 1 to 8, wherein instead of or in addition to the groove, a groove is provided on the surface of the interlayer insulating film facing the wiring.
前記溝内に前記電極及び電子素子のうち少なくとも一方が少なくとも部分的に埋め込まれることにより前記基板上における平坦化処理が施されていることを特徴とする請求項１から１０のいずれか一項に記載の基板装置。At least one of an electrode and an electronic device is further provided on one side of the substrate,
11. The method according to any one of claims 1 to 10, wherein at least one of the electrode and the electronic element is at least partially embedded in the groove to perform a planarization process on the substrate. Substrate apparatus as described.
前記溝内に前記配線及びスイッチング素子が少なくとも部分的に埋め込まれることにより前記基板上における平坦化処理が施されていることを特徴とする請求項１から１０のいずれか一項に記載の基板装置。The pixel electrode and the switching element electrically connected to the pixel electrode and the wiring are further provided on one surface of the substrate,
The substrate device according to any one of claims 1 to 10, wherein the wiring and the switching element are at least partially embedded in the groove to perform a planarization process on the substrate. .
前記スイッチング素子は、薄膜トランジスタからなり、
前記配線は、前記薄膜トランジスタに電気的に接続されたデータ線及び走査線を含むことを特徴とする請求項１３に記載の電気光学装置。The electro-optical material comprises liquid crystal,
The switching element comprises a thin film transistor,
The electro-optical device according to claim 13, wherein the wiring includes a data line and a scanning line electrically connected to the thin film transistor.
前記周辺回路に含まれる電子素子に対向する領域における前記基板装置に備えられた基板上には、前記溝が設けられていないことを特徴とする請求項１３又は１４に記載の電気光学装置。And a peripheral circuit formed on the periphery of the image display area and including an electronic element, on the substrate provided in the substrate device.
The electro-optical device according to claim 13, wherein the groove is not provided on a substrate provided in the substrate device in a region facing an electronic element included in the peripheral circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28082499A JP3895507B2 (en) | 1999-09-30 | 1999-09-30 | Substrate device and electro-optical device including the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28082499A JP3895507B2 (en) | 1999-09-30 | 1999-09-30 | Substrate device and electro-optical device including the same |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005357303A Division JP3922293B2 (en) | 2005-12-12 | 2005-12-12 | Substrate device and electro-optical device including the same |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2001100647A JP2001100647A (en) | 2001-04-13 |
| JP2001100647A5 true JP2001100647A5 (en) | 2004-08-05 |
| JP3895507B2 JP3895507B2 (en) | 2007-03-22 |
Family
ID=17630504
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28082499A Expired - Fee Related JP3895507B2 (en) | 1999-09-30 | 1999-09-30 | Substrate device and electro-optical device including the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3895507B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4047586B2 (en) * | 2002-01-10 | 2008-02-13 | Ｎｅｃ液晶テクノロジー株式会社 | Horizontal electric field type active matrix liquid crystal display device |
| JP3778195B2 (en) * | 2003-03-13 | 2006-05-24 | セイコーエプソン株式会社 | Substrate having flattening layer, method of manufacturing the same, substrate for electro-optical device, electro-optical device, and electronic apparatus |
| JP3783707B2 (en) | 2003-03-19 | 2006-06-07 | セイコーエプソン株式会社 | Substrate with inspection element, substrate for electro-optical device, electro-optical device, and electronic apparatus |
| JP5062667B2 (en) * | 2007-05-21 | 2012-10-31 | 株式会社ジャパンディスプレイウェスト | Transflective LCD panel |
| JP2014232338A (en) | 2011-09-26 | 2014-12-11 | シャープ株式会社 | Touch panel and display unit with touch panel |
| JP7449784B2 (en) | 2020-06-15 | 2024-03-14 | スタンレー電気株式会社 | MEMS device manufacturing method and MEMS device |
| CN113066393B (en) * | 2021-03-03 | 2022-07-29 | 武汉华星光电半导体显示技术有限公司 | Display device |
-
1999
- 1999-09-30 JP JP28082499A patent/JP3895507B2/en not_active Expired - Fee Related
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