JP2001087528A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the control burden required for power source interruption monitoring of a game control means in a game machine capable of backing up and storing data required when power source is interrupted. SOLUTION: An IC902 for monitoring power source introduces a +30V power supply voltage and output a voltage lowering signal by judging a power source interruption to be generated when the +30V power supply voltage becomes a prescribed value or below. The voltage lowering signal is supplied to an input terminal (CLK/TRG terminal) of a counter/timer that a CPU 56 incorporates via a buffer circuit. In the counter/timer, '1' is set as an initial value. A count value of the counter/timer at the inside of the CPU 56 is subtracted by 1 and the value becomes '0'. As a result, an interruption is generated and the CPU 56 is capable of performing a required power source interruption time processing by an interruption processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine such as a pachinko game machine or a coin game machine in which a game is played in response to a player's operation. It relates to a gaming machine in which a game is performed.

[0002]

2. Description of the Related Art As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a winning area such as a winning opening provided in the game area, a predetermined number of prize balls are obtained. Are paid out to players.
Furthermore, a variable display unit capable of changing the display state is provided,
There is a configuration in which a predetermined game value is provided to a player when a display result of the variable display unit has a predetermined specific display mode.

[0003] When the display result of the variable display section for displaying a special symbol is a combination of a predetermined specific display mode, it is usually called a "big hit". In addition, the game value is a right to make the state of the variable prize ball device provided in the game area of the gaming machine advantageous for a player who is easy to win a hit ball, or a right for the player to be in an advantageous state. Or to generate.

[0004] When a big hit occurs, for example, a big winning opening is opened a predetermined number of times, and the state shifts to a big hit game state in which a hit ball is easy to win. Then, in each open period, when a predetermined number (for example, 10) of winning prizes is won, the winning prize opening is closed. The number of opening of the special winning opening is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and if the opening time elapses even if the number of winnings does not reach a predetermined number, the winning opening is closed. If the predetermined condition (for example, winning in the V zone provided in the special winning opening) is not satisfied at the time when the special winning opening is closed, the big hit gaming state ends.

[0005] In addition, among the combinations of display modes other than the "big hit" combination, at a stage where some of the display results of the plurality of variable display portions have not been derived and displayed yet, the display results have already been derived and displayed. The state in which the display mode of the variable display unit that satisfies the display condition that is a combination of the specific display modes is called “reach”. If the display result of the identification information variably displayed on the variable display unit does not satisfy the condition of “reach”, the result is “out” and the variable display state ends. A player plays a game while enjoying how to generate a big hit.

When a game ball wins a winning opening provided on the game board, a predetermined number of award balls are paid out. Since the progress of the game is controlled by the game control means mounted on the main board, the number of winning balls based on the winning is determined by the game control means,
Sent to the prize ball control board.

[0007]

As described above, various control means including game control means are mounted on the gaming machine. Generally, each control means is constituted by a microcomputer. That is, a program is stored in a ROM or the like, and data that temporarily occurs in control or data that changes as the control progresses is stored in the RAM. Then, when a power-off state occurs due to a power failure or the like in the gaming machine, data in the RAM is lost. Therefore, at the time of recovery from a power failure or the like, the player must return to the initial state (for example, a state in which the power of the gaming machine is first turned on at the game store for the first time), which may cause disadvantage to the player. There is. For example, if a power failure occurs during a jackpot game and the gaming machine returns to the initial state, the player will not be able to enjoy the benefits based on the occurrence of the jackpot.

In order to avoid such a situation, necessary data is stored in a power supply backup RAM when an unexpected power failure such as a power failure occurs, and data stored when power is restored is restored. And then resume the game. However, when such control is performed, the occurrence of power interruption must be detected by some means. For example, a hardware circuit can detect a drop in the power supply voltage to detect that the power supply has been cut off, but the control means must recognize the result of detection by the hardware circuit. Since the control means constantly controls the gaming device, performing control for detecting a drop in the power supply voltage on top of that increases the control burden. In particular, in recent years, it has been demanded that game effects of game machines be abundant, and it is desirable to minimize the load required for control other than control of the gaming machine.

Accordingly, the present invention provides a gaming machine capable of detecting the occurrence of a power failure by simple control and reducing the control load required for monitoring the power failure of a control means for controlling the gaming machine. The purpose is to provide.

[0010]

A gaming machine according to the present invention comprises:
A game machine capable of giving a game result value to a player as a result of performing a predetermined game, a game control means for controlling the progress of the game, and a predetermined signal when a power supply voltage is monitored and a power supply voltage abnormality is detected. Power control monitoring means for outputting the game control information.The game control means stores the game control microcomputer and the fluctuation data generated when the game control microcomputer performs the control, and the power supply is turned off for at least a predetermined period from the time of the power cut off The game control microcomputer includes a variation data storage means such as a RAM capable of holding the immediately preceding storage content, the game control microcomputer includes an external signal input terminal to which a predetermined signal is input, a register, Register updating means for updating the register value by means of a register, and an external signal input terminal for supplying a predetermined signal to the register updating means. Control microcomputer, the value of the register and executes the at power-off process if it becomes a predetermined value. Note that the game result value is a concept indicating payout of a game ball or an increase in a score in the case of an image-type gaming machine.

The power supply monitoring means may be configured to monitor the voltage drop in a predetermined range and to output a predetermined signal before the game control microcomputer becomes inoperable.

The power supply voltage monitored by the power supply monitoring means is a power supply voltage immediately after conversion from AC to DC, and the power supply monitoring means determines that the power supply voltage has dropped when the power supply voltage drops to a predetermined value. It may be configured.

In the gaming machine, the game control microcomputer creates and saves a checksum of the variable data storage means in the process at the time of power failure, and confirms the validity of the saved data by confirming the checksum when the power is restored. It may be configured as follows.

The game control microcomputer may be configured to initialize the contents of the variation data storage means when it is confirmed that the contents of the checksum are abnormal when the power is restored.

The game control microcomputer may be configured to execute processing for preventing access to the variable data storage means in the processing at the time of power-off.

A backup power supply is supplied to the variable data storage means capable of protecting the storage contents for a predetermined period, and the backup power supply is branched from a power supply supplied to the game control microcomputer and stored therein. Good.

The register updating means subtracts 1 from the value of the register in response to the input of the predetermined signal, and the microcomputer for game control executes a power-off process when the value of the register becomes 0. May be.

The power supply monitoring means includes a second power supply monitoring means for detecting the voltage drop after detecting the voltage drop, and an output of the second power supply monitoring means is connected to a reset terminal of the game control microcomputer, and the output of the game control microcomputer is The computer may be configured to perform a system reset in response to an input to the reset terminal.

[0019]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of the pachinko gaming machine 1 as viewed from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. 3 is a rear view of the pachinko gaming machine 1 as viewed from the back. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine. Further, the present invention can be applied to an image-type gaming machine or a slot machine.

As shown in FIG. 1, the pachinko gaming machine 1 comprises:
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing prize balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided. Behind the glass door frame 2,
The game board 6 is detachably attached. A game area 7 is provided on the front of the game board 6.

In the vicinity of the center of the game area 7, a variable display section 9 for variably displaying a plurality of types of symbols and a 7-segment L
A variable display device 8 including a variable display 10 using an ED is provided. In this embodiment, the variable display section 9 has three symbol display areas of “left”, “middle”, and “right”. On the side of the variable display device 8, a passing gate 11 for guiding a hit ball is provided. The hit ball that has passed through the passing gate 11 is guided to the starting winning opening 14 via the ball exit 13. In a passage between the passage gate 11 and the ball outlet 13, there is a gate switch 12 for detecting a hit ball that has passed through the passage gate 11. In addition, the winning ball that entered the starting winning port 14 is
It is guided to the back of the game board 6 and is detected by the starting port switch 17. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. The variable winning ball device 15 is opened by the solenoid 16.

An opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state) is provided below the variable winning ball apparatus 15. In this embodiment, the opening and closing plate 20 serves as a means for opening and closing the special winning opening. The winning ball that enters one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by the V count switch 22. The winning ball from the opening / closing plate 20 is detected by the count switch 23. Variable display device 8
A start winning prize storage display 18 having four display sections for displaying the number of winning balls entering the starting winning prize port 14 is provided below. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. Then, each time the variable display of the variable display unit 9 is started, the number of the lit display units is reduced by one.

The gaming board 6 is provided with a plurality of winning ports 19 and 24, and winning of the game balls to the winning ports 19 and 24 is detected by the winning port switches 19a and 24a. At the left and right sides of the game area 7, there are provided decorative lamps 25 which are displayed blinking during the game, and at the lower part there is an out port 26 for absorbing hit balls which have not won. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. A gaming effect LED 2 is provided on the outer periphery of the gaming area 7.
8a and gaming effect lamps 28b and 28c are provided.

In this example, one of the speakers 27
Is provided with a prize ball lamp 51 which is lit when a prize ball is paid out, and a ball out lamp 52 which is lit when a supply ball is out is provided near the other speaker 27. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming table 1 and enables lending of balls by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card is ready for use. If there is a fraction (a number less than 100 yen) in the balance information recorded in the card, the fraction is displayed. Fraction display switch 1 for displaying on a frequency display LED provided near hit ball supply tray 3
52, a connecting stand direction indicator 15 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to
3. Card insertion indicator 154 indicating that a card has been inserted into card unit 50, card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back of card insertion slot 155 A card unit lock 156 is provided to release the card unit 50 when checking the mechanism of the writer.

The hit ball fired from the hitting ball launching device enters the game area 7 through the hitting rail, and thereafter, the game area 7
Come down. When a hit ball is detected by the gate switch 12 through the passage gate 11, the display number of the variable display 10 is changed continuously. Further, when a hit ball enters the starting winning opening 14 and is detected by the starting opening switch 17, the symbol in the variable display section 9 starts rotating if the symbol can be changed. If it is not possible to start changing the symbol, the start winning memory is increased by one.

The rotation of the image in the variable display section 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols, the game shifts to a big hit game state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. Then, when a hit ball wins in the specific winning area while the opening and closing plate 20 is opened and is detected by the V count switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. Generation of the continuation right is permitted a predetermined number of times (for example, 15 rounds).

If the combination of images in the variable display section 9 at the time of stoppage is a combination of big hit symbols with probability fluctuation, the probability of the next big hit becomes high. That is, a high probability state, which is more advantageous for the player, is obtained. Also, when the stop symbol on the variable display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the variable display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. On the back of the variable display device 8, as shown in FIG. 2, a prize ball tank 38 is provided above the mechanism plate 36, and when the pachinko gaming machine 1 is installed on the gaming machine installation island, a prize ball is provided from above. Premium ball tank 3
8 is supplied. The prize ball in the prize ball tank 38 reaches the ball payout device through the guide gutter 39.

On the mechanism board 36, a variable display control unit 29 for controlling the variable display section 9 via the relay board 30, and a game control board (main board) covered with a board case 32 and mounted with a game control microcomputer and the like. ) 31, a relay board 33 for relaying a signal between the variable display control unit 29 and the game control board 31, and a prize ball control board on which a prize ball control microcomputer for controlling the payout of prize balls is mounted. 37 are installed. Further, a ball is hit on the lower part of the mechanism plate 36 by using the rotating force of the motor in the game area 7.
Ball launching device 34 that launches on a game effect lamp / LE
D28a, 28b, 28c, a prize ball lamp 51 and a lamp control board 35 for sending signals to the ball out lamp 52 are provided.

FIG. 3 is a rear view of the gaming board of the pachinko gaming machine 1 as viewed from the rear. The ball that passed through the induction gutter 39
As shown in FIG. 3, the ball cut detectors 187a, 187
b, and reaches the ball dispensing device 97 via the ball supply gutters 186a and 186b. The prize ball paid out from the ball payout device 97 is supplied to the hit ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the communication port 45. On the side of the communication port 45, an excess ball passage 46 communicating with the excess ball tray 4 provided on the front of the pachinko gaming machine 1 is formed. A large number of prize balls based on the prize are paid out, and the ball supply tray 3 becomes full. Finally, after the prize balls reach the communication port 45, further prize balls are paid out. It is led to the ball tray 4. When the prize ball is further paid out, the sensing lever 47 is set to the full switch 4.
By pressing 8, the full tank switch 48 is turned on. In this state, the rotation of the stepping motor in the ball discharging device 97 stops, the operation of the ball discharging device 97 stops, and the driving of the hitting ball firing device 34 also stops as necessary. In addition,
In this embodiment, a ball payout device 97 in which game balls are paid out by rotation of a stepping motor is illustrated as a ball payout device that pays out game balls by driving an electric drive source. A ball payout device having a structure of sending out a ball may be used, or a ball payout device having a structure in which a stopper is removed by driving an electric drive source and payout is performed by the weight of the game ball may be used.

Signals from the winning opening switches 19a and 24a, the starting opening switch 17 and the V count switch 22 are sent to the main board 31 in order to perform the prize ball payout control.
When the starting port switch 17 is turned on, the CPU 56 of the main board 31 knows that a winning corresponding to the payout of six winning balls has occurred. Further, when the count switch 23 is turned on, it is known that a winning corresponding to the payout of 15 prize balls has occurred. Then, when the winning opening switch is turned on, it is known that a winning corresponding to the payout of 10 prize balls has occurred. In this embodiment, for example, a game ball that has won the winning opening 24 is detected by the winning opening switch 24 a provided in the winning ball flow path from the winning opening 24, and the game ball that has won the winning opening 19 is detected. Is
It is detected by a winning opening switch 19a provided in a winning ball flow path from the winning opening 19.

FIG. 4 is a block diagram showing an example of the circuit configuration of the main board 31. FIG. 4 also shows the prize ball control board 37, the lamp control board 35, the sound control board 70, the emission control board 91, and the display control board 80.
The pachinko machine 1 is provided on the main board 31 according to the program.
, A switch circuit 58 for giving signals from the gate switch 12, the starting port switch 17, the V count switch 22, the count switch 23, and the winning port switches 19a, 24a to the basic circuit 53, and a variable winning ball device. A solenoid circuit 59 for driving a solenoid 16 for opening and closing the opening 15 and a solenoid 21 for opening and closing the opening and closing plate 20 in accordance with a command from the basic circuit 53; 10 and a lamp / LED circuit 60 for driving the decorative lamp 25.

According to the data supplied from the basic circuit 53, jackpot information indicating occurrence of a jackpot, effective start information indicating the number of start winning balls used to start displaying an image on the variable display section 9, and probability fluctuation have occurred. And an information output circuit 64 that outputs probability change information or the like indicating the fact to a host computer such as a hall management computer.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 used as a work memory, a CPU 56 for performing a control operation in accordance with the control program, and an I / O port unit 57. In this embodiment, the ROM 54 and the RAM 55 are
6 is built in. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to have at least the RAM 55 therein, and the ROM 54 and the I / O port unit 57 may be external or internal. The I / O port unit 57 is a terminal capable of inputting and outputting information in the microcomputer.

Further, the main board 31 has an initial reset circuit 65 for resetting the basic circuit 53 when the power is turned on.
And an address decode circuit 67 that decodes an address signal provided from the basic circuit 53 and outputs a signal for selecting one of the I / O ports in the I / O port unit 57. Although there is switch information input from the ball dispensing device 97 to the main board 31, FIG.
Then they are omitted.

A hit ball launching device that hits and launches a game ball is driven by a drive motor 94 controlled by a circuit on a launch control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

FIG. 5 is a block diagram showing an example of a configuration around the CPU 56 for power supply monitoring and power supply backup. As shown in FIG. 5, the power supply monitoring IC 902
The occurrence of power interruption is detected by introducing a 30V power supply voltage and monitoring the + 30V power supply voltage. Specifically, +
When the 30V power supply voltage becomes equal to or lower than a predetermined value (for example, + 16V), a power-down signal is output and a voltage drop signal is output.
The voltage drop signal is supplied to an input terminal (CLK / TRG terminal) of a counter / timer built in the CPU 56 via a buffer circuit.

It should be noted that the voltage drop signal is directly applied to CLK / TRG
It may be connected to a terminal. In this embodiment, the power supply monitoring IC 902 outputs a high-level voltage drop signal when the monitored voltage falls below a predetermined value.
The count-up or count-down occurs at the rising edge of the input signal. When the power supply monitoring IC 902 outputs a low-level voltage drop signal, an inverting circuit may be used instead of the buffer circuit.

The predetermined value for the power supply monitoring IC 902 to detect the power-off is lower than the normal voltage.
Is a voltage that can operate for a while. Further, the power supply monitoring IC 902 is configured to monitor a voltage higher than the voltage for driving the CPU 56 (+5 V in this example) and immediately after the voltage is converted from AC to DC. The monitoring range can be extended for the required voltage. Therefore, more precise monitoring can be performed. Further, when +30 V is used as the monitoring voltage, since the voltage supplied to the various switches of the gaming machine is +12 V, it is possible to expect prevention of erroneous switch-on detection upon a momentary power interruption. That is, when the voltage of the +30 V power supply is monitored, the voltage of +12 V generated after the generation of +30 V is monitored.
It is possible to detect the decrease before V starts to fall.
Therefore, when the voltage of the + 12V power supply decreases, the switch output comes to the on state. However, if the + 30V power supply voltage that drops faster than + 12V is monitored and the power cutoff is recognized, the power supply is turned on before the switch output turns on. It is possible to enter a state of waiting for restoration and to enter a state where the switch output is not detected.

Further, a power supply monitoring IC is provided on the main board 31.
A second power supply monitoring circuit 903 is mounted in addition to the first power supply monitoring circuit 902. In this example, in the second power supply monitoring circuit 903, the power supply monitoring IC 904
The first power supply monitoring circuit monitors a + 5V power supply voltage which is lower than the voltage monitored by the first power supply monitoring circuit, and generates a low-level voltage drop signal when the voltage value falls below a predetermined value. In addition, + 5V
The power supply voltage is controlled by the gaming machine control microcomputer (C
PU56).

The voltage drop signal from the second power supply monitoring circuit 903 is logically ORed with the initial reset signal from the initial reset circuit 65 and then input to the reset terminal of the CPU 56. Accordingly, when the initial reset signal from the initial reset circuit 65 is at a low level, or when the voltage drop signal from the second power supply monitoring circuit 903 is at a low level, the CPU 56 is in the reset state ( Non-operating state).

When the power supply voltage drops, the power supply monitoring I
The power monitoring IC 9 generates a low-level voltage drop signal by the C 904 later than the power monitoring IC 902 generates a voltage drop signal.
A threshold level 04 (voltage level at which a voltage drop signal is generated) is set. For example, the threshold is 4.25V. 4.25V is lower than normal voltage,
Reference numeral 56 denotes a voltage that can operate for a while.

The reset I of the initial reset circuit 65
When the power of the gaming machine is turned on and the voltage of the + 5V power supply rises, the C651 sets the output signal to a high level when the + 5V power supply voltage exceeds a predetermined value. That is, the initial reset signal is turned off. Although the power supply monitoring ICs 902 and 904 monitor different power supply voltages here, the same power supply voltage may be monitored. For example, both may monitor the +30 V power supply voltage. Then, for example, one detection voltage (a voltage at which a voltage drop signal is output) is set to +16 V, and the other detection voltage is set to +8 V. In such a configuration, since the same voltage is monitored, the difference between the timing at which the first voltage monitoring means outputs the voltage drop signal and the timing at which the second voltage monitoring means outputs the voltage drop signal is obtained. The predetermined period can be reliably set to a desired value.

Further, one power supply monitoring IC set to output each voltage drop signal when each monitoring voltage drops to each predetermined value may be used. For example, one power supply monitoring IC has + 16V and +8
V may be monitored. In that case,
The first power supply monitoring means and the second power supply monitoring means can be realized by one power supply monitoring IC. Further, in this embodiment, the power supply monitoring means is provided on the main board 31, but may be mounted on the power supply board.

While no power is supplied from the + 5V power supply, at least a part of the RAM is backed up by a backup power supply supplied from a power supply board, and its contents are preserved even when the power supply to the gaming machine is cut off. And +
When the 5V power is restored, a reset signal is issued from the initial reset circuit 65, and the CPU 56 returns to the normal operation state. At that time, since the necessary data is backed up, it is possible to return to the gaming state at the time of the occurrence of the power failure when recovering from a power failure or the like.

The one-chip microcomputer generally has a built-in counter / timer that can be used as a timer or a counter. CPU 56 used in this embodiment
Also incorporate some counter / timers. As shown in FIG. 6, the counter / timer 561 has a CLK / TR
It counts down at the rise or fall of the signal input to the G terminal. Then, when counting up (when the count becomes 0), the interrupt controller 562 can detect the fact and generate various interrupts, for example. FIG. 6 shows only one counter / timer 561.

FIG. 7 is an explanatory diagram showing a counter and a control register constituting the counter / timer 561. In this example, a 16-bit counter is provided as a counter constituting the counter / timer 561, and data for setting the mode (usage) of the counter / timer 561 is set in the control register.

FIG. 8 is a block diagram showing an example of the configuration of the power supply board 910. The power supply board 910 includes a main board 31, a display control board 80, a sound control board 70, and a lamp control board 35.
And it is installed independently of a control board such as the prize ball control board 37, and generates a voltage used by each control board and mechanical components in the gaming machine. In this example, AC24V, DC + 30
V, + 21V DC, + 12V DC and + 5V DC. Also, a capacitor 91 serving as a backup power supply
6 is charged from DC + 5V, that is, a power supply line for driving ICs and the like on each substrate.

The transformer 911 converts an AC voltage from an AC power supply to 24V. AC 24V voltage is applied to connector 9
15 is output. Further, the rectifier circuit 912 includes an AC24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
The C converter 913 has + 21V, + 12V and + 5V.
V is generated and output to the connector 915. Connector 91
Reference numeral 5 is connected to, for example, a relay board, from which power of a voltage required for each control board and mechanical components is supplied.

+5 V from DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 serves as a backup power supply for a backup RAM (RAM that is backed up) when the power supply to the gaming machine is cut off. Further, a diode 917 for preventing backflow is inserted between the + 5V line and the backup + 5V line.

Next, the operation of the gaming machine will be described. FIG.
Is a flowchart showing a main process of a game control program executed by the CPU 56 on the main board 31.
When the power to the gaming machine is turned on, in the main processing, the CPU 56 first checks whether or not the power has been restored from the power failure (step S1). Whether or not recovery from a power failure has occurred is confirmed by a power failure flag set in the backup RAM area when the power is turned off. That is, based on the fact that predetermined data is stored in the backup RAM area at the time of recovery from a power failure, while the content of the RAM is undefined otherwise,
Whether or not it is time to recover from a power failure can be confirmed based on whether or not the power failure flag is set.

If it is time to recover from a power failure, the CP
U56 executes a power failure recovery process described later (step S3). If not, an initialization process is performed.
Thereafter, in the main process, the process shifts to a loop process in which the monitoring of the timer interrupt flag (step S7) is confirmed.
In the loop, the display random number update process (step S
6) is also executed.

In the initialization process, as shown in FIG. 10, the register and RAM are cleared (step S2a).
After the necessary initial value setting process (step S2b) is performed, the timer register provided in the CPU 56 is initialized (timeout is 2 ms) so that a timer interrupt is periodically performed every 2 ms. The setting for operating the repetition timer is performed (step S2c). That is, in step S2c, a process of activating a timer interrupt and a process of setting a timer interrupt interval are executed.

The initial value setting process (step S2b)
In this case, "1" is set as an initial value in the 16-bit counter of the counter / timer 561,
Settings such as counting down in response to a rising input to the RG terminal and generating an interrupt when the count value becomes "0" are made in the control register.

In this embodiment, an internal timer of the CPU 56 (for example, a counter / timer other than the counter / timer 561) is set to repeatedly generate a timer interrupt. Then, as shown in FIG. 11, when a timer interrupt occurs, the CPU 56 sets a timer interrupt flag (step S11).

When detecting that the timer interrupt flag is set in step S7, the CPU 56 resets the timer interrupt flag (step S7).
8), a game control process is executed (step S9). According to the above control, in this embodiment, the game control process is started every 2 ms.

FIG. 12 is a flowchart showing a game control process. In the game control process, the CPU 56 first performs a process of setting a display control command sent to the display control board 80 in a predetermined area of the RAM 55 (display control data setting process: step S21), and then executes the display control command. Output processing is performed (display control data output processing: step S22).

Next, processing for outputting the contents of the storage area for various output data to each output port is performed (data output processing: step S23). Further, an output data setting process for setting output data such as big hit information, start information, and probability variation information output to the hall management computer in the storage area is performed (step S24). Further, various abnormality diagnosis processes are performed by the self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S25).

Next, a process of updating each counter indicating a random number for determination such as a random number for big hit determination used in game control is performed (step S26).

Further, the CPU 56 performs a special symbol process (step S27). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Further, a normal symbol process is performed (step S28). In the normal symbol process process, a corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

The CPU 56 further includes a switch circuit 58
, The state of the gate sensor 12, the starting port sensor 17, the count sensor 23, and the winning port switches 19a and 24a are input, and it is determined whether or not each of the winning ports and the winning device has a winning (switch processing: step S29). .
The CPU 56 further performs a process of updating a display random number such as a random number that determines the type of stop symbol (step S3).
0).

Further, the CPU 56 performs signal processing with the award ball control board 37 (step S31). That is,
When a predetermined condition is satisfied, a prize ball control command is output to the prize ball control board 37. The prize ball control CPU mounted on the prize ball control board 37 drives the ball payout device 97 according to the prize ball control command.

As described above, the main process includes the process of determining whether or not to shift to the game control process.
Since a flag is set to determine whether or not to shift to the game control process in the timer interrupt process based on the timer interrupt that is periodically generated by the 56 internal timers, all the game control processes are reliably executed. Is done. In other words, until all of the game control processes have been executed, it is not determined whether or not to shift to the next game control process, so it is guaranteed that all processes in the game control process will be completed. ing.

In the conventional general game control process, the initial state is forcibly returned to the initial state by an external interrupt that occurs periodically. Explaining in accordance with the example shown in FIG. 12, for example, even during the process of step S31, the process is forcibly returned to the process of step S21. In other words, there is a possibility that the next game control process will be started before all the processes in the game control process are completed.

Here, the game control process executed by the CPU 56 of the main board 31 is executed according to the flag set in the timer interrupt process based on the timer interrupt generated by the internal timer of the CPU 56 periodically. , A hardware circuit that periodically generates a signal (for example, every 2 ms) is provided,
A signal from the circuit may be introduced into an external interrupt terminal of the CPU 56, and a flag for determining whether or not to shift to the game control process based on the interrupt signal may be set. Even in such a configuration, the flag is not determined until all of the game control processing is executed.
It is guaranteed that all processes in the game control process are completed.

When the power supply is cut off due to an unexpected power failure or the like, the voltage of each DC power supply such as +30 V or +5 V gradually decreases. The power supply monitoring IC 902 shown in FIG.
Sets the output to a high level when the + 30V power supply voltage drops to a predetermined value. That is, a voltage drop signal is generated. Then, the counter / timer 56 inside the CPU 56
The count value of 1 is decremented by one. Counter / Timer 561
Is "1", the value is "0". As a result, an interrupt occurs.

FIG. 13 is a flowchart showing an example of a power failure occurrence interrupt process started by an interrupt generated based on the value of the counter / timer 561 becoming "0". In the power failure occurrence interrupt processing, the CPU 56 first
The interrupt is prohibited (step S41). In the power failure occurrence process, a checksum generation process is performed to ensure that the contents of the RAM are preserved. If other interrupt processing is performed during the processing, C is generated before the checksum generation processing is completed.
Since it is conceivable that the voltage may drop to a voltage at which the PU cannot operate, first, settings are made so that other interrupts do not occur.

Then, the power failure flag is set in the RAM area where the power is backed up (step S42).
Further, a power failure preparation command is issued to the prize ball control board 37 (step S43). Upon receiving the power failure preparation command, the CPU mounted on the prize ball control board 37 recognizes that a power failure will occur, and executes a predetermined power-off process.

Next, the CPU 56 turns off all the output ports (step S44). Then, if necessary, the contents of each register are stored in the backup RAM area (step S45). Further, an appropriate initial value is set in the backup check data area of the backup RAM area (step S46), and exclusive OR is sequentially performed on the initial value and the data of the backup RAM area (step S47) to obtain a final operation value. Is set in the backup parity data area (step S48).

Thereafter, a loop is made with the RAM access prohibited (step S49). When the power supply voltage decreases, the levels of various signal lines become unstable and the RAM
Although the contents may be garbled, the data in the backup RAM will not be garbled if the RAM access is prohibited in this manner.

FIG. 14 is an explanatory diagram showing the state of the +30 V power supply voltage when the power is turned off, the signal input to the CLK / TRG terminal, and the count value of the counter / timer 561.
As shown in FIG. 14, when the +30 V power supply voltage drops to +16 V, the signal input to the CLK / TRG terminal rises, so that the count value of the counter / timer 561 becomes “0”. Accordingly, a power failure occurrence interrupt occurs, and the power failure occurrence interrupt processing shown in FIG. 13 is executed.

FIG. 15 shows a power failure recovery process (step S3).
6 is a flowchart illustrating an example of the above. In the power failure recovery processing, the CPU 56 first performs data check (parity check in this example) of the backup RAM area (step S51). If the power is restored after an unexpected power failure, the data in the backup RAM area should have been saved, and the check result becomes normal.
If the check result is not normal, since the internal state cannot be returned to the state at the time of power failure, the same initialization processing as the initialization processing (step S2) executed at the time of power-on without power recovery is executed. (Steps S52 and S5
4).

If the check result is normal, the CPU 56
Performs a game state restoring process for returning the internal state to the state when the power is turned off (step S53).

Here, in step S1, it is confirmed whether or not the power is restored from the power failure. If the power is restored from the power failure, the parity check is performed. First, the parity check is executed and the check result is normal. Otherwise, it is determined that it is not the recovery from the power failure, and the initialization processing of step S2 is executed, and if the check result is normal, the game state return processing may be performed. That is, it may be determined based on the result of the parity check whether recovery from a power failure has occurred.

FIG. 16 is an explanatory diagram for explaining a backup parity data creating method. However, FIG.
In the example shown in FIG.
The size of the data in the M area is 3 bytes. In the power failure generation process based on the power supply voltage drop, as shown in FIG. 16A, initial data (00H in this example) is set in the backup check data area. Next, "00
The exclusive OR of “H” and “F0H” is calculated, and the result is exclusive ORed with “16H”. Further, an exclusive OR of the result and “DFH” is obtained. Then, the result (“39H” in this example) is set in the backup parity data area.

When the power is turned on again, the parity diagnosis is performed in the power failure recovery processing. FIG. 16B is an explanatory diagram showing an example of the parity diagnosis. If all the data in the backup area is stored as it is, the data as shown in FIG. 16A is set in the backup area when the power is turned on again.

In the process of step S51, the CPU 5
6 is the data set in the backup parity data area of the backup RAM area (in this example, “39”).
H)) as initial data, a process of sequentially taking an exclusive OR for each data in the backup data area is performed.
If all the data in the backup area is stored as it is, the final calculation result is “00H”, that is, the same as the data set in the backup check data area. If a bit error has occurred in the data in the backup RAM area, the final calculation result is “00”.
H ".

Therefore, the CPU 56 compares the final operation result with the data set in the backup check data area, and if they match, determines that the parity diagnosis is normal. If they do not match, it is determined that the parity diagnosis is abnormal.

Hereinafter, the game state restoring process will be described. First, in this embodiment, the CP of the main substrate 31
A display control command, a sound control command, and a lamp control command that the U56 sends to the display control board 80, the sound control board 70, and the lamp control board 35 will be described.
Each control command is determined to be sent according to the progress of the game in the special symbol process process (step S28) in the game control process shown in FIG. 12, and specific data is displayed in the display control data setting process (step S21). Is set, and is transmitted by being output from the output port in the display control data output process (step S22).

FIG. 17A is an explanatory diagram showing an example of the transmission timing of each control command relating to the symbol variation on the variable display section 9. In this embodiment, the C
When starting the symbol change, the PU 56 sends a change start command to each of the display control board 80, the sound control board 70, and the lamp control board 35. To the display control board 80, a symbol designating command indicating a fixed symbol of the middle left and right symbols is further transmitted.

When the symbol variation is determined, a variation stop command is sent to each of the display control board 80, the sound control board 70, and the lamp control board 35.
Each CPU mounted on the display control board 80, the sound control board 70, and the lamp control board 35 performs display control, sound generation control, and lamp lighting control according to the variation mode specified by the variation start command. The change start command includes information indicating the change time.

FIG. 17B is an explanatory diagram showing an example of the transmission timing of each control command related to the big hit game executed when the display result of the variable display section 9 is a predetermined big hit symbol. In this embodiment, the CPU of the main board 31
56 sends a big hit start command to each of the display control board 80, the sound control board 70, and the lamp control board 35 at the start of the big hit game. After a lapse of a predetermined time, a one-round (1R) designation command is transmitted. When each CPU mounted on the display control board 80, the sound control board 70, and the lamp control board 35 receives the big hit start command, it performs display control, sound generation control, and lamp lighting control at the start of the big hit. When a one-round designation command is received, display control, sound generation control, and lamp lighting control during a big hit are performed. However, the display control board 80
CPU performs the first round of display.

Thereafter, the CPU 56 of the main board 31 sequentially sends commands indicating each round to the display control board 80. The CPU of the display control board 80 performs corresponding display control according to these commands.

At the end of the big hit game, the CPU 56 of the main board 31 sends a big hit end command to each of the display control board 80, the sound control board 70 and the lamp control board 35. Then, after a predetermined time has elapsed, a normal screen display command is transmitted. Each gaming machine control means,
When a normal screen display command is received, the control state is set to a game waiting state.

FIG. 18 is a flowchart showing an example of the game state restoring process performed in the power failure restoring process shown in FIG. In this example, if it is necessary to restore the contents of the register, the CPU 56 restores the value stored in the backup RAM to the register (step S61). Then, the game state at the time of the power failure is confirmed based on the data stored in the backup RAM. For example, the gaming state can be confirmed by the value of the special symbol process flag corresponding to the progress of the special symbol process.

If the game state is a symbol change (step S62), control is performed to send a change start command to the display control board 80, the sound control board 70, and the lamp control board 35 (step S63). If the gaming state is a jackpot game (step S64), the last transmitted control command before the power failure is displayed on the display control board 8.
0, control to send to the sound control board 70 and the lamp control board 35 is performed (step S65). When the game state is other than the above, for example, the normal screen display command is transmitted to the display control board 80 and the sound control board 7.
0 and control to send to the lamp control board 35 is performed (step S66).

FIG. 19 is an explanatory diagram showing an example of the control state when the power is restored after a power failure has occurred. In FIG. 19, the variable display state is realized by the CPU (display control means) of the display control board 80, and the sound state is set by the sound control board 7
0 is realized by the CPU (sound control means), and the state of the lamp is controlled by the CPU (lamp control means) of the lamp control board 35.
It is realized by.

FIG. 19A shows an example in which the power is restored after a power failure occurs during the change of the symbol. In this case, when the power is restored, a change start command is sent from the main board 31 (step S63 in FIG. 15). Since the change start command is a command sent at the start of the symbol change,
The states of the variable display control, the sound control, and the lamp control return to the states at the start of the change. In this embodiment, the fluctuation start command includes information for specifying the fluctuation time, and the main board 3
After transmitting the fluctuation start command, the first CPU 56 does not transmit anything (except for the symbol designation command) until the finalization command at the end of fluctuation (fluctuation stop command). Therefore, if a power failure occurs during the symbol change, the change cannot be restarted from the state in the middle of the change, but the display control, sound control, and lamp control are synchronized by resending the change start command. Return to

In the main board 31, various parameters used at the start of the fluctuation are stored in the backup RAM. Therefore, the display results (fixed symbols) and the like in the fluctuations after the restoration of the power supply are the same as the display results and the like that would have been made in the fluctuations interrupted by the power failure. Therefore, there is no disadvantage to the player.

FIG. 19B shows an example of a case where the power is restored after a power failure occurs during the big hit game. In this case, when the power is restored, the command sent from the main board 31 to the display control board 80, the sound control board 70, and the lamp control board 35 last before the power failure is sent again (step S65 in FIG. 18). Therefore, the sound control and the lamp control return to the control state during the big hit game. In addition, the display control also returns to the state performed at the time of the power failure.

In the main board 31, various parameters during the big hit game (number of times of opening of the special winning opening, number of winning balls of the special winning opening, etc.) are stored in the backup RAM. Therefore, since the game state for the player also returns to the state before the power failure, there is no disadvantage to the player.

As described above, the output signal of the power supply monitoring means is input to the built-in counter / timer (register updating means) of the game control microcomputer. The counter / timer updates the value of a counter (register), which is a component of the counter / timer. Then, when the value of the counter reaches a predetermined value (“0” in this example),
A power failure occurrence interrupt process is executed as a process at the time of power failure. Therefore, the game control microcomputer can start the power-off processing only by generating an interrupt without performing any monitoring processing. That is, the game control microcomputer can set the trigger of the interruption when the power is turned off only by setting the initial value in the register. Therefore, the power supply monitoring process is simplified, and the load required for the power supply monitoring process is reduced.

In the above embodiment, the case where the power supply monitoring process, the data saving process, and the restoring process are performed in the game control unit has been described. The power supply is backed up, and the display control unit, the sound control unit, and the lamp control unit may also perform the above-described processing. However, the display control means, the sound control means, and the lamp control means do not need to perform the command transmission processing at the time of restoration.

Further, in the above-described embodiment, in the power failure occurrence processing, the loop is lastly performed for waiting for the power-off.
The output signal of the power supply monitoring means may be monitored to return to the original state when it is detected that the power supply has been restored. In the case of such a configuration, the game can be continued in a case where a momentary power interruption occurs and the power is restored in a short time.

In the pachinko gaming machine 1 according to each of the above-described embodiments, when a special symbol is variably displayed on the variable display portion 9 based on a winning start, a predetermined symbol combination becomes a predetermined game value. Although it was a first-class pachinko gaming machine that can be given to a player, a predetermined game value that can be given to a player when there is a prize in a predetermined area of an electric accessory that is opened based on a start winning prize. Two types of pachinko machines,
A third-type pachinko gaming machine in which a predetermined right is generated or continued when there is a prize in a predetermined electric accessory which is opened when a stop symbol of a symbol variably displayed based on a start winning prize is a predetermined combination of symbols. Even so, the present invention can be applied.

[0097]

As described above, according to the present invention, the gaming machine is provided with the register updating means for updating the register value in response to the input of the predetermined signal from the power supply monitoring means. Since the power-off processing is executed when the value of the register reaches a predetermined value, the control load required for the power-off monitoring of the game control means can be reduced.

When the power supply monitoring means is configured to monitor a voltage drop in a predetermined range and to output a predetermined signal at a stage before the game control microcomputer becomes inoperable, when the power supply is cut off, The predetermined signal can be output at any stage where the processing can be performed.

The power supply voltage monitored by the power supply monitoring means is the power supply voltage immediately after conversion from AC to DC. The power supply monitoring means determines that the power supply voltage has dropped when the power supply voltage drops to a predetermined value. When configured, the monitoring range can be expanded for the voltage required by the game control microcomputer, and more precise monitoring can be performed.

The game control microcomputer creates and saves a checksum of the variable data storage means in the process at the time of power failure, and confirms the validity of the saved data by checking the checksum when the power is restored. In this case, it is possible to check whether the data is destroyed based on the checksum when the power is restored, and the reliability of the stored data can be improved.

If the game control microcomputer is configured to initialize the contents of the fluctuating data storage means upon confirming that the contents of the checksum is abnormal when the power is restored, based on the abnormal data. This prevents the gaming state from being restored.

If the game control microcomputer is configured to execute processing for preventing access to the variable data storage means in power-off processing, data in the RAM may be destroyed when power is turned off. There is an effect that there is no.

A backup power supply is supplied to the variable data storage means capable of protecting the storage contents for a predetermined period, and the backup power supply is configured to be stored by branching off from a power supply supplied to the game control microcomputer. In this case, it is not necessary to provide a power supply for power storage, and the cost of the gaming machine can be reduced.

The register updating means subtracts 1 from the value of the register in response to the input of the predetermined signal, and the microcomputer for game control is configured to execute a power-off process when the value of the register becomes 0. In such a case, a configuration is realized in which the control load required for monitoring the power-off of the game control means can be reduced by simple control.

The power supply monitoring means includes a second power supply monitoring means for detecting a voltage drop after detecting the voltage drop, and when the output of the second power supply monitoring means is connected to the reset terminal of the game control microcomputer. Since the game control microcomputer is reset during the voltage drop, abnormal operation based on indefinite data is prevented.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is a front view of the gaming board of the pachinko gaming machine as viewed from the front.

FIG. 3 is a rear view of the pachinko gaming machine as viewed from the rear.

FIG. 4 is a block diagram showing a circuit configuration example of a game control board (main board).

FIG. 5: C for power supply monitoring and power supply backup
FIG. 3 is a block diagram illustrating a configuration example around a PU.

FIG. 6 is a block diagram showing a counter / timer and the like built in the CPU.

FIG. 7 is an explanatory diagram showing a counter and a control register which constitute a counter / timer.

FIG. 8 is a block diagram illustrating a configuration example of a power supply board.

FIG. 9 is a flowchart showing the operation of the basic circuit on the main board.

FIG. 10 is a flowchart illustrating initialization processing.

FIG. 11 is a flowchart showing a 2 ms timer interrupt process.

FIG. 12 is a flowchart showing a game control process.

FIG. 13 is a flowchart illustrating a power failure generation process.

FIG. 14 shows the state of +30 V power supply voltage when power is turned off, CL
FIG. 4 is an explanatory diagram showing signals input to a K / TRG terminal and count values of a counter / timer.

FIG. 15 is a flowchart illustrating a power failure recovery process.

FIG. 16 is an explanatory diagram for describing a backup parity data creation method.

FIG. 17 is an explanatory diagram showing an example of transmission timing of each control command from the main board.

FIG. 18 is a flowchart illustrating an example of a game state restoration process.

FIG. 19 is an explanatory diagram illustrating an example of a control state when the power is restored after a power failure occurs.

[Explanation of symbols]

 1 Pachinko machine 31 Main board 53 Basic circuit 56 CPU 561 Counter / timer 902 Power supply monitoring IC 910 Power supply board 916 Capacitor

Claims (9)

[Claims] 1. A game machine capable of giving a game result value to a player as a result of playing a predetermined game, a game control means for controlling the progress of the game, a power supply voltage monitoring and a power supply voltage abnormality. And a power supply monitoring means for outputting a predetermined signal when detecting the game control means, the game control means stores a game control microcomputer, and fluctuation data generated when the game control microcomputer performs control, and from when power is turned off. A variable data storage unit capable of retaining storage contents immediately before power-off for at least a predetermined period; a register; a register updating unit for updating a value of the register in response to the input of the predetermined signal; An external signal input terminal for supplying the predetermined signal to the updating means, wherein the game control microcomputer has a value of the register Gaming machine and to execute the at power-off process if it becomes a predetermined value. 2. The gaming machine according to claim 1, wherein the power supply monitoring means monitors a voltage drop in a predetermined range and outputs a predetermined signal before the game control microcomputer becomes inoperable. 3. The power supply voltage monitored by the power supply monitoring means is a power supply voltage immediately after conversion from AC to DC, and the power supply monitoring means reduces the power supply voltage when the power supply voltage decreases to a predetermined value. The gaming machine according to claim 1, wherein the gaming machine is determined to be: 4. The game control microcomputer creates and saves a checksum of the variable data storage means in a process when the power is turned off, and confirms the validity of the saved data by checking the checksum when the power is restored. The gaming machine according to claim 1. 5. The gaming machine according to claim 4, wherein the game control microcomputer initializes the contents of the variable data storage means when it is confirmed that the contents of the checksum are abnormal when the power is restored. 6. The gaming machine according to claim 1, wherein the game control microcomputer executes a process for preventing access to the variable data storage means in a process when the power is turned off. 7. A backup power supply is supplied to a variable data storage means capable of protecting stored contents for a predetermined period, and the backup power supply is branched from a power supply supplied to a game control microcomputer and stored. The gaming machine according to claim 6. 8. The register updating means decrements the value of the register by one in response to the input of the predetermined signal, and the game control microcomputer executes a power-off process when the value of the register becomes zero. The gaming machine according to claim 1. 9. A power supply monitoring means comprising: a second power supply monitoring means for detecting a voltage drop after detecting a voltage drop; an output of the second power supply monitoring means is connected to a reset terminal of a game control microcomputer; 9. The gaming machine according to claim 1, wherein the gaming control microcomputer performs a system reset in response to an input to a reset terminal.