JP2001085819A - 集積回路応力低減装置 - Google Patents
集積回路応力低減装置Info
- Publication number
- JP2001085819A JP2001085819A JP2000228296A JP2000228296A JP2001085819A JP 2001085819 A JP2001085819 A JP 2001085819A JP 2000228296 A JP2000228296 A JP 2000228296A JP 2000228296 A JP2000228296 A JP 2000228296A JP 2001085819 A JP2001085819 A JP 2001085819A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- board
- stress
- ring
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Materials Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Wire Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/369,898 US6320754B1 (en) | 1999-08-06 | 1999-08-06 | Apparatus for the reduction of interfacial stress caused by differential thermal expansion in an integrated circuit package |
| US369898 | 1999-08-06 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001085819A true JP2001085819A (ja) | 2001-03-30 |
| JP2001085819A5 JP2001085819A5 (enExample) | 2007-09-06 |
Family
ID=23457388
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000228296A Withdrawn JP2001085819A (ja) | 1999-08-06 | 2000-07-28 | 集積回路応力低減装置 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6320754B1 (enExample) |
| JP (1) | JP2001085819A (enExample) |
| KR (1) | KR100709832B1 (enExample) |
| DE (1) | DE10034309B4 (enExample) |
| GB (1) | GB2356084B (enExample) |
| TW (1) | TW497233B (enExample) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030116860A1 (en) * | 2001-12-21 | 2003-06-26 | Biju Chandran | Semiconductor package with low resistance package-to-die interconnect scheme for reduced die stresses |
| US7235886B1 (en) * | 2001-12-21 | 2007-06-26 | Intel Corporation | Chip-join process to reduce elongation mismatch between the adherents and semiconductor package made thereby |
| US20040240188A1 (en) * | 2003-05-28 | 2004-12-02 | Cromwell Stephen Daniel | Protective coating for attach hardware for circuits |
| DE10340866A1 (de) * | 2003-09-04 | 2005-03-31 | Siemens Ag | Verfahren zum Befestigen einer Elementgruppe an einer Trägerschicht |
| US20120081872A1 (en) | 2010-09-30 | 2012-04-05 | Alcatel-Lucent Canada Inc. | Thermal warp compensation ic package |
| DE102018104521B4 (de) * | 2018-02-28 | 2022-11-17 | Rogers Germany Gmbh | Metall-Keramik-Substrate |
| CN108550559B (zh) * | 2018-05-28 | 2024-07-30 | 北京比特大陆科技有限公司 | 散热片、芯片组件及电路板 |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55107247A (en) * | 1979-02-09 | 1980-08-16 | Matsushita Electric Ind Co Ltd | Hybrid integrated circuit |
| US4437718A (en) * | 1981-12-17 | 1984-03-20 | Motorola Inc. | Non-hermetically sealed stackable chip carrier package |
| JPS58138050A (ja) * | 1982-02-10 | 1983-08-16 | Sumitomo Electric Ind Ltd | 半導体装置の製造方法 |
| EP0452752B1 (en) | 1990-04-16 | 1996-12-18 | Fujitsu Limited | Chip carrier for enabling production of high performance microwave semiconductor device by disposing semiconductor chip thereon |
| GB2276977B (en) | 1992-12-08 | 1996-09-18 | Hughes Aircraft Co | Thermal matched ic chip assembly and fabrication method |
| JP2541487B2 (ja) * | 1993-11-29 | 1996-10-09 | 日本電気株式会社 | 半導体装置パッケ―ジ |
| US5455387A (en) * | 1994-07-18 | 1995-10-03 | Olin Corporation | Semiconductor package with chip redistribution interposer |
| US5766982A (en) * | 1996-03-07 | 1998-06-16 | Micron Technology, Inc. | Method and apparatus for underfill of bumped or raised die |
| JP2828021B2 (ja) * | 1996-04-22 | 1998-11-25 | 日本電気株式会社 | ベアチップ実装構造及び製造方法 |
| US5868887A (en) | 1996-11-08 | 1999-02-09 | W. L. Gore & Associates, Inc. | Method for minimizing warp and die stress in the production of an electronic assembly |
| US5844319A (en) * | 1997-03-03 | 1998-12-01 | Motorola Corporation | Microelectronic assembly with collar surrounding integrated circuit component on a substrate |
| US6011304A (en) * | 1997-05-05 | 2000-01-04 | Lsi Logic Corporation | Stiffener ring attachment with holes and removable snap-in heat sink or heat spreader/lid |
| US5877070A (en) * | 1997-05-31 | 1999-03-02 | Max-Planck Society | Method for the transfer of thin layers of monocrystalline material to a desirable substrate |
| US5909057A (en) * | 1997-09-23 | 1999-06-01 | Lsi Logic Corporation | Integrated heat spreader/stiffener with apertures for semiconductor package |
| US5936304A (en) | 1997-12-10 | 1999-08-10 | Intel Corporation | C4 package die backside coating |
| US6081416A (en) * | 1998-05-28 | 2000-06-27 | Trinh; Hung | Lead frames for mounting ceramic electronic parts, particularly ceramic capacitors, where the coefficient of thermal expansion of the lead frame is less than that of the ceramic |
-
1999
- 1999-08-06 US US09/369,898 patent/US6320754B1/en not_active Expired - Fee Related
-
2000
- 2000-05-22 TW TW089109865A patent/TW497233B/zh not_active IP Right Cessation
- 2000-07-11 GB GB0017054A patent/GB2356084B/en not_active Expired - Fee Related
- 2000-07-14 DE DE10034309A patent/DE10034309B4/de not_active Expired - Fee Related
- 2000-07-28 JP JP2000228296A patent/JP2001085819A/ja not_active Withdrawn
- 2000-08-04 KR KR1020000045190A patent/KR100709832B1/ko not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| GB2356084B (en) | 2003-10-22 |
| KR20010021214A (ko) | 2001-03-15 |
| GB0017054D0 (en) | 2000-08-30 |
| TW497233B (en) | 2002-08-01 |
| KR100709832B1 (ko) | 2007-04-23 |
| DE10034309B4 (de) | 2004-03-04 |
| US6320754B1 (en) | 2001-11-20 |
| DE10034309A1 (de) | 2001-04-05 |
| GB2356084A (en) | 2001-05-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20060629 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20061130 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070723 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070723 |
|
| A761 | Written withdrawal of application |
Free format text: JAPANESE INTERMEDIATE CODE: A761 Effective date: 20090227 |