JP2001085679A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability and manufacturing yield of a minute MISFET(metal insulator semiconductor filed effect transistor) by suppressing the recess of a silicon oxide film being buried in an element separation groove. SOLUTION: At the lower part of a silicon nitride film 3 that becomes a mask when a substrate 1 of an element separation region is etched for forming a groove 5a, an amorphous silicon film (buffer film) 16 is provided. When the silicon nitride film 3 and the amorphous silicon film 16 are eliminated after the element separation groove is formed, the surface of a silicon oxide film 7 being buried to the element separation groove is set higher by the amount of the film thickness of the silicon nitride film 3 and the amorphous silicon film 16, thus preventing the height of the surface from greatly retreating (being recessed) downward as compared with the surface of the substrate 1 of an active region even when the silicon oxide film 7 is etched in a subsequent wet etching process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly to a fine MISFET (metal
Insulator Semiconductor Field Effect Transistor)
The present invention relates to a technique which is effective when applied to an element isolation groove forming process for realizing the above.

[0002]

2. Description of the Related Art As an element isolation technique in an LSI manufacturing process, a selective oxidation (Local Oxidization of Silicon;
Although the LOCOS method has been widely used, a new element isolation technique has been introduced with miniaturization of semiconductor elements.

An element isolation groove in which an insulating film such as a silicon oxide film is buried in a groove formed in a semiconductor substrate has the following characteristics.
(B) easy control of the element isolation film thickness and easy setting of the field reversal voltage; (c) separate impurities between the side wall and the bottom inside the trench By separating the inversion prevention layer from the diffusion layer and the channel region, it is superior to the selective oxidation method, such as ensuring sub-threshold characteristics, reducing junction leakage, and reducing the back gate effect. ing.

[0004] A general method of forming the above-mentioned element isolation groove is as follows. First, a semiconductor substrate (hereinafter simply referred to as a substrate) is thermally oxidized to form a thin silicon oxide film called a pad oxide film on the surface thereof, and a CVD (C
After depositing a silicon nitride film by a chemical vapor deposition method, the silicon nitride film in the element isolation region is removed by dry etching using a photoresist film as a mask. Next, the photoresist film is removed, and the substrate is subjected to dry etching using a silicon nitride film as a mask.
After forming a groove having a depth of about 00 nm, the substrate is thermally oxidized to form a thin silicon oxide film on the inner wall of the groove. This silicon oxide film is formed for the purpose of removing the etching damage generated on the inner wall of the groove and alleviating the stress of the silicon oxide film embedded in the groove in a later step.

Next, after depositing a thick silicon oxide film on the substrate including the inside of the groove by the CVD method, the substrate is heat-treated, and the silicon oxide film embedded in the inside of the groove is densified by densification. Subsequently, Chemical Mechanical Polishing (Chemical Me
By removing the silicon oxide film on the silicon nitride film using the (Chemical Polishing; CMP) method and leaving the silicon oxide film only inside the trench, the unnecessary silicon nitride film is removed by etching. The element isolation groove is completed.

In the above-described device isolation structure, the gate oxide film formed on the substrate surface in the active region is locally thinned at the end (shoulder) of the active region, and the gate voltage is applied to the shoulder. It is known that as a result of the concentration of an electric field, a phenomenon (called a kink characteristic or a hump characteristic) in which a drain current flows even at a low gate voltage occurs. A technique for attaching a tag has been proposed.

For example, JP-A-63-2371 discloses that
When a fine MISFET having a channel width of 1 μm or less is formed in the active region of the substrate surrounded by the above-described element isolation trench, a so-called narrow channel effect in which the threshold voltage (Vth) lowers becomes apparent, Point out the problem of becoming unusable. This is an element isolation structure in which a groove is formed in the substrate and an insulating film is embedded in the groove.
This is because the shoulder of the active region has a sharp cross-sectional shape close to a right angle, so that the electric field of the gate voltage concentrates in this region, and a channel is formed even at a low gate voltage.

[0008] Japanese Patent Application Laid-Open No. 2-260660 also discloses
In order to prevent the above-described kink (hump) characteristic from occurring, a technique is disclosed in which a shoulder of an active region is rounded to suppress a problem that a gate voltage electric field is concentrated in this region.

[0009]

The method of forming the element isolation trench and the method of forming the MISFET studied by the present inventor generally comprise the following steps (a) to (k).

(A) After a substrate is thermally oxidized to form a thin first silicon oxide film (pad oxide film) on its surface, a silicon nitride film is deposited thereon by a CVD method.

(B) The silicon nitride film in the element isolation region is removed by dry etching using the photoresist film as a mask, the photoresist film is removed, and then the element isolation region is removed by dry etching using the silicon nitride film as a mask. A groove is formed in the substrate.

(C) The substrate is thermally oxidized to form a thin second silicon oxide film on the inner wall of the groove. This second silicon oxide film is formed for the purpose of removing the etching damage generated on the inner wall of the groove and relieving the stress of the third silicon oxide film embedded in the groove in the next step. This heat treatment rounds the shoulder of the active region.

(D) After depositing a thick third silicon oxide film on the substrate including the inside of the groove by the CVD method, the substrate is subjected to a heat treatment to densely burn the third silicon oxide film embedded in the inside of the groove. Tighten (densify).

(E) The third silicon oxide film on the silicon nitride film is removed by chemical mechanical polishing, leaving the third silicon oxide film only inside the trench.

(F) By removing the silicon nitride film with hot phosphoric acid, an element isolation groove is completed. When the silicon nitride film is removed, the surface of the first silicon oxide film formed on the substrate surface in the active region defined by the element isolation groove and the surface of the third silicon oxide film embedded in the element isolation groove A step corresponding to the thickness of the silicon nitride film is generated therebetween.

(G) The substrate is thermally oxidized to form a thin fourth silicon oxide film (sacrificial oxide film) on the substrate surface in the active region. This fourth silicon oxide film is formed for the purpose of removing damage to the substrate surface in the active region generated during the formation of the isolation trench, preventing contamination of the substrate by ion implantation of impurities performed in the next step, and reducing damage.

(H) In order to form wells in the substrate, impurities are ion-implanted into the substrate through the fourth silicon oxide film. Further, in order to adjust the threshold voltage of the MISFET, impurities are ion-implanted into the substrate through the fourth silicon oxide film.

(I) heat-treating the substrate to form a well;
Subsequently, after the fourth silicon oxide film on the surface of the substrate is removed by wet etching, the substrate is thermally oxidized,
A clean gate oxide film is formed on the substrate surface in the active region.

(J) MISFET on top of gate oxide film
Is formed.

In the above-described process, when the remaining silicon nitride film becomes small due to a variation in chemical mechanical polishing or the like, the third silicon oxide film is formed in the wet etching before the formation of the fourth silicon oxide film in the step (h). However, since not only the upper surface but also the side surfaces are exposed to the etchant, the amount to be etched is larger than that of the third silicon oxide film in a region away from the active region. As a result, the surface of the third silicon oxide film recedes (recesses) downward in the element isolation trench near the shoulder of the active region, and the substrate surface at the shoulder of the active region is exposed.

In the above-mentioned process, in the step (i), after the fourth silicon oxide film on the surface of the substrate is removed by wet etching, the substrate is thermally oxidized, so that a clean gate is formed on the substrate surface in the active region. An oxide film is formed. Therefore, the recess (recess) of the third silicon oxide film generated in the step (h) further progresses by the wet etching.

As described above, when the (third) silicon oxide film buried in the element isolation trench is recessed (recessed) near the active region, the gate oxide film formed on the substrate surface at the shoulder of the active region is formed. End reaches a part of the side wall of the element isolation groove. However, since impurities for adjusting the threshold voltage of the MISFET are hard to be implanted into the sidewalls of the element isolation trench, the impurity concentration in this region is lower than the impurity concentration in the flat portion of the active region. As a result, when a voltage is applied to the gate electrode, a subchannel is formed on the shoulder of the active region before a channel is formed on the flat portion of the active region, so that the threshold voltage is reduced. . In particular, when the gate width is reduced along with the miniaturization of the MISFET, the influence of the sub-channel becomes remarkable, and the amount of decrease in the threshold voltage is increased. Such a phenomenon becomes a particularly serious problem in a surface channel type MISFET in which a gate electrode is formed of n-type polycrystalline silicon.

As a countermeasure to prevent the above-mentioned decrease in the threshold voltage, it is conceivable to increase the dose of the impurity to compensate for the decrease in the impurity concentration at the shoulder of the active region. However, in this method, since the impurity concentration of the substrate becomes high, for example, a dynamic random access memory (DRAM) is used.
In y), the electric field intensity in the vicinity of the semiconductor region of the storage node increases, which causes problems such as a decrease in refresh characteristics due to an increase in leak current and an increase in parasitic capacitance of the bit line.

An object of the present invention is to improve a process for forming an element isolation groove, thereby miniaturizing a MISFET.
It is an object of the present invention to provide a technique for improving the reliability and manufacturing yield of a semiconductor integrated circuit device having the above.

Another object of the present invention is to improve the process for forming the element isolation trench, thereby miniaturizing the DRAM.
To provide a technique for improving the refresh characteristics of the semiconductor device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0027]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

The method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.

(A) After forming a first silicon oxide film, a buffer film, and a silicon nitride film on the main surface of a semiconductor substrate, the silicon nitride film, the buffer film, the first silicon oxide film, Forming a groove in the semiconductor substrate in the element isolation region by sequentially etching the semiconductor substrate; (b) forming a second silicon oxide film on the semiconductor substrate including the inside of the groove; Forming an element isolation groove in the element isolation region by removing the second silicon oxide film outside the groove by a chemical mechanical polishing method and leaving the second silicon oxide film inside the groove; (c) After the removal of the silicon nitride film and the buffer film, the threshold voltage of the MISFET is adjusted on the main surface of the semiconductor substrate through the first silicon oxide film. A step of ion-implanting the impurity,
(D) after removing the first silicon oxide film by wet etching the main surface of the semiconductor substrate, forming a gate insulating film on the surface of the active region of the semiconductor substrate defined by the element isolation region; And (e) forming a gate electrode of the MISFET on the gate insulating film.

According to the above-described means, the buffer film is provided below the silicon nitride film used as a mask when the substrate in the element isolation region is etched to form the groove. When the silicon nitride film and the buffer film are removed, the surface of the second silicon oxide film buried in the isolation trench becomes higher by an amount corresponding to the thickness of the silicon nitride film and the buffer film. Therefore, even if the surface of the second silicon oxide film recedes in the subsequent wet etching step, the height of the surface does not largely recede (recess) below the surface of the substrate in the active region.

[0031]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) DR according to the present embodiment
A method for manufacturing an AM will be described with reference to FIGS. The left part of each figure shows a part of a DRAM memory array, and the right part shows part of a DRAM peripheral circuit.

First, as shown in FIG.
A substrate (wafer) 1 made of p-type single crystal silicon having a specific resistance of about Ωcm is thermally oxidized at about 850 ° C. to form a silicon oxide film (first silicon oxide film) 2 on its surface.
Subsequently, a film thickness of 20 nm is formed on the silicon oxide film 2 by the CVD method.
After an amorphous silicon film (buffer film) 16 is deposited on the amorphous silicon film 16, a CVD
A silicon nitride film 3 having a thickness of about 120 nm is deposited by the method.

The silicon oxide film 2 is formed to alleviate the stress generated at the interface between the substrate 1 and the silicon nitride film 3 and to prevent defects such as dislocations from occurring on the surface of the substrate 1 due to the stress. . In addition, the silicon oxide film 2
In order to reduce the amount of etching of the silicon oxide film in the element isolation trench during wet cleaning before forming a gate oxide film, which will be described later, the film thickness is made as small as possible (10 nm or less).
It is desirable to do. The silicon nitride film 3 is used as a mask when the substrate 1 in the element isolation region is etched to form a groove. Further, since the silicon nitride film 3 has a property of being hardly oxidized, it is also used as a mask for preventing the surface of the substrate 1 under the silicon nitride film 3 from being oxidized.

Next, as shown in FIG. 2, the silicon nitride film 3, the amorphous silicon film 16 and the silicon oxide film 2 in the element isolation region are selectively removed by dry etching using the photoresist film 4 as a mask. As shown in FIG. 3, a trench 5a having a depth of about 350 to 400 nm is formed in the substrate 1 in the element isolation region by dry etching using the silicon nitride film 3 as a mask. The groove 5a is formed by removing the silicon nitride film 3, the amorphous silicon film 16 and the silicon oxide film 2 in the element isolation region by dry etching using the photoresist film 4 as a mask, and subsequently using the photoresist film 4 as a mask. 1 may be formed by dry etching.

Next, as shown in FIG.
By performing thermal oxidation at 0 to 1100 ° C., a thin silicon oxide film 6 having a thickness of about 10 nm is formed on the inner wall of the groove 5a. The silicon oxide film 6 recovers the damage of the dry etching generated on the inner wall of the groove 5a and relieves the stress generated at the interface between the silicon oxide film 7 embedded in the groove 5a and the substrate 1 in a later step. To form. In addition, by performing this thermal oxidation treatment, the end portions (points indicated by arrows) of the amorphous silicon film 16 are oxidized, and the surface of the substrate 1 at the shoulder of the active region is rounded.

When the silicon oxide film 6 is formed thick,
When impurities for adjusting the threshold voltage are ion-implanted into the surface of the substrate in a later step, the dose of the impurity may be insufficient at the shoulder of the active region, which may cause a decrease in the effective channel width and a decrease in the threshold voltage. There is. Therefore, it is desirable that the film thickness is set to a degree necessary for rounding the shoulder of the active region (about 10 nm).

Next, as shown in FIG. 5, a silicon oxide film (second silicon oxide film) 7 is deposited on the substrate 1 including the inside of the groove 5a by the CVD method. The silicon oxide film 7 is deposited with a thickness (for example, about 450 to 500 nm) larger than the depth of the groove 5a, and the silicon oxide film 7 is buried in the groove 5a without gaps. The silicon oxide film 7 is formed by a film forming method with good step coverage, such as a silicon oxide film formed using oxygen and tetraethoxysilane ((C ₂ H ₅ ) ₄ Si).

Next, the substrate 1 is thermally oxidized at about 1000 ° C.
After performing a densify (sintering) process to improve the film quality of the silicon oxide film 7 embedded in the groove 5a, FIG.
As shown in FIG. 5, the grooves 5 are formed using a chemical mechanical polishing (CMP) method.
a, the silicon oxide film 7 outside the groove 5a is removed.
Is flattened on the surface of the silicon oxide film 7 on the top. This polishing is performed using the silicon nitride film 3 covering the surface of the substrate 1 in the active region as a stopper, and the time when the height of the surface of the silicon oxide film 7 becomes the same as that of the silicon nitride film 3 is defined as an end point. I do.

Next, the silicon nitride film 3 covering the active region of the substrate 1 is removed using an etching solution such as hot phosphoric acid.
Subsequently, the amorphous silicon film 16 under the amorphous silicon film 16 is removed by dry or wet etching.
As shown in FIG. 7, the element isolation trench 5 in which the silicon oxide film 7 is embedded is completed. As shown in the figure, when the silicon nitride film 3 and the amorphous silicon film 16 are removed, the surface of the silicon oxide film 2 remaining on the surface of the substrate 1 in the active region defined by the element isolation trench 5 and the element isolation trench 5 A step corresponding to the thickness of the silicon nitride film 3 and the amorphous silicon film 16 is generated between the surface of the buried silicon oxide film 7 and the surface of the buried silicon oxide film 7.

Next, as shown in FIG. 8, in order to form wells (p-type well 8 and n-type well 9) in the substrate 1, n-type impurities (for example, After phosphorus (ion) is ion-implanted and another part is ion-implanted with a p-type impurity (boron), a p-type impurity (boron) is ion-implanted into the substrate 1 in order to adjust the threshold voltage of the MISFET. Impurities for forming wells (p-type well 8 and n-type well 9) are introduced into a deep region of the substrate 1 with high energy, and impurities for adjusting a threshold voltage are formed on the substrate 1 with low energy. Introduce into shallow areas.

Next, as shown in FIG.
The impurity is extended and diffused by heat treatment at 0 ° C., thereby forming a p-type well 8 on the substrate 1 of the memory array and a p-type well 8 and an n-type well 9 on the substrate 1 of the peripheral circuit.

Next, as shown in FIG. 10, the silicon oxide film 2 remaining on the surface of the substrate 1 in the active region is removed by wet etching using hydrofluoric acid, and the surface of the substrate 1 is exposed. When this etching is performed, the surface of the silicon oxide film 7 buried in the element isolation trench 5 is also etched.
Its surface recedes downward. However, the silicon oxide film 7 at the time when the element isolation groove 5 is formed (the process shown in FIG. 7)
Is higher than the surface of the silicon oxide film 2 formed in the active region by an amount corresponding to the thickness of the silicon nitride film 3 and the amorphous silicon film 16. Also,
An oxide film formed by partially oxidizing the amorphous silicon film 16 in the thermal oxidation step shown in FIG. 4 remains at the end of the element isolation groove 5.

Therefore, the silicon oxide film 7 is removed by the wet etching for removing the silicon oxide film 2.
Does not recede (recess) largely below the surface of the substrate 1 in the active region. That is, as shown in FIG. 10, the surface of the substrate 1 in the active region after the removal of the silicon oxide film 2 is
Is almost the same height as the surface of the silicon oxide film 7 buried in the substrate.

Next, as shown in FIG.
After forming a clean gate oxide film 11 on the surface of the substrate 1 in the active region by thermal oxidation at 00 to 850 ° C.,
As shown in FIG. 12, gate electrodes 12A (word lines WL), 12B, and 12C are formed on the gate oxide film 11. The gate electrodes 12A (word lines WL), 12B,
12C, for example, a polycrystalline silicon film doped with phosphorus is deposited on the gate oxide film 11 by a CVD method, and then a WN film and a W film are deposited thereon by a sputtering method, and further nitrided by a CVD method on the top thereof. After the silicon film 13 is deposited, it is formed by patterning these films by etching using a photoresist film (not shown) as a mask.

Next, as shown in FIG.
Is implanted with an n-type impurity (phosphorous or arsenic) to form the source and drain of the memory cell selecting MISFET Qs in the p-type well 8 of the memory array.
^- -type semiconductor region 14 is formed, the peripheral circuit p-type well 8
Then, an n ⁻ type semiconductor region 14 is formed. Further, a p ^- type semiconductor region 15 is formed by ion-implanting a p-type impurity (boron) into the n-type well 9 of the peripheral circuit. By the steps up to this point, the memory cell selecting MI of the DRAM is performed.
The SFET Qs is substantially completed.

(Embodiment 2) FIG. 14 shows a step of removing the silicon oxide film 7 outside the groove 5a by using a chemical mechanical polishing method and flattening the surface of the silicon oxide film 7 above the groove 5a. Is shown. The steps so far are the same as the steps shown in FIGS. 1 to 6 of the first embodiment.

Next, after removing the silicon nitride film 3 covering the active region of the substrate 1 using an etching solution such as hot phosphoric acid, the wells (p-type wells 8 and n-type wells) are formed in the substrate 1 as shown in FIG. In order to form the mold well 9), n-type impurity (for example, phosphorus) ions are implanted into a part of the substrate 1 through the amorphous silicon film 16 and the silicon oxide film 2, and p-type impurity (boron) ions are implanted into the other part. After injecting
In order to adjust the threshold voltage of the SFET,
Type impurity (boron) ions are implanted.

In the first embodiment, the ion implantation is performed after removing the silicon nitride film 3 covering the active region of the substrate 1 and the amorphous silicon film 16 thereunder. In some cases, when the amorphous silicon film 16 is removed, the silicon oxide film 2 is also removed, and the surface of the substrate 1 may be exposed.

According to the present embodiment, since the above-mentioned problems can be prevented, contamination and damage of the surface of the substrate 1 due to ion implantation can be reliably prevented.

The substrate 1 has wells (p wells 8, n wells).
After performing the ion implantation for forming the mold well 9), as shown in FIG.
Only the p-type impurity (boron) ions may be implanted into the substrate 1 through the silicon oxide film 2 in order to remove only the MISFET and adjust the threshold voltage of the MISFET. In this case, since impurities are implanted into substrate 1 through thin silicon oxide film 2, impurities for adjusting the threshold voltage can be introduced into a shallow region of substrate 1 with low energy.

Next, as shown in FIG.
The impurities are extended and diffused by heat treatment at 50 ° C., thereby forming a p-type well 8 on the substrate 1 of the memory array and a p-type well 8 and an n-type well 9 on the substrate 1 of the peripheral circuit. Subsequent steps are the same as in the first embodiment.

(Embodiment 3) In Embodiment 2,
As a countermeasure for surely preventing contamination and damage on the surface of the substrate 1, impurities are ion-implanted into the substrate 1 through the amorphous silicon film 16 and the silicon oxide film 2, but the following countermeasures are also possible.

First, as shown in FIG. 18, the silicon oxide film 7 outside the groove 5a is removed by using a chemical mechanical polishing method, and the surface of the silicon oxide film 7 above the groove 5a is planarized. As shown in FIG. 19, the silicon nitride film 3 covering the active region of the substrate 1 and the amorphous silicon film 16 thereunder are removed. The steps so far are the same as the steps shown in FIGS. 1 to 6 of the first embodiment.

Next, as shown in FIG.
A silicon oxide film 17 having a thickness of about 10 nm to 20 nm by a VD method.
Is deposited on the substrate 1 to form wells (p-type wells 8 and n-type wells 9) in the substrate 1 through the silicon oxide film 17 and the silicon oxide film 2 so that n-type impurity (for example, phosphorus) ions , And p-type impurity (boron) ions are implanted into other portions. Subsequently, p-type impurity (boron) ions are implanted into the substrate 1 for the MISFET. As in the second embodiment, the ion implantation of impurities for adjusting the threshold voltage may be performed after the silicon oxide film 17 is removed. Subsequent steps are the same as in the first and second embodiments.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

In the above embodiment, the case where the present invention is applied to a DRAM has been described. However, the present invention is not limited to this, and is widely applied to a semiconductor integrated circuit device in which a fine MISFET is formed on a substrate having element isolation grooves. Can be.

[0058]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the recess of the silicon oxide film buried in the isolation trench can be suppressed, so that the threshold voltage and the effective channel width of the miniaturized MISFET can be suppressed. can do. As a result, in the case of a DRAM, it is possible to realize an improvement in refresh characteristics by reducing a leak current.

Further, according to the present invention, the contamination and damage of the substrate surface due to the ion implantation can be reliably prevented, so that the reliability and the production yield of the semiconductor integrated circuit device can be improved.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a substrate, illustrating a method of manufacturing a semiconductor device according to Embodiment 1 of the present invention;

FIG. 2 is a fragmentary cross-sectional view of the substrate, illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the substrate, illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the substrate, illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the substrate, illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the substrate, illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the substrate, illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 8 is a cross-sectional view of a substantial part of the substrate, illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the substrate, illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the substrate, illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the substrate, illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the substrate, illustrating a method of manufacturing the semiconductor device according to Embodiment 1 of the present invention;

13 is a fragmentary cross-sectional view of the substrate, illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention; FIG.

FIG. 14 is a fragmentary cross-sectional view of the substrate, illustrating a method of manufacturing the semiconductor device according to the second embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the substrate, illustrating a method of manufacturing the semiconductor device according to the second embodiment of the present invention;

16 is a fragmentary cross-sectional view of a substrate, illustrating a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention; FIG.

FIG. 17 is a fragmentary cross-sectional view of the substrate, illustrating a method of manufacturing the semiconductor device according to Embodiment 2 of the present invention;

FIG. 18 is a fragmentary cross-sectional view of the substrate, illustrating a method of manufacturing the semiconductor device according to the third embodiment of the present invention;

FIG. 19 is a fragmentary cross-sectional view of the substrate, illustrating a method of manufacturing the semiconductor device according to Embodiment 3 of the present invention;

FIG. 20 is an essential part cross sectional view of the substrate for illustrating the method of manufacturing the semiconductor device according to Embodiment 3 of the present invention;

[Explanation of symbols]

Reference Signs List 1 wafer (substrate) 2 silicon oxide film 3 silicon nitride film 4 photoresist film 5 element isolation groove 5a groove 6 silicon oxide film 7 silicon oxide film 8 p-type well 9 n-type well 10 photoresist film 11 gate oxide film 12A to 12C Gate electrode 13 Silicon nitride film 14 n ^- type semiconductor region 15 p ^- type semiconductor region 16 amorphous silicon film (buffer film) 17 silicon oxide film Qs MISFET WL for memory cell selection word line

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Naotaka Hashimoto 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. (72) Yaichiro Miura 5, Josuihoncho 5 22-22-1, Hitachi Ultra-SII Systems Co., Ltd. (72) Inventor Koichiro Sakanishi 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Within the semiconductor group of Hitachi, Ltd. (72) Inventor Takayuki Kanda 3-16, Shinmachi, Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Shinichi Horibe 3-16-16 Shinmachi, Ome-shi, Tokyo, Japan 3 72) Inventor Hiroyuki Izoe 5-22-1, Josuihoncho, Kodaira-shi, Tokyo Hitachi, Ltd. F-Terms in Lee Systems (reference) PR22 PR36 PR43 PR44 PR45 PR46 PR53 PR54 PR55 PR56

Claims (8)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device comprising the steps of: (a) forming a first silicon oxide film, a buffer film, and a silicon nitride film on a main surface of a semiconductor substrate, Forming a groove in the semiconductor substrate in the element isolation region by sequentially etching the silicon nitride film, the buffer film, the first silicon oxide film, and the semiconductor substrate; and (b) including the inside of the groove. After forming a second silicon oxide film on the semiconductor substrate, removing the second silicon oxide film outside the groove by a chemical mechanical polishing method, leaving the second silicon oxide film inside the groove, Forming an element isolation groove in the element isolation region; and (c) removing the silicon nitride film and the buffer film, and then removing the semiconductor substrate through the first silicon oxide film. Ion-implanting an impurity for adjusting a threshold voltage of a MISFET into the main surface; (d) wet-etching the main surface of the semiconductor substrate to remove the first silicon oxide film; Forming a gate insulating film on the surface of the active region of the semiconductor substrate whose periphery is defined by a region; and (e) forming a gate electrode of a MISFET on the gate insulating film. 2. A method of manufacturing a semiconductor integrated circuit device including the following steps: (a) forming a first silicon oxide film, a buffer film, and a silicon nitride film on a main surface of a semiconductor substrate;
The silicon nitride film in the element isolation region, the buffer film,
Forming a groove in the semiconductor substrate in the element isolation region by sequentially etching the first silicon oxide film and the semiconductor substrate; and (b) forming a second silicon oxide on the semiconductor substrate including the inside of the groove. After forming the film, the second silicon oxide film outside the trench is removed by a chemical mechanical polishing method, and the second silicon oxide film is left inside the trench, so that the device isolation trench is formed in the device isolation region. (C) removing the silicon nitride film, ion-implanting an impurity for adjusting a threshold voltage of a MISFET into the main surface of the semiconductor substrate through the buffer film and the first silicon oxide film. The process of injecting,
(D) removing the buffer film, subsequently wet-etching the main surface of the semiconductor substrate to remove the first silicon oxide film, and then defining an active region of the semiconductor substrate whose periphery is defined by the element isolation region Forming a gate insulating film on the surface of the gate insulating film;
Forming a gate electrode of the SFET; 3. A method of manufacturing a semiconductor integrated circuit device including the following steps: (a) forming a first silicon oxide film, a buffer film, and a silicon nitride film on a main surface of a semiconductor substrate;
The silicon nitride film in the element isolation region, the buffer film,
Forming a groove in the semiconductor substrate in the element isolation region by sequentially etching the first silicon oxide film and the semiconductor substrate; and (b) forming a second silicon oxide on the semiconductor substrate including the inside of the groove. After forming the film, the second silicon oxide film outside the trench is removed by a chemical mechanical polishing method, and the second silicon oxide film is left inside the trench, so that the device isolation trench is formed in the device isolation region. (C) removing the silicon nitride film and the buffer film, forming a third silicon oxide film on the semiconductor substrate, and forming the third silicon oxide film through the third silicon oxide film and the first silicon oxide film. A step of ion-implanting an impurity for adjusting the threshold voltage of the MISFET into the main surface of the semiconductor substrate; and (d) removing the third silicon oxide film. After removal of the first oxide silicon film main surface of the semiconductor substrate by wet etching, forming a gate insulating film on the surface of the active region of the semiconductor substrate defined around by the isolation region,
(E) forming a gate electrode of the MISFET on the gate insulating film; 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said buffer film is made of amorphous silicon. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the semiconductor substrate is thermally oxidized after the step (a) and prior to the step (b). Forming a fourth silicon oxide film on the inner wall of the groove. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first silicon oxide film has a thickness of 10 nm or less. Manufacturing method. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said buffer film has a thickness of 20 nm or less. . 8. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said MISFE
T is a method of manufacturing a semiconductor integrated circuit device, wherein the method constitutes a DRAM memory cell.