JP2001077419A - Group iii nitride semiconductor light-emitting element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide low-resistance in as-grow state by forming a p-type stage electrode which makes contact with a second n-type group III nitride semiconductor layer which is vapor-phase grown, after completion of vapor-phase growth of a p-type group III nitride semiconductor layer laminated above a luminous layer, while peeping the growth temperature kept within a specified range. SOLUTION: After the completion of vapor-phase growth of a group III nitride semiconductor layer 105 where p-type impurity is doped, an n-type group III nitride semiconductor layer 106 is formed by vapor-phase growth in a temperature range of ±100 deg.C with respect to the film-forming temperature of the p-type impurity doped group III nitride semiconductor layer 105. With this constitution, the n-type group III nitride semiconductor layer 106 comprises hydrogen as a carrier gas, or captures hydrogen impurity coming into the p-type impurity doped group III nitride semiconductor layer 105. Thus, capability enabling a p-type impurity doped group III nitride semiconductor layer 105 to be p-type conductive layer of low resistance In an 'as-grow' state is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION As-grown as-grown
The present invention relates to a technique for forming a group III nitride semiconductor light emitting device having a high light emission intensity from a laminated structure having a junction structure that provides a low resistivity p-type group III nitride semiconductor layer in an as-grown state.

[0002]

2. Description of the Related Art A group III nitride semiconductor light emitting diode (LED) or laser diode (LD) has a laminated structure using a high resistance or insulating single crystal such as sapphire (α-Al ₂ O ₃ single crystal) as a substrate. It is composed of the body. The light emitting portion provided in the laminated structure has a pn junction type double hetero (DH) structure including a light emitting layer and p-type and n-type barrier (cladding) layers sandwiching the light emitting layer. For example, a pn junction type DH structure composed of a cladding layer made of p-type and n-type aluminum gallium nitride (Al _x Ga ₁ -xN: 0 ≦ X ≦ 1) and an indium group III nitride semiconductor layer Are known (J
pn. J. Appl. Phys. Vol. 34, Pa
rt 2, No. 10B (1995), L1332-L
1335). Emitting layer is conveniently gallium indium nitride having a bandgap at room temperature to emit short wavelength visible light such as blue band or green band from the ultraviolet band (Ga _X an In
_1-X N: 0 ≦ X ≦ 1) (see Japanese Patent Publication No. 55-3834).

A p-type light emitting portion having a pn junction type DH structure has a p-type structure.
Form and n-type group III nitride semiconductor crystal layers are usually formed by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), halogen (halogen).
The film is formed by a vapor deposition (VPE) method such as a hydride method or a hydride method. However, a group III nitride semiconductor vapor deposition layer to which a p-type impurity is added (doped) generally has a high resistance in an as-grown state. For this reason, a low-resistance p-type group III nitride semiconductor layer constituting a light emitting portion having a pn junction type DH structure is made of, for example, magnesium (element symbol: Mg) or zinc (element symbol: Zn) by MOCVD. Group II p
After the growth layer to which the impurity is added is vapor-phase-grown, an electron beam is irradiated in a vacuum environment to perform a post-treatment to reduce the resistance (Japanese Patent Publication No. 6-9258 and Japanese Patent No. 25003).
No. 19).

Further, a group III nitride semiconductor layer doped with Mg which has high resistance in an as-grown state is formed again by means of heat treatment at a temperature of 400 ° C. or higher (Japanese Patent No. 2836685). reference). In performing a heat treatment for electrically activating the p-type impurity to lower the resistance, Ga _x Al ₁ -xN (0 ≦ x) is formed on the surface of the group III nitride semiconductor layer doped with the p-type impurity. ≤
1), means for performing after forming a surface protective layer (cap layer) made of AlN, Si ₃ N ₄ , or SiO ₂ is also disclosed (Japanese Patent No. 2540791 and Japanese Patent No. 2790).
No. 235).

FIG. 7 shows an insulating sapphire substrate 301.
FIG. 10 is a schematic cross-sectional view of a laminated structure 60 </ b> A showing a configuration of a conventional group III nitride semiconductor LED 60. A conventional group III nitride semiconductor LED 60 having a light emitting portion 60B having a pn junction type DH structure has a p-type III in which a p-type impurity doped layer having a high resistance in an as-grown state is reduced in resistance by performing a heat treatment or the like. Group nitride semiconductor cladding layer 30
5, a p-type pedestal (pad) electrode 306 is provided. The planar shape of the p-type pedestal electrode 306 is generally circular, square, or polygonal (see, for example,
-209497). In addition, the p-type pedestal electrode 306 is mainly made of gold (element symbol: Au) or an alloy thereof (Japanese Patent Laid-Open No. 5-2 / 1993).
No. 9121).

In the LED 60 of the type in which light is emitted to the outside by transmitting the light through the p-type group III nitride semiconductor clad layer 305 provided on the light-emitting layer 304, the p-type pedestal is provided on substantially the entire surface of the layer 305. It is made to conduct to the electrode 306 so that the transparent p
Laying the ohmic thin-film electrode 307 is a conventional general technique (see Japanese Patent No. 2803742). In the structure that has been subjected to the heat treatment with the surface protective layer as described above, the protective layer is removed over the entire area after the heat treatment, so that the surface of the p-type group III nitride semiconductor layer is exposed. A p-type ohmic electrode is arranged (Japanese Patent No. 2540791 and Japanese Patent No. 27902).
No. 35). The p-type ohmic thin-film electrode 307 laid on the surface of the p-type group III nitride semiconductor layer 305 is made of nickel (element symbol: Ni) or the like (see JP-A-9-64337).

As shown in FIG. 7, when a p-type pedestal electrode 306 is arranged on a p-type group III nitride semiconductor layer such as a p-type clad layer 305, a light emitting portion is provided in a region immediately below the pedestal electrode 306. A conventional example in which a layer 309 exhibiting a current blocking function for preventing a short-circuit flow of an element driving current to 60B is provided (Japanese Patent Laid-Open No. Hei 8-25076).
No. 9). In the prior art, the current blocking functional layer 309 is made of insulating silicon dioxide (Si).
O _2), or are composed of silicon nitride (Si ₃ N ₄₎ (see Japanese Specification No. Hei 8-279643). By taking such measures, the device operating current can be diffused over a wide range via the p-type ohmic thin film electrode 307, and therefore, it is said that this is effective in obtaining a group III nitride semiconductor light emitting device with high light emission intensity.

On the other hand, if an explanation is given with reference to FIG.
The pedestal electrode 308 is generally provided as an n-type ohmic electrode in the n-type group III nitride semiconductor layer 303 located between the crystal substrate and the light emitting layer. For example, it is provided on a cladding layer 303 made of an n-type group III nitride semiconductor layer constituting the light emitting section 60B (for example, see Japanese Unexamined Patent Application Publication No.
-209493). n-type pedestal electrode 3
08 is composed of titanium (element symbol: Ti) or the like (see Japanese Patent Application Laid-Open No. 7-45867). Its shape is a circle, a square, a polygon or the like.
No. 17). Regions 306a, 308a for providing n-type pedestal electrode 308 and p-type pedestal electrode 306
Are generally different from each other in the plane shape and the plane area (see Japanese Patent Application Laid-Open No. 10-209497).

[0009]

A light-emitting portion having a pn junction type DH structure and a low-resistance p-type group III nitride semiconductor layer resulting in good ohmic contact are difficult to obtain in an as-grown state. As described above, the formation of the group III nitride semiconductor layer is complicated because a post-process such as heat treatment is required again after the vapor phase growth. In addition, since the means for lowering resistance by electron beam irradiation needs to irradiate an electron beam under a relatively low acceleration voltage of 3 kV (kV) to 30 kV (see Japanese Patent Publication No. 6-9258 and Japanese Patent No. 2500319). I) doped with a p-type impurity with a limited depth from the surface where the electron beam can penetrate and reach.
It has been pointed out that the p-type impurity cannot be uniformly activated in the depth direction of the group II nitride semiconductor layer (see Japanese Patent No. 2836685). That is, there is a disadvantage that it is difficult to obtain a low-resistance group III nitride semiconductor layer having a uniform resistivity in the depth direction from the layer surface.

As a means for preventing the element operating current from short-circuiting and intensively flowing from the p-type pedestal electrode into the light-emitting portion area immediately below, an insulating film is provided below the p-type pedestal electrode as described above. Laying measures have been taken. But p
In order to take measures for providing a functional layer for performing such a current blocking function on a low-resistance group III nitride semiconductor layer in the form of a p-type impurity, first, a p-type impurity-doped II
A post-process after the vapor phase growth for making the group I nitride semiconductor layer a low-resistance layer, and then, a processing step of applying an insulating film and leaving it only in a predetermined region directly below the p-type pedestal electrode. Needed. Therefore, according to the conventional method, a group III nitride semiconductor having a p-type group III nitride semiconductor layer having a low resistance enough to provide a p-type thin film electrode having good ohmic contact and having a current blocking function is provided. In order to obtain a light emitting element, it is necessary to go through complicated steps.

A post-process for lowering resistance, such as annealing, is performed.
No need, low resistance III in as-grown state
If a group III nitride semiconductor layer can be obtained, the pn junction type I
A group II nitride semiconductor light emitting device can be provided. p-type impurity
Of the resistance of the group III nitride semiconductor layer doped with
Small is dependent on the concentration of hydrogen impurities contained in the layer
You. Obtaining a p-type group III nitride semiconductor crystal layer with low resistance
One effective means for achieving this is to add a p-type impurity III
In growing the group III nitride semiconductor crystal layer by vapor phase growth,
Concentration of hydrogen (hydrogen atoms) entering the crystal layer from the environment
Is to be reduced in advance. Already aluminum phosphide
Mu-gallium-indium mixed crystal ((Al _XGa_1-X)_0.5
In_0.5P: half of a group III-V compound such as 0 ≦ X ≦ 1)
For the conductor crystal layer, zinc is doped by MOCVD.
Ping (Al_0.7Ga_0.3)_0.5In_0.5On the P layer, n
G-type or p-type gallium arsenide (GaAs) crystal layer
Laminated structure as a functional layer to prevent intrusion of
First, a p-type AlGaInP layer in a vapor phase growth process
Is known to suppress the intrusion of hydrogen into the air
(J. Crystal Growth., 118 (19
92), 425-429).

The present invention has been made by paying attention to a laminated structure for suppressing intrusion of hydrogen impurities into a p-type impurity-doped semiconductor layer in the above-mentioned prior art, and (1) p-type impurities are doped. Group III nitride semiconductor layer as-
It has a laminated structure that is convenient for forming a p-type group III nitride semiconductor layer having a low resistance in a grown state. In particular, (2) p-type I having a low resistance in an as-grown state
N-type II provided to provide a group II nitride semiconductor layer
A group III nitride semiconductor light emitting device having a high light emission output and having a function of preventing short-circuiting of an element operating current to a region directly below a p-type pedestal electrode, which is formed using a group I nitride semiconductor layer. It is intended to provide.

[0013]

Means for Solving the Problems The present inventors have made intensive studies to solve the above-mentioned problems, and as a result, have reached the present invention.
That is, the present invention relates to [1] n in contact with a first n-type group III nitride semiconductor layer disposed between an insulating single crystal substrate and a light emitting layer made of an indium-containing group III nitride semiconductor. P-type I having a pedestal electrode and stacked above the light emitting layer
After the vapor phase growth of the group II nitride semiconductor layer is completed, the growth temperature is set to ±
A III-nitride semiconductor light-emitting device having a p-type pedestal electrode in contact with a second n-type III-nitride semiconductor layer continuously grown in a vapor phase while maintaining the temperature within 100 ° C. The shape of the region where the n-type pedestal electrode of the group III nitride semiconductor layer is provided (the n-type pedestal electrode forming region) and the region where the p-type pedestal electrode of the second n-type group III nitride semiconductor layer is provided (the p-type pedestal electrode) Group III nitride semiconductor light emitting device, wherein the shape of the
[2] The group III nitride according to [1], wherein the ratio of the plane area of the p-type pedestal electrode formation region to the n-type pedestal electrode formation region is in the range of 0.7 to 1.4. [3] The object semiconductor light emitting device, [3], wherein the n-type pedestal electrode forming region and the p-type pedestal electrode forming region are arranged at positions facing each other with respect to the center point of the planar shape of the device. The group III nitride semiconductor light-emitting device according to [2],
[4] A second n-type III under the p-type pedestal electrode formation region
The group III nitride according to any one of [1] to [3], wherein a pn junction including a junction between the group III nitride semiconductor layer and the p-type group III nitride semiconductor layer is formed. [5] The resistivity of the first n-type group III nitride semiconductor layer and the second n-type group III nitride semiconductor layer is 5 × 10 ^-4 to 1 × 10 ^-2 Ω · cm. I according to any one of [1] to [4], wherein
Group II nitride semiconductor light emitting device, [6] First n-type III
The group III nitride semiconductor light emitting device according to [5], wherein the group III nitride semiconductor layer and the second n-type group III nitride semiconductor layer are made of n-type gallium nitride doped with silicon. [7] The element, [7], wherein the light emitting layer is made of a group III nitride semiconductor having a multiphase structure composed of a plurality of phases having different indium composition ratios.
The group III nitride semiconductor light-emitting device according to any one of the above,
About.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a group III nitride as a starting material for obtaining a group III nitride semiconductor LED according to a first embodiment of the present invention. FIG. 3 is a schematic cross-sectional view showing a configuration of a laminated structure 10A including a semiconductor layer. The laminated structure 10A according to the first embodiment is formed by using a high-resistance or insulating single crystal, such as sapphire or zinc oxide (ZnO), as a substrate 101, for example.
It can be formed by stacking group III nitride semiconductor layers by OCVD vapor deposition. On the substrate 101, for example, aluminum gallium nitride (Al _x Ga _{1 -x} N: 0 ≦ X ≦ 1)
Buffer layer 102 made of, for example, n-type Al _x Ga ₁ -xN
N-type lower cladding layer 103 made of (0 ≦ X ≦ 1), gallium indium nitride (Ga _X In _1-X N: 0 ≦ X ≦
1), an upper cladding layer 105 made of, for example, Al _x Ga ₁ -xN (0 ≦ X ≦ 1) doped with a p-type impurity, and an n-type III bonded to the same layer 105. The group nitride semiconductor layers 106 can be sequentially laminated. In this example, the light emitting unit 10B is an n-type III
It comprises an n-type lower cladding layer 103 made of a group nitride semiconductor, a light emitting layer 104, and an upper cladding layer 105 made of a group III nitride semiconductor layer doped with a p-type impurity.

The first embodiment has a feature of the lamination structure in that it is bonded to a group III nitride semiconductor layer doped with a p-type impurity (FIG. 1, reference numeral 105) to form an n-type II.
That is, a group I nitride semiconductor layer (FIG. 1, FIG. 106) is provided. The general n-type group III nitride semiconductor layer contains hydrogen as a carrier gas or contains a fragment (decomposed product) containing a hydrogen-nitrogen bond due to thermal decomposition of a nitrogen supply source. Has an action of trapping hydrogen impurities entering the p-type impurity-doped group III nitride semiconductor layer. Therefore,
forming a p-type impurity-doped group III nitride semiconductor layer as-gr
It has the function of forming a low-resistance p-type conductive layer in the down state.

The action of trapping hydrogen impurities is as follows.
Group III nitride semiconductor layer, undoped (un
dope) III-nitride semiconductor layer, n-type impurity doped
It increases in the order of the group III nitride semiconductor layers that are doped.
Further, as described later, a p-type impurity-doped group III nitride
The group III nitride semiconductor layer bonded to the conductor layer is referred to as an n-type layer.
By doing so, a pn junction that can exhibit the current blocking function later
Can be formed. Therefore, in the present invention, the p-type impurity
III-nitride semiconductor layer to be bonded to the
It is made of a group III nitride semiconductor. n-type group III nitride half
The conductor layer is generally made of Al_XGa_YIn_ZN (0 ≦ X, Y, Z
.Ltoreq.1). In addition, nitrogen (element symbol: N)
Al containing outer Group V element (represented by symbol M)_XGa_YIn
_ZN_1-QM _Q(0 ≦ X, Y, Z ≦ 1, X + Y + Z = 1, 0
.Ltoreq.Q <1). These III-nitride halves
The conductor layer is formed by normal pressure (atmospheric pressure) or reduced pressure MOCVD.
Generally, ammonia (NH) is used in a hydrogen atmosphere._ThreeA)
Hydrazines etc.
Vapor growth can be used as a source. To capture hydrogen impurities
A suitable thickness of the n-type group III nitride semiconductor layer is approximately 50
Range of not less than nanometer (unit: nm) and not more than 1.5 μm
It is. The layer thickness can be adjusted by controlling the film formation time.

The n-type group III nitride semiconductor layer for providing an as-grown and low-resistance p-type group III nitride semiconductor layer is formed after the vapor-phase growth of the p-type impurity-doped group III nitride semiconductor layer is completed. Then, vapor phase growth is continued at substantially the same temperature as the film forming temperature of the same layer. A p-type impurity-doped group III nitride semiconductor layer is vapor-phase grown and temporarily
After cooling to a temperature of 00 ° C. or lower, n-type III
When the group III nitride semiconductor layer is covered, as-grown
Therefore, it is difficult to obtain a low-resistance p-type group III nitride semiconductor layer. This is because more hydrogen impurities are taken in during the cooling process in the atmosphere where the hydrogen impurities remain, and the hydrogen impurities remain in the layer. Therefore, after the vapor phase growth of the group III nitride semiconductor layer doped with the p-type impurity is completed, the n-type group III nitride semiconductor layer is cut off at substantially the same temperature without changing the film formation temperature. It is important to continue vapor phase growth. The substantially same temperature is within a temperature range of ± 100 ° C. based on the film forming temperature of the p-type impurity-doped group III nitride semiconductor layer. For example, MO
After growing a gallium nitride (GaN) layer doped with magnesium at 1050 ° C. by the CVD method,
An example in which a silicon (element symbol: Si) -doped GaN layer is grown in the same vapor phase growth system without changing the film formation temperature, that is, at 1050 ° C.

FIG. 2 shows one I according to the first embodiment.
FIG. 1 is a schematic plan view of a group II nitride semiconductor LED 10. In the LED 10 according to the present invention, the n-type pedestal electrode 107 is, for example, on the surface of the n-type lower cladding layer 103 laminated via the low-temperature buffer layer 102 on the sapphire substrate 101.
It is provided so as to occupy a part of the region 107a where the n-type pedestal electrode 107 is formed. On the other hand, the p-type pedestal electrode 108 is
It is provided in part of the region 108a over the group III nitride semiconductor layer 106. In the LED according to the first embodiment, n
First n-type III for laying the base electrode 107
Plane shape of surface region 107a of group nitride semiconductor layer 103 and region 108 for laying p-type pedestal electrode 108
The feature is that the planar shape of a is made similar to that of FIG. A planar shape 107a in a region where the pedestal electrodes 107 and 108 are laid,
If the shape of 108a is substantially similar, the open light emitting surface 104a exposed to the outside other than the region where the p-type pedestal electrode 108 is provided can be formed in a substantially symmetrical plane shape.
As a result, the light emission pattern emitted from the envelope of the light emitting element exhibiting the light condensing effect is made to have a substantially symmetrical shape, and the light emission intensity is balanced in the emission direction.
A group II nitride semiconductor light emitting device can be provided.

Referring to FIG. 2, as described in the second embodiment according to the second aspect of the present invention,
In addition to making the planar shape substantially similar to the n-type pedestal electrode forming region 107a and the p-type pedestal electrode forming region 108a, if the plane area is substantially the same, the open light emitting surface 104a is further improved.
Can be made to be symmetrical in the plane shape. Substantially similar shape means that the prototype of the pedestal electrode has a substantially similar relationship. As an example, it is assumed that even if the shape of a part of the peripheral edge is different, it is substantially similar if the main body is the same shape. If a specific example is shown, as shown in FIG.
Although the main bodies of the bases 7 and 108 are also square, even if one corner of the n-type base electrode 108 is cut off, both base electrodes 107 and 108 are regarded as having substantially similar shapes. In order to form a pedestal electrode having a substantially similar shape, patterning may be performed to provide a pedestal electrode having a substantially similar shape in the first place.
In addition, that the plane area is substantially the same means that the ratio of the plane area of the p-type pedestal electrode formation region to the n-type pedestal electrode formation region is preferably in the range of 0.7 to 1.4, and more preferably 0.8.
１．２1.2. It is almost similar,
If the pedestal electrode is patterned so as to give substantially the same plane area, a group III nitride semiconductor light emitting device having the pedestal electrode according to the second embodiment can be configured. The patterning can be performed using a general photolithography (photolithography) technique.

Further, a third aspect according to the third aspect of the present invention.
In the group III nitride semiconductor LED described in the embodiment, the n-type pedestal electrode forming region and the p-type pedestal electrode forming region are arranged at positions facing each other with respect to the center point of the planar shape of the individual element. . FIG. 3 is a schematic plan view of one group III nitride semiconductor LED 30 according to the third embodiment. The n-type and p-type pedestal electrodes 107 and 108 are arranged at positions opposing each other with respect to a center point C of a planar shape of an individual element, a so-called chip. When the pedestal electrodes 107 and 108 are arranged with respect to the center point C, the pedestal electrodes are installed adjacent to each other irrespective of the relative positional relationship with the center point C (see Japanese Patent Laid-Open No. 10-209497).
And the distance between the pedestal electrodes 107 and 108 can be further increased. Therefore, it is possible to suppress the short-circuiting flow of the element operating current between the pedestal electrodes which is likely to occur between the pedestal electrodes arranged at a short distance. Therefore, the element operating current can be distributed over a wider area of the light emitting surface, so that the region where the element operating current is diffused is expanded, which is effective in expanding the light emitting surface.

The group III nitride semiconductor light emitting device according to the fourth embodiment has a structure in which the second
Is characterized in that a pn junction consisting of a junction between the n-type group III nitride semiconductor layer and the group III nitride semiconductor layer doped with p-type impurities is formed. In particular, in the present invention, the second n-type group III nitride semiconductor layer according to the present invention, which is formed by vapor-phase growth following the p-type impurity-doped group III nitride semiconductor layer to constitute the pn junction It is characterized by using. FIG. 4 is a schematic cross-sectional view of a group III nitride semiconductor LED 40 illustrating the situation of the fourth embodiment. The p-type pedestal electrode 108 is formed from the second n-type III-nitride semiconductor layer 106 and the p-type III-nitride semiconductor layer 105 having low resistance as-grown by joining the same layer 106. Pn junction region 10
Place on 5a. P-type pedestal electrode 108 and light emitting layer 104
By arranging the pn junction region 105a in the middle of the above, the effect of preventing the element operating current supplied from the p-type pedestal electrode 108 from flowing short-circuiting to the light-emitting layer 104 immediately below it is exerted. You. That is, the pn junction region exerts a current blocking function in which the element operating current blocks the supply of current to a region where light emission is difficult to take out due to the laying of the p-type pedestal electrode, and the operating current is preferentially applied to the open light emitting surface. This is effective in distributing the data.

According to the conventional means, a pn junction can be formed directly below the p-type pedestal electrode. For example, following the prior art,
A group III nitride semiconductor layer doped with a p-type impurity such as magnesium is vapor-phase grown, cooled once to room temperature or the like, and then heat-treated at 400 ° C. or more again for lowering resistance,
Alternatively, it can also be formed by performing a vapor phase growth of an n-type group III nitride semiconductor layer again on the p-type group III nitride semiconductor layer that has been subjected to electron beam irradiation. However, the method based on this conventional means is complicated and the steps are redundant. On the other hand, if the p-type impurity-doped group III nitride semiconductor layer according to the present invention has a stacked structure in which the second n-type group III nitride semiconductor layer is joined, only one vapor phase growth is required, and In order to reduce the p-type resistance, a low resistance p-type group III nitride semiconductor layer can be obtained in an as-grown state without a post-process after vapor phase growth, and a current blocking function is achieved. There is the convenience that a pn junction can be formed together. In order to leave the second n-type group III nitride semiconductor layer only in the region where the p-type pedestal electrode is formed, an ordinary patterning technique and an etching technique such as plasma etching may be used.

Referring to FIG. 4, the p-type group III nitride semiconductor layer 1 is electrically connected to the p-type pedestal electrode 108 formed on the pn junction region 105a which performs a current blocking function.
When the ohmic metallic thin film 109 is laid on the surface of the light emitting layer 05, the operating current can be distributed to almost the entire surface of the light emitting layer 104 via the ohmic thin film electrode 109. A conventional technique of providing a light-transmitting thin-film electrode over substantially the entire surface of a heat-treated p-type group III compound semiconductor layer is also known (see Japanese Patent No. 2803742). However, in the present invention, an ohmic thin-film electrode is used. In order not to provide the entire surface only with the p-type group III nitride semiconductor layer, but to form the p-type group III nitride semiconductor layer 105 with low resistance as-grown only in the formation region 108a of the p-type pedestal electrode 108 It is provided on the remaining n-type group III nitride semiconductor layer 106. With such an arrangement different from the conventional one, the operation just below the p-type pedestal electrode, which could not be achieved by the conventional method of arranging an ohmic thin-film electrode on the surface of the p-type group III nitride semiconductor layer. This has the effect of preventing short-circuit flow of current.

The ohmic thin-film electrode 109 for electrically connecting the p-type pedestal electrode 108 in the pn junction region (p-type pedestal electrode formation region) 105a is made of well-known gold (Au),
It can be composed of silver (element symbol: Ag), nickel, palladium (element symbol: Pd), or the like. Further, it can be composed of an oxide of a transition metal such as nickel oxide (chemical formula: NiO). In the LED 40 (see FIG. 4) for extracting light emitted from the light-emitting layer 104 from the p-type group III nitride semiconductor layer 105 side, an ohmic thin-film electrode 109 provided on the layer generally has a light-transmitting property. Suitably, the layer thickness is less than about 20 nm. In order to achieve uniform ohmic contact with the p-type group III nitride semiconductor layer, about 5
A layer thickness of at least nm is required. Ohmic thin film 109
A window layer 110 made of a transparent oxide can be disposed thereon. When this window layer 110 is made of a conductive oxide, the transparent and conductive oxide window layer 110 is made of pn.
In a configuration in which the p-type pedestal electrode 108 is provided so as to be in electrical contact with the junction region 105a (see FIG. 4), an element operating current is supplied to almost the entire surface of the ohmic thin film electrode 109 via the window layer 110. It has an effect. Accordingly, the diffusion region of the operating current is expanded, and the high emission intensity I
A group II nitride semiconductor light emitting device is provided.

The pn junction formed by using the n-type group III nitride semiconductor layer provided in contact with the p-type impurity-doped group III nitride semiconductor layer is not limited to an LED, but may be an L-type junction.
It can also be used to construct D. In the LD, a group III nitride semiconductor LD including a current confinement layer is formed using a pn junction formed according to the present invention. In the LD, the region where the pn junction is arranged is opposite to the LED, for example, on the p-type group III nitride semiconductor layer other than the region immediately below the belt-like p-type electrode. This is an arrangement unique to an LD that requires a means for suppressing the current from flowing into other regions in order to effectively and efficiently flow the element operating current into the light emitting layer immediately below the p-type electrode.

It is desirable that the first and second n-type group III nitride semiconductor layers provided with the p-type and n-type pedestal electrodes are composed of low resistivity crystal layers. This is because the device operating current can be diffused in a wider range as the crystal layer is formed of a low resistivity crystal layer. In the fifth embodiment according to the fifth aspect of the present invention, both the p-type and n-type pedestal electrodes preferably have a resistivity of 1 × 10 ⁻² Ω · cm or less.
It is provided on the surface of the group III nitride semiconductor layer. 1x1
If it is an n-type group III nitride semiconductor layer having a resistivity greater than 0 ^-2 Ω · cm, it becomes difficult to provide an n-type pedestal electrode having excellent ohmic contact and diffusing current.
In addition, even with an undoped n-type group III nitride semiconductor layer having a high carrier concentration of 5 × 10 ⁻⁴ Ω · cm or less, the operating current can be diffused. However, in such an undoped high carrier concentration layer, a large amount of nitrogen vacancies as a donor component is present.
When such a low-resistivity crystal layer is used as the n-type group III nitride semiconductor layer, the lower layer of the p-type impurity-doped III
This is inconvenient because resistance reduction of the group III nitride semiconductor layer is hindered. On the other hand, a low resistivity n doped with an n-type impurity
In the group III nitride semiconductor layer, the resistivity is 5 × 10
^In order to obtain a crystal layer having a resistivity of ^-4 Ω · cm or less, generally, about 1
It is necessary to dope an n-type impurity ^exceeding × 10 ¹⁹ cm ⁻³ . However, the flatness of the surface of the n-type group III nitride semiconductor layer doped with an n-type impurity at a high concentration is impaired, which hinders stable obtaining of n-type and p-type pedestal electrodes having excellent contact properties. Come. For this reason, a group III nitride semiconductor light-emitting device having a reduced forward voltage for an LED and a reduced threshold voltage for an LD cannot be supplied stably.

The first and second resistances having the above-mentioned preferable resistivity are used.
Of the n-type group III nitride semiconductor layer is undoped.
ope). However, if the n-type impurity is doped, the n having the above-described preferable resistivity can be more stably formed.
A Group III nitride semiconductor layer is obtained. n-type dope III
The group III nitride semiconductor layer is made of n such as silicon, selenium (element symbol: Se) and sulfur (element symbol: S) during the vapor phase growth.
It can be formed by doping a shaped impurity. In particular, silicon
Compared with a group VI element such as selenium or tellurium (element symbol: Te), it is difficult to thermally diffuse in the group III nitride semiconductor layer. Therefore, in particular, when the silicon-doped n-type group III nitride semiconductor layer is joined to the p-type impurity-doped group III nitride semiconductor layer and subsequently stacked as the second group III nitride semiconductor layer, the dopant ( Diffusion and intrusion of silicon) into the p-type impurity-doped group III nitride semiconductor layer are suppressed. That is, when silicon is used as the n-type dopant, the degree of electrical compensation of the activated p-type impurity (acceptor) is reduced, and an as-grown, low-resistance p-type group III nitride semiconductor layer is obtained. It will be more convenient. In particular, in the sixth embodiment according to the sixth aspect of the present invention, silicon is doped with p-type impurities by silicon.
It is preferable that the n-type group III nitride semiconductor layer to be joined to and bonded to the group II nitride semiconductor layer is made of a silicon-doped group III nitride semiconductor.

In particular, an optimal embodiment of the sixth embodiment
Converts the first and second n-type group III nitride semiconductor layers to silicon.
It can be configured as doped gallium nitride (GaN). Al
_XGa_YIn_ZI represented by N (0 ≦ X, Y, Z ≦ 1)
In group II nitride semiconductors, GaN is easily converted to Si
Can be doped and has excellent controllability of doping concentration
Therefore, the first and second n-type IIs having a predetermined carrier concentration
There is an advantage that a group I nitride semiconductor layer can be stably obtained.
For use as a first n-type group III nitride semiconductor layer
Preferred carrier (electron) concentration of Si-doped GaN layer
Is 1 × 10¹⁷cm ^-31 × 10¹⁹cm^-3Below
You. In addition, the desirable range of the layer thickness is generally 0.5 μm or less.
5 μm or less. Second n-type group III nitride semiconductor
Of a Si-doped GaN layer preferred for use as a body layer
The range of the layer thickness is approximately 10 nm or more and 1.5 μm or less,
The carrier concentration range is 1 × 10¹⁶cm^-31 × 1
0¹⁹cm^-3It is as follows. The Si-doped GaN layer is made of GaN
During the vapor phase growth of silane (SiH_Four), Disilane (Si_Two
H₆) And Si as a doping source.
It can be formed by grouping. Si-doped GaN layer cap
The rear concentration is the amount of doping source supplied to the vapor phase growth reaction system.
The thickness can be adjusted by controlling the GaN deposition time.
Control.

According to a seventh embodiment of the present invention, there is provided a multi-phase structure comprising a plurality of phases having different indium (In) compositions.
-Phase), a second n-type group III nitride compound layer is joined to the p-type group III nitride semiconductor layer on the indium-containing group III nitride semiconductor light emitting layer.
Further, a first n-type group III nitride semiconductor layer is disposed below the light emitting layer, for example, as a lower cladding layer, to constitute a light emitting element. It has already been revealed by the present inventor that a light emitting layer having a multi-phase structure is superior in obtaining high-intensity light emission (US Pat. No. 5,8,8).
88, 369). Therefore, the light emitting layer is composed of an indium-containing group III nitride semiconductor layer having a multi-phase structure, and hydrogen impurities for forming an as-grown, low-resistance p-type group III nitride semiconductor layer in an emission direction in the light emission direction. With a configuration in which the second n-type group III nitride semiconductor layer serving as an intrusion prevention layer is crowned, a light-emitting layer providing high-intensity light emission;
A pn-junction-type light-emitting portion having a p-type group III nitride semiconductor layer having a low current resistance and excellent current diffusion properties as a barrier layer can be configured. Thereby, a group III nitride semiconductor light emitting device having high light emission intensity can be provided.

The multi-phase structure light emitting layer generally means a matrix phase which occupies a large part in volume.
And a dependent phase (sub) scattered as a microcrystal in the main phase.
-Phase). For example, in a GaInN crystal layer having a multiphase structure, the main phase usually has a smaller indium composition ratio than the subordinate phase. Therefore, the subject phase usually has a larger forbidden band width than the dependent phase. As an example, an indium concentration of about 5
% Of a Ga _0.95 In _0.05 N main phase and a dependent phase of Ga _0.85 In _0.15 N having an average indium concentration of 15%. Further, there is an example of a GaInN light emitting layer having a multi-phase structure in which GaN is a main phase and a microcrystalline body of Ga _0.90 In _0.10 N having an average indium composition ratio of 10% is a dependent phase. Whether the indium composition has a multi-phase structure or not
For example, it can be known by examining the distribution of indium concentration inside the light emitting layer by a cross-sectional TEM technique using a transmission electron microscope (abbreviation: TEM).

The light emitting layer having a multi-phase structure is formed on the first n-type group III nitride semiconductor layer according to the present invention by, for example, about 70 nm.
Indium-containing II film formed in the range of 0 ° C to 950 ° C
A group I nitride semiconductor layer can be formed as a material. Ga _X I whose indium composition ratio (= 1−X) exceeds approximately 10%
In the case of n _1−X N (0 ≦ X <0.9), a region having a different indium composition may be generated in the crystal layer due to a difference in the degree of condensation or the like in the crystal layer at the time of film formation. The multi-phase structure can be surely formed by adjusting the heating rate or the cooling rate after the formation of the light emitting layer (see the above U.S. Pat.
S-5,888,369). In particular, according to the vapor phase growth technique utilizing the cyclopentadienyl In (C ₅ H ₅ In) as indium source, ammonia (NH a nitrogen source
₃ ) Since an extra complexation reaction in the gas phase with, for example, can be avoided (see Japanese Patent Publication No. H8-17160), a multiphase structure in which the existence density of the subcrystallite microcrystals is substantially uniform can be formed. .

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present embodiment, the present invention will be described as an example in which the LED 50 is formed from an epitaxial growth structure 50A comprising a group III nitride semiconductor layer laminated on a sapphire substrate. FIG. 5 is a schematic plan view of the LED 50 according to the present embodiment. FIG. 6 is a schematic sectional view taken along a broken line AA ′ shown in the schematic plan view of FIG.

The laminated structure 50A for the LED 50 is:
(0001) sapphire single crystal substrate 501, GaN low temperature buffer layer 502, Si-doped n-type gallium nitride (GaN)
N-type cladding layer (first n-type II according to the present invention)
Group I nitride semiconductor layer) 503, main phase S is n-type Ga _0.95
In _0.05 N, the average indium composition ratio was 0.15
Gallium nitride-indium mixed crystal (Ga _0.85 In
N-type light-emitting layer 50 having a multiphase structure with _0.15 N) as the dependent phase T
4, the magnesium-doped Al _X Ga _{1 over X} N _(X = 0.15
To 0) cladding layer 505 composed of a composition gradient layer and S
i-doped n-type GaN layer (second n-type III according to the present invention)
(Group III nitride semiconductor layer) 506 (see FIG. 6).

Group III nitride compound semiconductor layers 502 to 506
Is trimethylgallium ((CH ₃ ) ₃ Ga) / trimethyl aluminum ((CH ₃ ) ₃ Al) / cyclopentadienyl indium (C ₅ H ₅ In) / ammonia (NH ₃ )
It was grown by the system normal pressure MO-VPE method. As a silicon doping source, a disilane-hydrogen mixed gas containing disilane at a concentration of about 10 ppm by volume was used. Bis-cyclopentadienyl Mg is used as a doping source of magnesium.
Using _{(bis- (C 5 H 5)} 2 Mg). The polycrystalline buffer layer 502 was formed at 430 ° C. Light emitting layer 5 with multi-phase structure
04 was set to 890 ° C., and the other group III nitride semiconductor growth layers 503 and 505 to 506 were set to 103
0 ° C. The composition gradient layer 505 has an aluminum composition ratio (= X) at the junction interface with the light emitting layer 504 of 0.15, and Al _x Ga ₁ -xN (X = 0.1) where X = 0 at the surface layer.
5 to 0). The gradient of the Al composition was obtained by reducing the amount of trimethylaluminum added to the vapor phase growth system with the elapse of the film formation time.

After the completion of the formation of the p-type impurity-doped layer 505, the Si-doped n-type GaN layer 506 was grown “continuously” without changing the film formation temperature. After the Si-doped n-type GaN layer 506 was deposited by bonding to the p-type impurity-doped layer 505, the temperature was lowered to 800 ° C. at a rate of about 20 ° C./min in an ammonia gas flow. The temperature was lowered from 800 ° C. to a temperature near room temperature by natural cooling in a hydrogen atmosphere. By this temperature lowering operation, the dependent phase T constituting the light emitting layer 504 having the multi-phase structure is formed.
The indium composition, outer shape and size of the indium were made uniform.

The thickness (d) of the buffer layer 502 was about 17 nm. The n-type cladding layer 503 had d = 3.5 μm and the carrier concentration (n) = 2 × 10 ¹⁸ cm ⁻³ . Light emitting layer 5
04 has d = 0.12 μm and carrier concentration (n) = 8
× 10 ¹⁷ cm ^-3 . The p-type impurity doped layer 505 is d
= 0.25 μm. Among them, the Al composition ratio was 0.15
The thickness of the region made of Al _0.15 Ga _0.85 N, which was substantially constant, was about 0.05 μm. Further, the Al composition ratio of the surface layer portion is set to 0, that is, the layer thickness of the region made of GaN is about 0.1
μm. The doping amount of Mg in the same layer 505 is about 7
× 10 ¹⁸ cm ^-3 . Since the Si-doped n-type GaN layer 506 is provided on the p-type impurity-doped layer 505 in a joined state, the layer 505 has low resistance in an as-grown state, and its carrier concentration (p) is 4 × 10 ¹⁷ cm. It became ^-3 . The p-type impurity-doped layer 505, which became a low-resistance p-type layer and was used as the p-type upper cladding layer, had a hydrogen atom concentration of about 7 × 10 ¹⁷ cm ⁻³ . The layer thickness of the Si-doped n-type GaN layer 506 was 0.15 μm, and the carrier concentration was about 2 × 10 ¹⁸ cm ⁻³ .

After cooling to room temperature, formation of the laminated structure 50A was completed, and the structure was taken out of the MOCVD growth furnace. afterwards,
Except for a part of the outermost Si-doped n-type GaN layer 506, the p-type impurity-doped layer 505 is formed by a general patterning technique (photo etching) and plasma etching means.
Removed from the surface. As shown in FIG. 5, the Si-doped n-type GaN layer 5 is formed only in a region 509a of a square individual element (chip) where a square p-type pedestal electrode 509 is to be formed.
06 was left on the p-type impurity-doped layer 505. Thus, the region 509a where the p-type pedestal electrode 509 is to be formed is formed.
A pn junction 505a was formed at the lower part of the surface. Si-doped n-type Ga remaining on p-type pure doped layer 505
The planar shape of the region of the N layer 506 was a square having a side similar to the bottom shape of the p-type pedestal electrode 509 and having one side of about 130 μm. The plane area of the p-type pedestal electrode formation region 509a is:
It was set to 7 × 10 ⁻⁴ cm ² .

Next, a general electron beam (beam) evaporation is performed on the surface of the Si-doped n-type GaN layer 506 and the surface of the p-type impurity-doped layer 505 which are left only in the region where the p-type pedestal electrode 509 is to be formed. Nickel oxide thin film 50
7 was deposited at about 250 ° C. Nickel oxide thin film 507
Was about 13 nm. The transmittance of blue light of a wavelength of 450 nm of a nickel oxide film (thickness = 13 nm) separately formed on a glass substrate under the same conditions was about 84%. On the NiO thin film 507, a transparent and n-type conductive layer is formed by a general high frequency sputtering method.
A TO film 508 was applied to substantially the entire surface of the NiO thin film 507. The pressure during sputtering of the ITO film is about 1 × 10 ^-3
The applied high frequency power is about 15
0 W. The thickness of the ITO layer 508 was about 0.3 μm. The resistivity of the film 508 was about 8 × 10 ⁻⁴ Ω · cm. From the above NiO thin film 507 and ITO film 508, p
An ohmic electrode 510 was formed.

A p-type pedestal electrode 509 is provided on a portion of the p-type pedestal electrode forming region 509a where the Si-doped n-type GaN layer 506 is left and the p-type impurity-doped layer 505 and the pn junction 505a are formed. Was. p-type pedestal electrode 509
Is approximately one side similar to the above pn junction region 505c.
It was a 10 μm square. IT of p-type pedestal electrode 509
The lower part 509-1 in contact with the O layer 508 was made of titanium, and the upper part 509-2 was made of gold. The thickness of the lower Ti film 509-1 was about 250 nm. The thickness of the upper Au film 509-2 was about 1.0 μm. The n-type pedestal electrode 511 also serving as the n-type ohmic electrode is formed by forming the Si-doped n-type GaN layer 506, the p-type impurity doped layer 505, and the light emitting layer 504 having a multiphase structure in the region 511a to be formed with argon (Ar) The n-type cladding layer 503 was removed and exposed on the surface of the n-type cladding layer 503 by plasma etching using a mixed gas of methane / methane (CH ₄ ) / hydrogen (H ₂ ). The pedestal electrode forming region 511a for laying the n-type pedestal (ohmic) electrode 511 was a square region having a side of 130 μm (flat area: about 1.7 × 10 ⁻⁴ cm ² ). The n-type pedestal electrode 511 was made of aluminum (Al) and had a layer thickness of about 1.2 μm. The planar shape of the n-type pedestal (n-type ohmic) electrode 511 was a square having a long side of about 110 μm. P-type and n-type pedestal electrode formation regions 509a and 511a, and p-type and n-type pedestal electrodes 50
Reference numerals 9 and 511 are arranged at positions facing each other with the center point C of the LED chip interposed therebetween. With this arrangement, the distance between the p-type and n-type pedestal electrodes 509 and 511 is maximized, and the p-type and n-type electrode formation regions 509a and 51 are formed.
Except for 1a, the planar shape of the light emitting surface 504a opened to the outside is bilaterally symmetric with respect to a diagonal line BB 'passing through the chip center point C.

Next, each LED 50 was divided into chips each having a length of about 350 μm. p
2 in the forward direction via the n-type and n-type pedestal electrodes 509 and 511
When a current of 0 milliamperes (mA) flows, the open light-emitting surface 5 around the outer periphery of the p-type pedestal electrode formation region 509a is formed.
Blue light was emitted from substantially the entire surface of 04a with substantially uniform intensity. The emission wavelength measured by the spectrometer is about 46
It was 0 nm. The half width of the emission spectrum is about 30 nm
It became. In light emission, the forward voltage (Ｖ20 mA) was 3.2 volts (V) on average, and the forward voltage between chips was stable and uniform at 3.2 ± 0.1 V. The light emission intensity in the chip state reached about 20 microwatts (μW), and a high-output group III nitride semiconductor LED was provided. In addition, in an LED lamp sealed with a general epoxy resin having a microlens for condensing light on the head, the angle distribution of the luminous intensity of the LED lamp (edited by Seiji Aoki, “Light Emitting Diode” (Industry Research Inc.) Society, first edition published on September 10, 1977), pages 64 to 69).

[0041]

According to the present invention, after the vapor phase growth of a group III nitride semiconductor layer doped with a p-type impurity is completed, a post-process such as a heat treatment is required to reduce the resistance. Since the p-type group III nitride semiconductor layer having low resistance in the as-grown state is avoided by avoiding the complexity, the group III nitride semiconductor light emitting device can be easily configured. Furthermore,
Unlike the related art, there is no need to newly apply an insulating layer or the like as a current blocking layer, and a current blocking region can be formed by forming a pn junction. Therefore, a group III nitride semiconductor light emitting device with high light emission output can be provided.

In particular, according to the invention as set forth in claim 1 of the present invention, in the group III nitride semiconductor light emitting device, both the p-type and n-type pedestal electrodes are n-type group III nitride semiconductor layers. For providing an n-type pedestal electrode on the surface of
The planar shape of the first n-type group III nitride semiconductor layer surface region (n-type pedestal electrode forming region) and the second n-type group III nitride semiconductor layer surface region (p
Since the flat area of the base electrode forming area) is similar to the flat area, it is possible to provide a group III nitride semiconductor LED excellent in the symmetry of the angular distribution of the light emission output.

According to the second aspect of the present invention, the plane area of the n-type pedestal electrode forming region is substantially the same as the plane area of the p-type pedestal electrode forming region. A group III nitride semiconductor LED having excellent distribution symmetry can be provided.

In particular, according to the third aspect of the present invention, the n-type pedestal electrode forming region and the p-type pedestal electrode forming region are opposed to each other with respect to the center point of the planar shape of the individual element. Since the device operating current is short-circuited between the pedestal electrodes, the device operating current can be spread over a wide range of the light emitting surface, and the light emitting area is expanded. A group III nitride semiconductor LED can be provided.

According to a fourth aspect of the present invention, a p-type pedestal electrode is formed of a second n-type group III nitride semiconductor layer and a group III nitride doped with a p-type impurity. Since it is provided on the pn junction region formed by the junction with the semiconductor layer, it is possible to prevent the operation current from flowing to the so-called light-shielded region immediately below the p-type pedestal electrode, and the light emission opened to the outside. An operating current can be circulated to the surface in a friendly manner, so that a group III nitride semiconductor light emitting device having a high light output can be provided.

According to the fifth aspect of the present invention, the first and second n-type p-type and n-type pedestal electrodes are provided.
Since a group III nitride semiconductor layer having a defined resistivity is used as the group III nitride semiconductor layer, the n-type GaN doped with silicon is particularly preferably used according to the invention of claim 6. Since the n-type group III nitride semiconductor layer is formed, a low-resistance p-type group III nitride semiconductor layer can be obtained stably in an as-grown state,
As a result, a pn junction type light emitting portion is provided by using the light emitting device, so that a group III nitride semiconductor light emitting device having high light emission intensity is provided.

According to the invention of claim 7 of the present invention, the light emitting layer of the group III nitride semiconductor light emitting device has a multiphase structure of indium composed of a plurality of phases having different indium composition ratios (concentrations). Since the light emitting device is made of the contained group III nitride semiconductor, there is an effect that a group III nitride semiconductor light emitting device having high light emission output is provided.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a laminated structure according to first and second embodiments of the present invention.

FIG. 2 is a schematic plan view of a laminated structure according to first and second embodiments of the present invention.

FIG. 3 is a schematic plan view of an LED according to a third embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of an LED according to a fourth embodiment of the present invention.

FIG. 5 is a schematic plan view of the LED described in Example 1.

FIG. 6 is a schematic cross-sectional view of the LED shown in FIG. 5 along the broken line AA ′.

FIG. 7 is a schematic sectional view of a conventional group III nitride semiconductor LED.

[Explanation of symbols]

REFERENCE SIGNS LIST 10 LED according to the present invention 10A laminated structure 10B Light emitting unit 20 LED according to the present invention 30 LED related to the present invention 40 LED related to the present invention 50 LED related to the present invention 50A laminated structure 60 Conventional LED 60A Conventional LED application 60B pn junction type light emitting unit 101 high resistance crystal substrate 102 buffer layer 103 n-type lower cladding layer (first n-type group III nitride semiconductor layer) 104 light emitting layer 104a open light emitting area 105 upper cladding layer 106 2 n-type group III nitride semiconductor layer 107 n-type pedestal electrode 107 a n-type pedestal electrode forming region 108 p-type pedestal electrode 108 a p-type pedestal electrode forming region 109 p-type ohmic thin film electrode 301 sapphire substrate 302 buffer layer 303 n-type lower portion Cladding layer 304 Light emitting layer 305 P-type upper cladding layer 306 p-type pedestal electrode 306a p-type pedestal electrode formation region 307 p-type ohmic thin film electrode 308 n-type pedestal (ohmic) electrode 308a n-type pedestal electrode formation region 309 current blocking layer 501 sapphire substrate 502 GaN buffer layer 503 n-type GaN cladding layer 504 Multi-phase structure light emitting layer 504a Open light emitting surface 505 p-type impurity doped composition gradient layer 505a pn junction region 506 Si-doped n-type GaN layer 507 Nickel oxide (NiO) thin film 508 ITO film 509 p-type pedestal electrode 509a p-type pedestal electrode formation Area 509-1 Lower layer of p-type pedestal electrode 509-2 Upper layer of p-type pedestal electrode 510 p-type ohmic electrode 511 n-type pedestal (n-type ohmic) electrode 511a n-type pedestal electrode formation area C Plan shape of individual element (chip) center

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[Procedure amendment]

[Submission date] September 25, 2000 (2009.2)
5)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction contents]

Further, a third aspect according to the third aspect of the present invention.
In the group III nitride semiconductor LED described in the embodiment, the n-type pedestal electrode forming region and the p-type pedestal electrode forming region are arranged at positions facing each other with respect to the center point of the planar shape of the individual element. . FIG. 3 is a schematic plan view of one group III nitride semiconductor LED 30 according to the third embodiment. The n-type and p-type pedestal electrodes 107 and 108 are arranged at positions opposing each other with respect to a center point C of a planar shape of an individual element, a so-called chip. When the pedestal electrodes 107 and 108 are arranged with respect to the center point C, the pedestal electrodes are installed adjacent to each other irrespective of the relative positional relationship with the center point C (see Japanese Patent Laid-Open No. 10-209497).
Degree from publication reference herein), may be separated more the distance between the pad electrode 107 each other. Therefore, it is possible to suppress the short-circuiting flow of the element operating current between the pedestal electrodes which is likely to occur between the pedestal electrodes arranged at a short distance. Therefore,
Since the device operating current can be distributed over a wider area of the light emitting surface,
The region in which the element operating current is diffused is expanded, which is effective in expanding the light emitting surface.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0045

[Correction method] Change

[Correction contents]

According to a fourth aspect of the present invention, a p-type pedestal electrode is formed of a second n-type group III nitride semiconductor layer and a group III nitride doped with a p-type impurity. Since it is provided on the pn junction region formed by the junction with the semiconductor layer, it is possible to prevent the operation current from flowing to the so-called light-shielded region immediately below the p-type pedestal electrode, and the light emission opened to the outside. An operating current can be effectively passed to the surface, and therefore, a group III nitride semiconductor light emitting device having a high light emission output can be provided.

Continued on the front page F term (reference) 5F041 AA04 AA21 CA04 CA34 CA35 CA40 CA41 CA46 CA53 CA57 CA64 CA65 CA66 CA73 CA74 CA83 CA85 CA88 CA93 DA44 5F073 AA07 AA61 CA07 CA14 CB05 CB07 CB19 DA05 DA06 DA24 EA07 EA24

Claims (7)

[Claims] 1. Insulating single crystal substrate and indium-containing II
A light-emitting layer made of a group I nitride semiconductor,
After the vapor phase growth of the p-type group III nitride semiconductor layer having an n-type pedestal electrode in contact with the first n-type group III nitride semiconductor layer and stacked above the light emitting layer, the growth temperature is set to ± 100. A III-nitride semiconductor light-emitting device having a p-type pedestal electrode in contact with a second n-type III-nitride semiconductor layer which has been continuously grown in vapor phase while maintaining the temperature within 1 ° C.
A region (n) where an n-type pedestal electrode of a group II nitride semiconductor layer is provided.
Wherein the shape of the p-type pedestal electrode forming region) and the shape of the region of the second n-type group III nitride semiconductor layer where the p-type pedestal electrode is provided (p-type pedestal electrode forming region) are similar. Group III nitride semiconductor light emitting device. 2. The III according to claim 1, wherein the ratio of the plane area of the p-type pedestal electrode forming area to the n-type pedestal electrode forming area is in the range of 0.7 to 1.4. Group nitride semiconductor light emitting device. 3. The device according to claim 1, wherein the n-type pedestal electrode forming region and the p-type pedestal electrode forming region are arranged at positions facing each other with respect to the center point of the planar shape of the element. Group III nitride semiconductor light emitting device. 4. A pn junction formed of a junction between a second n-type group III nitride semiconductor layer and a p-type group III nitride semiconductor layer under a p-type pedestal electrode formation region. The group III nitride semiconductor light emitting device according to any one of claims 1 to 3, wherein 5. A first n-type group III nitride semiconductor layer and a second
Has a resistivity of 5 × 10 ⁻⁴
5. The group III nitride semiconductor light emitting device according to claim 1, wherein the range is within a range of 1 to 10 ⁻² Ω · cm. 6. 6. A first n-type group III nitride semiconductor layer and a second
The III-nitride semiconductor light-emitting device according to claim 5, wherein the n-type III-nitride semiconductor layer is made of n-type gallium nitride doped with silicon. 7. The light-emitting layer according to claim 1, wherein the light-emitting layer is made of a group III nitride semiconductor having a multiphase structure composed of a plurality of phases having different indium composition ratios.
Item 13. The group III nitride semiconductor light emitting device according to item 1.