經濟部智慧財產局員工消費合作社印製 4 6 6 7 8 3 A7 B7 五、發明說明（ί) 發明所屬之技術範圍 本發明係有關於爲了形成以氣相成長之原來生成態（a s -grown)狀態之低電阻率的p型ΙΠ族氮化物半導體層，而於P 型m於氮化物半導體層上層積η型m族氮化物半導體層’並 製作利用該η型m族氮化物半導體層之高發光強度的m族 氮化物半導體發元光件之技術。 習知技術 由m族氮化物半導體所形成的發光二極體（LED)或雷射 二極體（LD)等之m族氮化物半導體發光元件，從以前即以 層壓由主要以AlGalnN所表示之m族氮化物半導體所構成 之半導體層，於由藍寶石（sapphi re)( α -A 1 203單晶）等之 絕緣性單晶所形成之基板上所製作而成。具有習知之pn接 合型雙異質（DH)構造發光部分的m族氮化物半導體發光元 件，則以被設計爲直接接觸底座（pad)電極或p型歐姆 (Ohmic)電極於p型瓜族氮化物半導體層上構成。第3圖爲 展示由習知之Π族氮化物半導體所構成的LED構造的剖面 模型圖。於第3圖中，301爲藍寶石基板、302爲緩衝層、 3 0 3爲η型下方覆蓋層、304爲發光層，3 05爲p型上方覆 蓋層、306爲Ρ型底座電極、307爲透明的ρ型歐姆電極、 308爲η型底座電極、309爲電流阻止層，而由η型下方覆 蓋層303、發光層304、ρ型上方覆蓋層305構成ρη接合型 DH構造的發光部分。 具備有習知之ρη接合型DH構造的發光部分之LED，則於 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝---------訂---------線 4 6 6 78 3 經濟部智慧財產局員工消費合作社印製 A7 £7____五、發明説明（2_ ) P型上方覆蓋層305上設置p型底座電極306所構成。更於 第3圖中’於作爲p型]1族氮化物導體層的p型上方覆蓋層 3 0 5上形成p型底座電極3 0 6的情況下，爲了防止元件驅動 電流流入P型底座電極306之垂直區域，而展示形成電流阻 止層309於p型底座電極306之垂直區域的技術。根據習知 技術，完成該電流阻止的電流阻止層3 〇 9爲由絕緣性的二氧 化矽（S i 〇2)或氮化矽（s i 3N4)所構成。又，於該習知之LED 中，爲了傳導p型上方覆蓋層3〇5與1)型底座電極306，形 成透明的P型歐姆電極307。 [發明欲解決之課題] 於ΙΠ族氮化物半導體發光元件之pn接合型DH構造發光部 分所使用的低電阻之p型m族氮化物半導體層，以往難以在 生成態（a s - g r own )的狀態下得到，爲了低電阻化則必須於 氣相成長之後重新熱處理添加有p型雜質之m族氮化物半 導體層等，於形成低電阻之P型m族氮化物半導體層中則必 須要有繁雜的步驟。 又，爲了於P型m族氮化物半導體層上設置電流阻止層， 必須有首先爲了低電阻化添加p型雜質的m族氮化物半導 體層於氣相成長後所進行的熱處理步驟，以及之後於該層 上被覆絕緣膜’並殘存在限於p型底座電極之垂直區域的該 絕緣膜之加工步驟。爲了得到被賦予該等電流阻止機能的 瓜於氮化物半導體發光元件，必須歷經繁雜的步驟。 有鑑於上述之習知技術的缺點，本發b月的目的在（1 )建議 -4 - (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 4 6 6 78 3 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（J ) 形成適合於在生成態（a s - g r 〇 w η )的狀態下添加有p型雜質 的Κ族氮化物半導體層的m族氮化物半導體層之積層構造 ’（2)爲了在生成態（as-grown)的狀態下造成低電阻之p型 ΙΠ族氮化物半導體層，則利用層壓於p型m於氮化物半導體 層上的η型m族氮化物半導體層（以下稱爲第2個η型ΠΙ於 氮化物半導體層），來形成可防止元件驅動電流流入ρ型底 座電極之垂直區域的構造，而提供高發光功率之瓜族氮化 物半導體發光元件。 [解決課題之手段] 本發明者爲了達成上述目的之專一意努力的結果而達致 本發明。即，本發明係有關於： [1] m族氮化物半導體發光元件，其具備有絕緣性之單晶基 板，及層壓於該單晶基板上的第1個η型ΠΙ於氮化物半 導體層，及形成於該第1個η型m族氮化物半導體層表 面之一部份的第1個η型底座電極，及由包含銦元素的 瓜族氮化物半導體所構成的發光層、且該ΠΙ於氮化物層 壓於除去該第1個η型m族氮化物半導體層表面之形成 該第1個η型底座電極區域之區域上，及層壓於該發光 層上之Ρ型m族氮化物半導體層，及層壓於Ρ型m族氮 化物半導體層之第2個η型m族氮化物半導體層，及形 成於該第2個η型ΙΠ族氮化物半導體層之表面的第2個η 型底座電極； [2 ]如[1 ]所記載之瓜族氮化物半導體發光元件，但其特徵 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 經濟部智慧財產局員工消費合作社印製 466 78 3 at ___B7 _五、發明説明（4 ) 爲該第2個η型m族氮化物半導體層存在於該P型ΠΙ族 氮化物半導體層上之該第2個η型底座電極的投影區域 ， [3 ]如[2 ]所記載之ΙΠ族氮化物半導體發光元件’但其特徵 爲形成於該第1個η型m族氮化物半導體層表面之該第 1個η型底座電極的區域與形成於該第1個η型m族氮 化物半導體層表面之該第1個η型底座電極的區域爲相 似形； [4 ]如[2 ]所記載之m族氮化物半導體發光元件，但其中相 對於形成於該第1個η型ΠΙ族氮化物半導體層表面之該 第1個η型底座電極的區域面積，形成於該第2個η型 皿族氮化物半導體層表面之該第2個η型底座電極的區 域面積比例爲0 . 7以上同時1 . 4以下之範圍；. [5 ]如[3 ]所記載之m族氮化物半導體發光元件，但其中該 第1個η型底座電極及該第2個η型底座電極則形成於 相對於該ΙΠ族氮化物半導體發光元件之平面形狀中心 點的對稱位置； [6 ]如[2 ]所記載之m族氮化物半導體發光元件，其中形成 覆蓋有至少一部份之該P型m族氮化物半導體層及該 第2個η型瓜族氮化物半導體層之p型歐姆電極； [7]如[6]所記載之m族氮化物半導體發光元件，其中於該 第2個η型瓜族氮化物半導體層與P型m族氮化物半導 體層之接觸所形成之pn接合上形成該第2個η型底座 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） 經濟部智慧財產局員工消費合作社印製 6 7 8 3 4 6 6 783 A7 __ B7 發明説明（Γ) 電極； [8 ]如[7 ]所記載之m於氮化物半導體發光元件，但其中該p 型in族氮化物半導體層則由氮化鋁鎵銦（組成式爲Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 6 6 7 8 3 A7 B7 V. Description of the invention (ί) Technical scope of the invention The invention relates to the formation of the original as-grown state in order to grow in the gas phase. P-type III-nitride semiconductor layer with low resistivity in the state, and an n-type m-type nitride semiconductor layer is laminated on the p-type m-on-nitride semiconductor layer to produce the n-type m-type nitride semiconductor layer. Technology for m-nitride semiconductor light-emitting device with luminous intensity. Conventional technology M-nitride semiconductor light-emitting elements such as light-emitting diodes (LEDs) or laser diodes (LDs) formed from m-group nitride semiconductors have been laminated in the past and are mainly represented by AlGalnN A semiconductor layer composed of a group m nitride semiconductor is fabricated on a substrate formed of an insulating single crystal such as sapphire (α-A 1 203 single crystal). An m-group nitride semiconductor light-emitting device having a conventional pn-junction double hetero (DH) structure light-emitting portion is designed to directly contact a pad electrode or a p-type ohmic electrode to a p-type melon nitride. Structured on the semiconductor layer. Fig. 3 is a cross-sectional model diagram showing the structure of an LED composed of a conventional group III nitride semiconductor. In Figure 3, 301 is a sapphire substrate, 302 is a buffer layer, 303 is an n-type lower cover layer, 304 is a light-emitting layer, 305 is a p-type upper cover layer, 306 is a P-type base electrode, and 307 is transparent. The p-type ohmic electrode, 308 is an n-type base electrode, and 309 is a current blocking layer. The n-type lower cladding layer 303, the light-emitting layer 304, and the p-type upper cladding layer 305 constitute a light-emitting portion of the ρ-type junction DH structure. For LEDs with a light emitting part with a conventional ρη junction type DH structure, the Chinese national standard (CNS) A4 specification (210 X 297 mm) applies to this paper size (please read the precautions on the back before filling this page). --------- Order --------- Line 4 6 6 78 3 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 £ 7 ____ V. Description of the invention (2_) P-type top cover The layer 305 is configured by providing a p-type base electrode 306. In FIG. 3, when a p-type base electrode 3 0 6 is formed on the p-type upper cladding layer 3 0 5 which is a p-type] group 1 nitride conductor layer, in order to prevent the element drive current from flowing into the P-type base electrode 306 is a vertical region, and a technique for forming a current blocking layer 309 in a vertical region of the p-type base electrode 306 is shown. According to the conventional technology, the current blocking layer 309 which completes the current blocking is made of insulating silicon dioxide (Si02) or silicon nitride (Si3N4). Also, in this conventional LED, a transparent P-type ohmic electrode 307 is formed in order to conduct the p-type upper cover layer 305 and 1) -type base electrode 306. [Problems to be Solved by the Invention] A low-resistance p-type m-type nitride semiconductor layer used in a pn-junction type DH structure light-emitting portion of a group III-nitride semiconductor light-emitting element has conventionally been difficult to produce in the as-grown state. It is obtained in the state. In order to reduce the resistance, it is necessary to heat-treat the m-type nitride semiconductor layer added with a p-type impurity after the vapor phase growth, and it is necessary to have trouble in forming a low-resistance p-type m nitride semiconductor layer. A step of. In addition, in order to provide a current blocking layer on the P-type m-group nitride semiconductor layer, it is necessary to firstly perform a heat treatment step after vapor-phase growth of the m-type nitride semiconductor layer in which a p-type impurity is added in order to reduce resistance, and thereafter This layer is covered with an insulating film 'and a processing step of the insulating film limited to the vertical region of the p-type base electrode remains. In order to obtain a nitride semiconductor light-emitting device that is provided with such a current blocking function, complicated steps must be taken. In view of the shortcomings of the above-mentioned conventional technology, the purpose of this month is (1) Recommendation -4-(Please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 specifications ( 210X297 mm) 4 6 6 78 3 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (J) Form suitable for adding p-type impurities in the as-grown state (as-gr 〇w η) The layered structure of the m-type nitride semiconductor layer of the K-type nitride semiconductor layer is (2) In order to cause a low-resistance p-type group III nitride semiconductor layer in an as-grown state, lamination is used. An n-type m group nitride semiconductor layer on the p-type m on the nitride semiconductor layer (hereinafter referred to as the second n-type III on the nitride semiconductor layer) to form a vertical that can prevent the device drive current from flowing into the p-type base electrode The structure of the region provides a guar-nitride semiconductor light-emitting element with high luminous power. [Means for Solving the Problems] The present inventors have achieved the present invention as a result of a dedicated effort to achieve the above-mentioned object. That is, the present invention relates to: [1] a group m nitride semiconductor light-emitting device, which includes an insulating single crystal substrate, and a first n-type III semiconductor layer laminated on the single crystal substrate. And a first n-type base electrode formed on a part of the surface of the first n-type m-group nitride semiconductor layer, and a light-emitting layer composed of a cucurbit nitride semiconductor containing indium element, and ΠΙ The nitride is laminated on a region where the first n-type m-type nitride semiconductor layer is removed from the surface of the first n-type m-type nitride semiconductor layer, and the p-type m-type nitride is laminated on the light-emitting layer. A semiconductor layer, and a second n-type m-type nitride semiconductor layer laminated on the P-type m-type nitride semiconductor layer, and a second n-type formed on the surface of the second n-type I-III nitride semiconductor layer Type base electrode; [2] The guar nitride semiconductor light-emitting device as described in [1], but its characteristics (please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) Α4 specifications (210 × 297 mm) Consumption cooperation among employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed 466 78 3 at ___B7 _V. Description of the invention (4) It is the second n-type base electrode of the second n-type m-type nitride semiconductor layer on which the second n-type m-type nitride semiconductor layer exists. [3] The projection region, [3] The Ill-nitride semiconductor light-emitting element described in [2], but is characterized in that the first n-type base electrode is formed on the surface of the first n-type m-type nitride semiconductor layer. The area is similar to the area of the first n-type base electrode formed on the surface of the first n-type m-type nitride semiconductor layer; [4] the m-nitride semiconductor light-emitting device according to [2], However, the area of the first n-type base electrode formed on the surface of the first n-type III nitride semiconductor layer is the area of the first n-type base semiconductor formed on the surface of the second n-type nitride semiconductor layer. The area ratio of the two n-type base electrodes is in the range of 0.7 or more and 1.4 or less; [5] The m-type nitride semiconductor light-emitting device described in [3], but the first n-type base electrode The base electrode and the second n-type base electrode are formed with respect to the group III nitride semiconductor. [6] The m-group nitride semiconductor light-emitting element according to [2], wherein the P-type m-group nitride semiconductor layer and the first m-type nitride semiconductor light-emitting element described in [2] are formed. [N] p-type ohmic electrode of two n-type melon nitride semiconductor layers; [7] The m-group nitride semiconductor light-emitting device according to [6], wherein the second n-type melon nitride semiconductor layer and P The second n-type base is formed on the pn junction formed by the contact of the m-type group nitride semiconductor layer (please read the precautions on the back before filling this page) This paper size applies to the Chinese National Standard (CNS) Α4 specification (210X297 (Mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 6 7 8 3 4 6 6 783 A7 __ B7 Description of the Invention (Γ) Electrode; [8] m as described in [7] is for nitride semiconductor light-emitting devices, but The p-type in-group nitride semiconductor layer is composed of aluminum gallium indium nitride (composition formula is
AlxGaYInzN ’ 但是 OS 1、OS YS 1、〇$ 1 、χ+γ+ζ=ι)所形成，而該p型m族氮化物半導體層之電 阻率爲10Ω · cm以下； [9] 如[7]所記載之m於氮化物半導體發光元件，其中於第2 個η型瓜族氮化物半導體層中添加矽（Si)作爲雜質； [10] 如[9]所記載之m族氮化物半導體發光元件，但其中該 第2個n型m族氮化物半導體層則由氮化鋁鎵銦（組成 式爲 AlxGaYInzN ’ 但是 0 各 XS 1、0 彡 Yg 1、〇$ z S 1 ' X + Y + Z=l )所形成； [11] 如[7]所記載之m族氮化物半導體發光元件，但其中該 第1及第2個η型m族氮化物半導體層之電阻率在5X 1〇'4Ω · cm以上、IX 1(Γ2Ω · cm以下的範圍； [1 2 ]如[7 ]所記載之m於氮化物半導體發光元件，但其中第 2個η型ΠΙ於氮化物半導體層之載體（carrier)濃度値（ 單位：cnT3)與厚度値（單位：cm)的乘積在5X l〇1Qem-2以上、1 . 5 X 1 0l5cnT2以下之範圍： Π3]如[1]所記載之m族氮化物半導體發光元件，其中前述 發光層以由不同的銦組成比之多數相所構成之多相構 造的ΙΠ族氮化物半導體所形成； [1 4 ]如[1 ]所記載之瓜族氮化物半導體發光元件的製造方 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） H· nw mV i -—^1· m· —^ϋ ^n· n^i 0¾-9 ; . (請先閲讀背面之注意事項再填寫本頁) 466783 經濟部智慧財產局員工消费合作社印製 A7 B7 _五、發明説明（6 ) 法，其中以氣相成長法依序層壓該第1個η型ΠΙ族氮化 物半導體層、該發光層、該ρ型ΙΠ族氮化物半導體層、 該第2個η型ΠΙ族氮化物半導體層時，該第2個η型ΙΠ 族氮化物半導體層之成長溫度爲800 °C，同時該第2個 η型m族氮化物半導體層之成長溫度爲相對於該ρ型ΙΠ 族氮化物半導體層之成長溫度的± 1 00 °C範圍之溫度 〇 [發明之實施範例] 以下則敘述使用第1圖、第2圖之本發明的實施範例。第 1圖爲展示關於本發明之m族氮化物半導體LED構造的剖面 模型圖。又，第2圖爲關於本發明之m族氮化物半導體LED 之平面模型圖。 示於第1圖之LED可由在藍寶石或氧化鋅（ZnO )等之絕緣 性的單晶基板上、以有機金屬化學氣相沉積（M0CVD )法來層 壓ΙΠ族氮化物半導體所形成的積層構造體所構成。構成LED 之積層構造體可於單晶基板101上依序層壓由氮化鋁鎵 (AlxGa|.xN : 0 S X S 1 )所構成的緩衝層102、由作爲第1 個N型Π於氮化物半導體層之η型氮化鋁鎵（AlxGa,_xN ·· 0 客XS 1)所構成的η型下方覆蓋層103 、由氮化鋁銦 (AlxIn,_xN : OS XS 1)所構成的發光層104、由作爲ρ型 Π族氮化物半導體層且ρ型雜質爲已參雜之AUGa^NiOS 1)所構成之P型上方覆蓋層1〇5、以及接著ρ型上方覆 蓋層1 0 5形成的第2個η型Π族氮化物半導體層1 06而形成 —i - - n —————— . I I I !| 訂 二 、' (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部智慧財產局員工消費合作社印製 A7 B7___五、發明説明（7) 〇 第1個實施範例中層壓有m族氮化物半導體層之積層構 造體的特徵爲設置有接合於作爲p型m族氮化物半導體層 的P型上方覆蓋層之第2個η型m族氮化物半導體層。第2 個η型瓜族氮化物半導體層具有捕捉由氣相成長環境氣體 侵入於ρ型上方覆蓋內而來的氫不純物之作用。因此，具有 以生成態（a s - g r own )狀態使ρ型上方覆蓋層變爲低電阻之ρ 型層。又如後述者，根據層壓於P型上方覆蓋層上的ΠΙ族氮 化物半導體層作爲η型層方面，可形成能發揮電流阻止機能 的Ρη接合。因此，本發明中則由η型m族氮化物體層構成 接於p型上方覆蓋層所形成的ΙΠ於氮化物半導體層（第2個 Π型m族氮化物半導體層）。第2個η型m於氮化物半導體層 一般可由 AlxGaYInzN(OS X,Y,ZS 1)所形成。 第2個η型ΙΠ族氮化物半導體層在p型上方覆蓋層之氣相 成長結束後，繼續在與同層之成長溫度大約相同之成長溫 度下氣相成長。大約相同的溫度爲以ρ型上方覆蓋層之成長 溫度爲基準之± 1 〇 〇 t：的範圍內，又成長溫度未滿8 0 0 〇c， 不能從P型上方覆蓋層脫逸之殘留於該層內的氫不純物濃 度會變高。因此’第2個η型m族氮化物半導體層之成長溫 度以800 °C以上爲佳。 (第2之實施範例） 在有關於本發明之專利申請專利範圍第2項的第2實施 範例中’於p型m於氮化物半導體層之大約全部平面上一樣 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） 466 78 3 經濟部智慧財產局員工消費合作社印製 A7 WJ_五、發明説明（δ* ) 地不殘留η型m族氮化物半導體層。第2個η型m族氮化物 半導體層1 0 6，則以殘留於形成第2個η型底座電極1 0 8之 區域1 0 8 a的第2個η型底座電極1 0 8之投影區域者佳。另一 方面，第1個η型底座電極1 〇 7，則設置於例如作爲第1個 η型Π族氮化物半導體層之η型下方覆蓋層1〇3表面上，並 且是形成第1個η型底座電極107之區域107a上。第2個η 型底座電極108，則設置於形成第2個η型底座電極108區 域1 08 a之殘留有第2個11型111族氮化物半導體層1〇6上。限 定於特定之區域，在殘存第2個η型m族氮化物半導體層106 中，可利用使用光學平版印刷技術的圖案形成袪（攝影蝕刻 法），並以電漿蝕刻法等手段來除去不必要的第2個η型ΠΙ 族氮化物半導體層106。 (第3之實施範例） 在有關記載於本發明之申請專利範圍第3項之發明的第 3實施範例中，形成第1個η型底座電極1 0 7之區域1 〇 7 a的 平面形狀與形成第2個η型底座電極108之區域l〇8a的平面 形狀爲相似形。若形成第1及第2個η型底座電極1 〇 7、1 0 8 之區域1 07a、1 08a的平面形狀爲相似形，可使已除去形成 2個η型底座電極108之區域108a的p型上方覆蓋層表面 l〇5a變爲大約左右對稱的平面形狀。因此，可達到從發揮 集光作用之發光元件的外圍器射出的發光之圖案變爲大約 左右對稱形狀的效果’並可提供相關射出方向之發光強度 均衡的ΙΠ族氮化物半導體發光元件。 -1 0 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 4 6 6 783 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（々） (第4之實施範例） 利用第2圖來說明有關記載於本發明之申請專利範圍第 4項之發明’形成第1個n型底座電極1 〇 7之區域1 〇 7 a與形 成第2個n型底座電極1〇8之區域i〇8a大約爲相似形，若平 .面積大約相同，則可使p型上方覆蓋層表面1〇53的平面形 狀變爲大約左右對稱形狀。所謂大約相似形爲例如週邊的 一部份形狀不同而本體同形狀者。所謂平面積大約相同爲 相對於形成第1個η型底座電極之區域，形成第2個η型底 座電極區域之平面積比例爲〇 · 7.至1.4之範圍內，而以0.8 至1.2之範圍內爲佳。 (第5之實施範例） 又’在有關記載於本發明之申請專利範圍第5項之發明 的第5實施範例中，配置第1個η型底坐電極與第.2個η型 底座電極，在相對於m族氮化物半導體發光元件之平面形 狀中心點的對稱位置。即如第2圖所示，配置第1及第2個 η型底座電極107、108。在相對於皿族氮化物半導體LED 之平面形狀中心點C的對稱位置。對稱地配置以中心點c爲 基準的底座電極1〇7、108，以及底座電極107、108相互 間的距離隔開，可抑制在底座電極間短路地流通元件驅動 電流。所以，由於可分配元件驅動電流於比發光面廣的範 圍，而達到擴長LED之發光面積的效果。 (第6之實施範例） 在有關記載於本發明之申請專利範圍第6項之發明的第 -11- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 466783 經濟部智慧財產局員工消費合作社印製 A7 _B7_五、發明説明（β) 6實施範例中，如第1圖所示，形成被覆至少一部份之前述 Ρ型上方覆蓋層105與前述第2個η型m族氮化物半導體層 106之p型歐姆電極，並於該p型歐姆電極1〇9上形成前述 第2個η型底座電極108。p型歐姆電極109則由相對於LED 之發光的透明質材所形成。在通導於第2個η型底座電極的 Ρ型上方覆蓋層105之表面上形成ρ型歐姆電極109所構成 ，並舉出分配元件驅動電流於由第2個η型底座電極1 08經 由Ρ型歐姆電極109的發光層104之大約全部面積。於本發 明中，只設置Ρ型歐姆電極109於ρ型上方覆蓋層105而不 能構成，亦可被覆殘留之第2個η型ΙΠ族氮化物半導體層106 而形成。 (第7之實施範例） 在有關記載於本發明之申請專利範圍第7項之發明的第 7實施範例中，在以第2個η型ΙΠ族氮化物半導體層106與ρ 型上方覆蓋層105之接觸而形成的ρη接合106a上，形成前 述第2個η型第座電極108。以配置pn接合l〇6a於第2個η 型第座電極108與發光層104的中間，達到防止短路地流通 由第2個η型第座電極1 0 8供給的元件驅動電流於該垂直之 發光層104的效果。該ρη接合106a具有阻止流通元件驅動 電流於難以取出發光於作爲第2個η型底座電極之投影區 域的外部區域，並且優先地擴散驅動電流於Ρ型上方覆蓋層 表面的作用。 如至今所述，若接合第2個η型H[族氮化物半導體層於作 -12- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 4 6 6 78 3 經濟部智慧財產局員工消費合作社印製 A7 B7_五、發明説明（|丨） " '~ 爲p型m族氮化物半導體層之p型上方覆蓋層的積層構造 只經由一次的氣相成長’則不必要爲了低電阻化添加有p 型雜質之瓜族氮化物半導體層氣相成長後之熱處理步驟， 加上以生成態（a s - g r own )狀態可獲得低電阻之p型皿族氮 化物半導體層’具有一倂形成完成電流阻止機能之？11接合 的優點。 於本發明中’第2個η型瓜族氮化物半導體層之氣相完成 後，在隨著層壓該層的狀況來冷卻基板方面，以生成態 (a s - g r 〇 w η )狀態形成的低電阻ρ型ΠΙ族氮化物半導體層的 電阻率可望在室溫下爲10Ω. cm以下。又，ρ型瓜族氮化 物半導體層以由以AlxGaYInzN(OS 1、〇$ ys 1、〇 S Z S 1、X + Y + Z=l )表示的氮化鋁鎵銦形成爲佳。ρ型m族 氮化物半導體層之比電阻則依附上層之第2個η型m族氮 化物半導體層的載體濃度、層厚及成長溫度。爲了製造本 發明之ffl族氮化物半導體發光元件，在依次以氣相成長法 層壓前述發光層、前述p型m族氮化物半導體層、前述第2 個η型m族氮化物半導體層時，以8 0 〇 °c以上作爲前述第2 個η型ΙΠ族氮化物半導體層之成長溫度，同時以相對於前述 Ρ型瓜族氮化物半導體層之成長溫度±100 °C範圍之溫度作 爲前述第2個η型ΠΙ於氮化物半導體層之成長溫度。 又，本發明之第2個η型m族氮化物半導體層，則於該氣 相成長時摻雜層壓矽（Si)、硒（Se)或硫（S)等之η型雜質。 特別是矽具有較硒或碲（Te)等第IV族元素難熱擴散之優點 n- an n^— n·— n^i 11 -/ n^i I i In ml' nn、一-eJ -- - .-· (請先聞讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 4 6 6 783 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（11) 。因此，使用矽作爲η型雜.質則可滅少η型雜質擴散或侵入 ρ型m族氮化物半導體層內部之可能性。即’如果使用矽作 爲η型摻雜物，則減低電氣補償P型瓜族氮化物半導體層中 之P型雜質的程度，以於生成態Us-grown)而得的ρ型ΠΙ族 氮化物半導體層則變得合適。更進一步而言，第2個η型皿 族氮化物半導體層則以矽之摻雜效率高、且以摻雜控制濃 度容易的η型氮化鋁鎵銦AlxGaYInzN(0客1、OS Υ各 1、0 S Z S 1、X + Y + Z=l )形成爲佳。特別以使用氮化鎵（GaN) 爲佳。 於本發明中，第1及第2個η型底座電極則以設置於電阻 率變爲1 X 10_2 Ω · cm以下之η型ΠΙ族氮化物半導體層的 表面上爲佳。於較電阻率1 X 1〇 — 2 Ω · cm大的η型m族氮 化物半導體層之上，設置歐姆接觸性優異的η型底座電極則 變得困難。然而，於電阻率較5 X 1 (Γ4 Ω · cm小的η型Π 族氮化物半導體層上，一般由於摻雜了超過1 X 1019 cm3的 多量η型雜質，則會損害表面之平坦性。因此，電阻率爲5 X 1 0_4 Ω · cm以下的η型ΙΠ族氮化物半導體層則得到安定 之接觸性優異的η型底座電極的障礙，而第1及第2個η型 底座電極以形成電阻率爲5Χ 10_4Ω · cm以上之η型m族 氮化物半導體層爲佳。 又，第2個η型1Π族氮化物半導體層之載體（carrier)濃 度値（單位：cm — 3)與層厚値（單位：cm)之乘積爲5 X l〇1(1cnr2至1 . 5 X 10Mcm —2，則可較有效率地防止氫雜質侵 -14- (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 466 783 A7 A7 B7 五、發明説明（f3〇 入P型瓜族氮化物半導體層內。在低設定第2個η型ΠΙ族氮 化物半導體層之載體（c a r r i e r )濃度範圍的情況下則增加 層厚。第2個η型Π族氮化物半導體層之最低的η型載體 (carrier)濃度大槪爲1 X l〇l7cm·3。又，最大層厚約爲5 .// m(5x 10 — 4cm)。第2個η型ΙΠ族氮化物半導體層之層厚 變得極端地厚，則與垂直之p型Μ族氮化物半導體層的差距 變大，導致不適於p型歐姆電極之形成。載體（carrier)濃 度則可由平常的容量-電壓特性測定法或霍爾（H a 1 1 )效應 測定法等來測定。 在本發明之ΠΙ族氮化物半導體發光元件方面，以由不同 的銦（I η )組成比之複數相（p h a s e )構成的多相構造（m u 1 t i -Phase)之m族氮化物半導體所構成發光層有得到高強度之 發光的優勢。多相構造之發光層則在例如作爲第1個η型皿 族氮化物半導體層之η型下方覆蓋層上，以大約從7 00 °C至 950 °C之範圍層壓含有銦的ΠΙ族氮化物半導體層而形成。又 ，以在發光層之層壓後調節昇溫速度或冷卻速度，可使發 光層變爲多相構造。特別以使用環戊二烯銦（C5H5I η )作爲銦 原料的MOCVD來層壓發光層，以及由於可避免與作爲氮原的 氨（νη3 )等在氣相中的複合反應，可形成主體相與從屬相之 存在密度大致均一的多相構造發光層。 [實例] (實例） 在本實例中，則使用第4、 5圖來說明由層壓m族氮化物 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) '裝. 訂 經濟部智慧財產局員工消費合作社印製 466783 A7 ____ _B7____ 五、發明説明（Hf) (請先閱讀背面之注意事項再填寫本頁) 半導體層於藍寶石基板上來製作LED的範例。第4圖爲有關 於本實例之LED的平面模型圖。又，第5圖爲沿著第4圖之 平面模型圖所示之LED的虛線A-A’之剖面模型圖。 LED用途之積層構造體爲在具有（0001)晶面之藍寶石單 '晶基板5 0 1上，以氮化鎵（G a N )所構成的緩衝層5 0 2、由摻 雜砂（Si)之n型氮化錠（GaN)所構成的η型下方覆蓋層（第] 個η型Ε[族氮化物半導體層）5〇3、以Ga()95ln()()5N所構成的 主體相、以銦組成比平均爲0. 15的GaQ.85In().MN所構成之 從屬相所構成的多相構造之η型發光層504、由摻雜在厚的 方向由0 . 1 5至0來變化鋁組成X的鎂之A 1 , _XG a ΧΝ所構成的 Ρ型上方覆蓋層（ρ型瓜族氮化物半導體層）505、以及摻雜 砂的η型氮化鎵層（第2個η型m族氮化物半導體層）506所 構成（參照第5圖）。 . 經濟部智慧財產局員工消費合作社印製 瓜族氮化物半導體層502〜506則以使用三甲基鎵 ((CH3)3Ga)、三甲基鋁（（CH3)3A1)、環戊二烯基銦（C5H5In) 、氨（NH3 )爲原料的常壓MOCVD法來生成。利用含有二矽烷 (S i 2H6)約1 〇體積ppm濃度的二矽烷與氫的混合氣體作爲矽 的摻雜原料。鎂的摻雜原料方面則利用雙環戊二烯基鎂 (bi s - (C5H5 )2Mg)。由多結晶構成的緩衝層502則於430 °C下 層壓而成。多相結構之發光層504的層壓溫度爲890 °C，其 他ΠΙ族氮化物半導體層503、505、506之層壓溫度爲1030 °C。p型上方覆蓋層50 5則由具有於與發光層504之接合界 面的鋁組成比（X )爲0 . 1 5、於表層X爲0的鋁組成之斜度的 -16- 本紙張尺度適用中國國家標準（CNS > A4规格（210X297公釐） 466783 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（ΙΓ) A 1 ! -xGaxN所構成。鋁組成之斜度則於以MOCVD法層壓時間 之同時減少添加於MOCVD法之生成裝置的三甲基鋁而形成 緩衝層502之層厚約爲17mm。η型下方覆盖層503層厚 + 爲 3.5#m，而載體（carrier)濃度爲 2Χ l〇i8cm_3。ρ 型上 _方覆蓋層505層厚爲0.25 。p型上方覆蓋層.內由銘組成 比約略固定爲0 . 1 5的GaQ.85〗nfl.MN所構成之區域的層厚約 爲0 · 0 5 // m。又，表層部份之銘組成比爲0，即，由氮化鎵 所構成的區域之層厚約爲0.1 。.p型上方覆蓋層505中 的鎂摻雜量約爲7 X l〇18cm_3。由於在p型上方覆蓋層505 上接著設置η型氮化鎵，故p型上方覆蓋層505變爲於生成 態（a s - g r 〇 w η )狀態之ρ型低電組，而該載體（c a r r丨e r )濃度 則變爲4X 1017cirT3。p型上方覆蓋層505內之氫元子濃度 約爲7 X 1017cnT3。η型氮化鎵層506之層厚爲〇.15 ， 而該載體（carrier)濃度則約爲2 X l〇18cm —3。即，^型氮 化鎵層506之載體（carrier)濃度與層厚之乘積値變爲3.0 X 1 0 丨3 cm·2。 P型上方覆蓋層505之層壓結束後不改變層壓溫度並繼 續成長η型氮化鎵層506。堆積n型氮化鎵層5〇6於p型上 方覆蓋層5 0 5後’將積層構造體之溫度於氨氣流中以每分鐘 2 0 °C降溫至8 0 0 °C。由8 0 0 °C至室溫附近溫度的降溫則於氫 氣環境氣體內自然地冷卻。以該降溫操作來謀求構成多相 結構之發光層5 0 4之主相與從屬相之姻組成、形狀、以及尺 -17- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） mu It— 1 nn mvr —r .-- : .' (請先閲讀背面之注意事項再填寫本頁) 466 783 A7 B7 丨 1 1"" 五、發明説明（a ) 寸大小之均一化。 在冷卻至室溫而形成積層構造體結束後，從MOCVD法$ 生成裝置中取出。然後，去除表面上的η型氮化鎵層5 06而 形成第2個η型底座電極之區域5 0 9 a，依照一般的圖案成 _开乡技術法（攝影触刻法）與電獎触刻方法來由p型上方覆g _層505之表面除去。如第4圖所不，除了形成正方形LED之 一角的第2個η型底座電極之區域509a，殘留了 η型氮化鎵 層506於ρ型上方覆蓋層505。因此，可於第2個η型底座 電極509之下方形成ρη接合506a »殘留於ρ型上方覆蓋層 50 5之η型氮化鎵層506平面形狀爲與第2個η型底座電極 5 0 9爲相似形的邊長約1 3 0 β m之正方形。形成第2個η型底 座電極5 09區域509a的平面積爲7 X 1 〇'4cm2。 經濟部智慧財產局員工消費合作社印製 n^i ϋ· n^i —f^i n ^^^1 - «—^1 1^1^1 nn m ί IV. 穿 i ; ;; - (請先閎讀背面之注意事項再填寫本頁) 其次，於除了形成第2個η型底座電極5 0 9 a之殘留的n .型氮化鎵層506表面與ρ型上方覆蓋層505表面上，以一般 的電子束（be am)電鍍法於大約250 °C下被覆氧化鎳（NiO)薄 膜507。氧化鎳薄膜507之層厚約爲]3nm。於同一條件下 層壓於其他玻璃基板上之膜厚爲1 3 n m的氧化鎳薄膜之對波 長450nm之青色光的透過率爲84%。於氧化鎳薄膜上則以一 般的高周波濺鍍法來全面被覆透明且具有傳導性的銦錫氧 化物（I TO )膜5 0 8。爲了形成I TO膜5 0 8所進行的濺鍍法之 壓力約爲1 X 1 (T3Tor r，施加的高周波電力約爲1 50W。IT0 膜508之層厚約爲0.3 //m。IT0膜508之電阻率變爲大約8 X 10“Ω · cm。由以上之氧化鎳薄膜507與I TO膜508構成 - -18- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29'7公釐） 4 6 6 78 3 A7 B7___________ 五、發明説明（/?) P型歐姆電極5 1 0。 (請先閱讀背面之注意事項再填寫本頁) 於形成第2個η型底座電極之區域.509 a的P型歐姆電極 上則設置有第2個η型底座電極5 0 9。第2個η型底座電極 5Ό 9之接於I TO膜5 0 8的電極下層部份5 0 9 - 1則以駄形成’ 而膜厚約爲2 5 0 n m。電極上層部份5 0 9 - 2則以金形成’而膜 厚約爲1 . 0 // m。 第1個η型底座電極5 1則形成於以使氬（A r )、甲院（CH4 ) 及氫之混合氣體的電漿蝕刻法依序除去在形成第1個1 n ® 底座電極之區域511a上的η型氮化鎵層506、P型上方覆蓋 層505、及多相構造發光層504而裸露出的η型下方覆蓋層 503之表面上。形成第1個η型底座電極511之區域511a爲 一邊爲1 3 0 // m、即平面積約爲1 . 7 X 1 (Γ4 c m2的正方形區域 。即，相對於形成第1個η型底座電極區域511a之面積’ 形成第2個η型底座電極區域5 0 9 a之面積比例爲1 . 〇。第1 個η型底座電極511則由鋁（A1)構成，該層厚約爲1.2 /im 。第1個η型底座電極511之平面形狀爲一邊約爲110 的正方形。形成第1及第2個η型底座電極之區域509a、 經濟部智慧財產局員工消費合作社印製 5 1 1 a，以及第1及第2個η型底座電極5 0 9、5 1 1則配置於 相對於LED之中心點的對稱位置。使以該配置之第1、第2 個η型底座電極5 0 9、5 1 1間之距離爲最大極限，並且除去 形成第1及第2個η型底座電極之區域509a、511a，而Ρ 型上方覆蓋層之表面5 0 5 a之平面形狀則左右對稱於通過晶 片中心點C的對角線B - B ’。 ’ -1 9 - ϋ張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ~ " 4 6 6 78 3 A7 B7 _ 五、發明説明（β) 其次’分割上述積層構造體成一邊約爲350#m的晶片， 並個別形成LED。在經由第1、第2個η型底座電極509、 (請先閱讀背面之注意事項再填寫本頁) 5 1 1 ’順著該LED方向流通20mA的電流時，由在第2個η型 底座電極之形成區域5 0 9 a的外緣之ρ型上方覆蓋層表面 505a的大約全面上以槪略均一的強度發射青色光。以分光 器測定的發光波長約爲4 6 0 n m ’發光光譜之半幅長則爲3 0 n m 。順著方向流通20mA電流時的電壓平均爲3 . 2伏特（V )。 LED之發光強度約爲20微瓦特（"W)，製作出高輸出功率的 瓜族氮化物半導體LED。又，於以一般的環氧樹脂密封該 LED而製成頭部具備用於集光的微透鏡的燈具則爲該發光 強度之角度分佈約略左右對稱形狀而適用。 [發明之效果] 經濟部智慧財產局員工消費合作社印製 根據本發明，添加p型雜質的m族氮化物半導體層可於 生成態（a s - g r 〇 w η )狀態變爲低電阻之ρ型。又，於利用爲了 於生成態（a s - g r own )狀態形成低電組之ρ型皿族氮化物半 •導體層之η型氮化物半導體層（第2個η型ΙΠ族氮化物半導 體層）的pn接合上設置ρ型m族氮化物半導體層之底座電 極的結果，由於可達成阻止電流短路地流入第2個η型底座 電極垂直部份，故可有效地分配元件驅動電流於發光於外 部之區域，並可提供高發光輸出功率的m族氮化物半導體 發光元件。 [圖式之簡單說明] 第1圖爲記載於本發明之實施範例的m族氮化物半導體 -20- 本紙張尺度適用中國國家標準（CNS ) 格（210X297公釐） 4 6 6 78 3 A7 B7 五、發明説明（I f) LED剖面模型圖。 第2圖爲記載於本發明之實施範例的m族氮化物半導體 LED剖面模型圖。 第3圖爲習知之瓜族氮化物半導體LED剖面模型圖。 第4圖爲關於本發明之實施範例的LED平面模型圖。 第5圖爲沿著示於第4圖之LED的虛線A-A’之剖面模型圖 經濟部智慧財產局員工消費合作社印製 [符號說明 ] 101 單晶基 板 102 緩衝層 103 η型下方覆 蓋 層 104 發光層 105 Ρ型上方覆 蓋 層 105a Ρ型上方覆 蓋 層 之 表 面 106 第2個 η型 m 族 氮 化 物 半 導 體 層 106a ρη接合 107 第1個 η型 底 座 電 極 107a 形成第 1個 η 型 底 座 電 極 之 區 域 108 第2個 η型 底 座 電 極 108a 形成第 2個 η 型 底 座 電 極 之 區 域 109 Ρ型歐姆電 極 30 1 藍寶石 基板 302 緩衝層 -21- 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） ---------:裝--------訂 (請先閲讀背面之注意事項再填寫本頁) A7 466783 B7 五、發明説明U。） 經濟部智慧財產局員工消費合作社印製 303 n型下方覆蓋層 304 發光層 305 P型上方覆蓋層 306 P型底座電極 307 P型歐姆電極 308 η型底座電極 309 電流阻止層 501 藍寶石單晶基板 502 緩衝層 503 η型下方覆蓋層 504 發光層 505 Ρ型上方覆蓋層 5 0 5 a Ρ型上方覆蓋層之表面 506 η型氮化鎵層 5 0 6 a ρη接合 507 氧化鎳薄膜 508 ΙΤΟ膜 509 第2個η型底座電極 5 0 9 a 形成第2個η型底座電極之區域 5 0 9 -1 電極下層部份 5 0 9 -2 電極上層部份 5 10 ρ型歐姆電極 5 11 第1個η型-底座電極 5 11a 形成第1個η型底座電極之區域 C LED之平面形狀中心點 -22 - (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）AlxGaYInzN 'but formed by OS 1, OS YS 1, 〇 $ 1, χ + γ + ζ = ι), and the resistivity of the p-type m group nitride semiconductor layer is less than 10Ω · cm; [9] such as [7 [M] is a nitride semiconductor light-emitting device, in which silicon (Si) is added as an impurity to the second n-type melon nitride semiconductor layer; [10] The m-group nitride semiconductor according to [9] emits light Device, but where the second n-type m group nitride semiconductor layer is composed of aluminum gallium indium nitride (compositional formula is AlxGaYInzN 'but 0 each XS 1, 0 彡 Yg 1, 〇 $ z S 1' X + Y + Z = l); [11] The m-group nitride semiconductor light-emitting device as described in [7], wherein the resistivity of the first and second n-type m-group nitride semiconductor layers is 5 × 10 ′. 4Ω · cm or more, IX 1 (Γ2Ω · cm or less; [1 2] m is a nitride semiconductor light-emitting device as described in [7], but the second n-type III is on a nitride semiconductor layer carrier ( The product of carrier) concentration 値 (unit: cnT3) and thickness 値 (unit: cm) is in the range of 5X l01Qem-2 or more and 1.5 X 1 0l5cnT2 or less: Π3] Group m nitrogen as described in [1] Material semiconductor light-emitting device, wherein the light-emitting layer is formed of a group III nitride semiconductor having a multi-phase structure composed of a plurality of phases of different indium composition ratios; [1 4] The group nitride semiconductor described in [1] The manufacturer of the light-emitting element is sized according to the Chinese National Standard (CNS) A4 (210X297 mm) H · nw mV i -— ^ 1 · m · — ^ ϋ ^ n · n ^ i 0¾-9;. (Please (Please read the notes on the back before filling this page) 466783 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 _V. Invention Description (6) method, in which the first η-type is sequentially laminated by the vapor phase growth method Growth temperature of the second n-type III nitride semiconductor layer when the III-nitride semiconductor layer, the light-emitting layer, the p-type III-nitride semiconductor layer, and the second n-type III-nitride semiconductor layer It is 800 ° C, and the growth temperature of the second n-type m group nitride semiconductor layer is a temperature in the range of ± 100 ° C relative to the growth temperature of the p-type group III nitride semiconductor layer. [Implementation of the invention Example] The following is a description of the present invention using Figs. 1 and 2. Example. Fig. 1 is a cross-sectional model diagram showing the structure of the m-group nitride semiconductor LED of the present invention. Fig. 2 is a plan model diagram of the m-group nitride semiconductor LED of the present invention. It is shown in Fig. 1 The LED can be composed of a laminated structure formed by laminating a group III nitride semiconductor by an organometallic chemical vapor deposition (MOCVD) method on an insulating single crystal substrate such as sapphire or zinc oxide (ZnO). The multilayer structure constituting the LED can be sequentially laminated on the single crystal substrate 101 with a buffer layer 102 composed of aluminum gallium nitride (AlxGa | .xN: 0 SXS 1), and formed as a first N-type nitride on the nitride. N-type lower cladding layer 103 composed of n-type aluminum gallium nitride (AlxGa, _xN ·· 0 guest XS 1) of a semiconductor layer, and a light-emitting layer 104 composed of indium aluminum nitride (AlxIn, _xN: OS XS 1) A P-type upper cladding layer 105 composed of a p-type group III nitride semiconductor layer and a p-type impurity AUGa ^ NiOS 1), and a p-type upper cladding layer 105 Formed by two n-type Π-nitride semiconductor layers 1 06 —i--n ——————. III! | Order II, '(Please read the precautions on the back before filling this page) This paper size applies China National Standard (CNS) A4 specification (210X297 mm) Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7___ V. Description of the invention (7) 〇 In the first example, a layer of a m-type nitride semiconductor layer is laminated. The structure is characterized by a second n-type m group provided with a p-type upper cladding layer bonded to the p-type m group nitride semiconductor layer. Nitride semiconductor layer. The second n-type melon nitride semiconductor layer has a function of trapping hydrogen impurities which are intruded into the upper layer of the p-type by a gas phase growth environment gas. Therefore, it has a p-type layer with a low resistance in a generated state (as s-gr own). As described later, according to the aspect of the group III nitride semiconductor layer laminated on the P-type cladding layer as the n-type layer, it is possible to form a pn junction capable of exerting a current blocking function. Therefore, in the present invention, the n-type m-group nitrided object layer is used to form a nitride semiconductor layer (the second Π-type m-nitride semiconductor layer) formed next to the p-type upper cladding layer. The second n-type m-on-nitride semiconductor layer is generally formed of AlxGaYInzN (OS X, Y, ZS 1). After the vapor phase growth of the second n-type group III nitride semiconductor layer over the p-type cladding layer is completed, the vapor phase growth is continued at a growth temperature approximately the same as the growth temperature of the same layer. Approximately the same temperature is within the range of ± 1 000 t: based on the growth temperature of the cladding layer above the p-type, and the growth temperature is less than 8 0 0 c. The concentration of hydrogen impurities in this layer becomes higher. Therefore, the growth temperature of the 'n-type m-type nitride semiconductor layer is preferably 800 ° C or higher. (Second embodiment example) In the second embodiment example of item 2 of the scope of patent application for the present invention, the p-type m is the same on approximately all planes of the nitride semiconductor layer (please read the precautions on the back first) (Please fill in this page again) This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 466 78 3 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 WJ_V. Description of Invention (δ *) No residue A m-type nitride semiconductor layer. The second n-type m-type nitride semiconductor layer 10 6 is a projection region of the second n-type base electrode 108 which remains in the region 1 0 8 where the second n-type base electrode 108 is formed. Is better. On the other hand, the first n-type base electrode 107 is provided on the surface of the n-type undercoating layer 103 which is the first n-type group III nitride semiconductor layer, for example, and forms the first n On the region 107a of the base electrode 107. The second n-type base electrode 108 is disposed on the second 11-type 111-type nitride semiconductor layer 106 formed in the region 1 08 a where the second n-type base electrode 108 is formed. Limited to a specific area, in the remaining second n-type m-group nitride semiconductor layer 106, patterning (photographic etching) using optical lithography can be used to pattern the photoresist, and plasma etching can be used to remove the Necessary second n-type group III nitride semiconductor layer 106. (Third embodiment example) In the third embodiment example of the invention described in item 3 of the scope of patent application of the present invention, the planar shape of the area 1 〇7 a of the first n-type base electrode 107 is formed. The planar shape of the area 108a forming the second n-type base electrode 108 is similar. If the planar shapes of the areas 1 07a and 1 08a of the first and second n-type base electrodes 1 107 and 108 are similar, the p of the region 108a where the two n-type base electrodes 108 are formed can be removed. The surface 105a of the upper cover layer of the mold becomes approximately a left-right symmetrical planar shape. Therefore, it is possible to achieve the effect that the light emission pattern emitted from the peripheral device of the light-emitting element which functions as a light-collecting device is changed to a roughly symmetrical shape 'and to provide a group III nitride semiconductor light-emitting element with a uniform emission intensity in the emission direction. -1 0-This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) (Please read the notes on the back before filling out this page) 4 6 6 783 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Explanation of the invention (i) (Example of the fourth embodiment) The second invention is used to describe the invention described in the fourth item of the patent application scope of the present invention, 'the area 1 where the first n-type base electrode 1 0 7 is formed. 7 a is approximately similar to the area i〇8a forming the second n-type base electrode 108. If the flat area is approximately the same, the planar shape of the surface of the overcoat layer 1053 above the p-type can be changed to about the same. Symmetrical shape. The so-called similar shape is, for example, a shape in which a part of the periphery is different and the body is the same shape. The so-called flat area is about the same as that of the area where the first n-type base electrode is formed, and the area ratio of the flat area where the second n-type base electrode is formed is in the range of 0.7 to 1.4, and in the range of 0.8 to 1.2. Inside is better. (Fifth embodiment example) In the fifth embodiment example of the invention described in the fifth item of the patent application scope of the present invention, the first n-type bottom seat electrode and the second n-type base electrode are arranged. A symmetrical position with respect to the center point of the planar shape of the m-type nitride semiconductor light-emitting element. That is, as shown in Fig. 2, the first and second n-type base electrodes 107 and 108 are arranged. Symmetrical position with respect to the center point C of the planar shape of the ceramic nitride semiconductor LED. The base electrodes 107 and 108 and the base electrodes 107 and 108 are symmetrically arranged with the center point c as a reference, and the base electrodes 107 and 108 are spaced apart from each other, so that a component driving current can be suppressed from short-circuiting between the base electrodes. Therefore, since the drive current of the distributable element can be distributed in a wider range than the light emitting surface, the effect of increasing the light emitting area of the LED is achieved. (Example of the 6th embodiment) In the -11-th aspect of the invention described in item 6 of the scope of patent application for the present invention, the paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the back Note: Please fill in this page again) 466783 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _B7_ V. Description of Invention (β) 6 In the implementation example, at least part of the aforementioned P-type is formed as shown in Figure 1. The upper cladding layer 105 and the p-type ohmic electrode of the second n-type m-type nitride semiconductor layer 106 described above, and the aforementioned second n-type base electrode 108 is formed on the p-type ohmic electrode 109. The p-type ohmic electrode 109 is formed of a transparent material that emits light relative to the LED. A p-type ohmic electrode 109 is formed on the surface of the P-type upper cover layer 105 which is electrically connected to the second n-type base electrode, and the driving current is distributed to the second n-type base electrode 108 through the P-type. Approximately the entire area of the light emitting layer 104 of the ohmic electrode 109. In the present invention, the P-type ohmic electrode 109 is only provided on the p-type overlying cover layer 105 and cannot be formed. The second n-type group III nitride semiconductor layer 106 can also be formed by coating. (Seventh embodiment example) In the seventh embodiment example of the invention described in item 7 of the scope of patent application of the present invention, the second n-type group III nitride semiconductor layer 106 and the p-type upper cover layer 105 are covered. The second η-type seat electrode 108 is formed on the ρη bond 106a formed by the contact. The pn junction 106 is arranged between the second n-type seat electrode 108 and the light-emitting layer 104 in a configuration of pn, so as to prevent a short circuit from flowing a component driving current supplied from the second n-type seat electrode 108 to the vertical. Effect of the light emitting layer 104. The ρη junction 106a has a function of preventing the drive current from flowing through the element from being difficult to extract from the outer area emitting light to the projection area as the second n-type base electrode, and preferentially diffusing the drive current on the surface of the P-type upper cover layer. As described so far, if the second n-type H [group nitride semiconductor layer is used as a -12- (Please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 specification ( 210X297 mm) 4 6 6 78 3 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7_V. Description of the Invention (| 丨) " '~ is the p-type top cover layer of the p-type m-type nitride semiconductor layer The laminated structure only undergoes vapor phase growth once. It is not necessary to perform heat treatment steps after the vapor phase growth of the melon nitride semiconductor layer with p-type impurities added for the purpose of reducing the resistance, and it may be added in the as-grown state. Obtaining a low-resistance p-type nitride semiconductor layer has a formation of a current blocking function? 11 advantages of joints. In the present invention, after the gas phase of the second η-type melon nitride semiconductor layer is completed, it is formed in a generated state (as-gr 〇w η) in terms of cooling the substrate as the layer is laminated. The resistivity of the low-resistance p-type group III nitride semiconductor layer is expected to be 10 Ω · cm or less at room temperature. The p-type cucurbit nitride semiconductor layer is preferably formed of aluminum gallium indium nitride represented by AlxGaYInzN (OS 1, 0 $ ys 1, 0 S Z S 1, X + Y + Z = 1). The specific resistance of the p-type m-type nitride semiconductor layer depends on the carrier concentration, layer thickness, and growth temperature of the second n-type m-type nitride semiconductor layer of the upper layer. In order to manufacture the ffl group nitride semiconductor light-emitting device of the present invention, when the light-emitting layer, the p-type m-group nitride semiconductor layer, and the second n-type m-group nitride semiconductor layer are sequentially laminated by a vapor phase growth method, A temperature of 80 ° C or higher is used as the growth temperature of the second η-type III nitride semiconductor layer, and a temperature in the range of ± 100 ° C relative to the growth temperature of the P-type quaternary nitride semiconductor layer is used as the first 2 n-type III at the growth temperature of the nitride semiconductor layer. The second n-type m-type nitride semiconductor layer of the present invention is doped with n-type impurities such as silicon (Si), selenium (Se), or sulfur (S) when the gas phase is grown. In particular, silicon has the advantage that it is more difficult to thermally diffuse than Group IV elements such as selenium or tellurium (Te). N- an n ^ — n · — n ^ i 11-/ n ^ i I i In ml 'nn, a-eJ- --.- · (Please read the precautions on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210X297 mm) 4 6 6 783 A7 B7 Employee Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Printed 5. Description of Invention (11). Therefore, the use of silicon as the n-type impurity can reduce the possibility that the n-type impurity diffuses or penetrates into the p-type m-type nitride semiconductor layer. That is, 'If silicon is used as the n-type dopant, the degree of electrical compensation of the P-type impurity in the P-type melon nitride semiconductor layer is reduced, so that the p-type III-nitride semiconductor obtained from Us-grown) is reduced. The layers become appropriate. Furthermore, the second n-type ceramic group nitride semiconductor layer has high doping efficiency of silicon and easy control of doping concentration with n-type aluminum gallium indium AlxGaYInzN (0 guest 1, OS 1 each) , 0 SZS 1, X + Y + Z = 1). Particularly, gallium nitride (GaN) is preferably used. In the present invention, the first and second n-type base electrodes are preferably provided on the surface of the n-type group III nitride semiconductor layer having a resistivity of 1 X 10_2 Ω · cm or less. It is difficult to provide an n-type base electrode having an excellent ohmic contact on an n-type m group nitride semiconductor layer having a resistivity of 1 X 10 to 2 Ω · cm. However, on an n-type Π-type nitride semiconductor layer having a resistivity smaller than 5 X 1 (Γ4 Ω · cm), the surface flatness is generally impaired due to doping of a large amount of n-type impurities exceeding 1 X 1019 cm3. Therefore, the η-type ΙΠ group nitride semiconductor layer having a resistivity of 5 X 1 0_4 Ω · cm or less is a barrier to stable η-type base electrodes having excellent contact properties, and the first and second η-type base electrodes are formed. The n-type m-type nitride semiconductor layer having a resistivity of 5 × 10_4Ω · cm or more is preferred. The carrier concentration of the second n-type 1Π-type nitride semiconductor layer (unit: cm-3) and the layer thickness are preferred. The product of 値 (unit: cm) is 5 X l〇1 (1cnr2 to 1.5 X 10Mcm —2, which can effectively prevent the invasion of hydrogen impurities. -14- (Please read the precautions on the back before filling this page ) This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 466 783 A7 A7 B7 V. Description of the invention (f30 is entered into the P-type guar nitride semiconductor layer. At the low setting, the second η-type ΠΙ If the carrier concentration of the group nitride semiconductor layer is in the range, the layer is added. The lowest n-type carrier concentration of the second n-type group III nitride semiconductor layer is approximately 1 X 107 cm · 3, and the maximum layer thickness is approximately 5 // m (5x 10-4cm ). The layer thickness of the second n-type group III nitride semiconductor layer becomes extremely thick, and the gap with the vertical p-type group M nitride semiconductor layer becomes large, resulting in unsuitability for the formation of a p-type ohmic electrode. Carrier The carrier concentration can be measured by a conventional capacity-voltage characteristic measurement method or a Hall (H a 1 1) effect measurement method. In the group III nitride semiconductor light emitting device of the present invention, different indium (I η) The light emitting layer composed of a m-type nitride semiconductor of a multi-phase structure (mu 1 ti -Phase) having a composition ratio of multiple phases has the advantage of obtaining high intensity light emission. The n-type lower nitride clad layer, which is the first n-type dish-type nitride semiconductor layer, is formed by laminating a group III nitride semiconductor layer containing indium at a temperature ranging from about 700 ° C to 950 ° C. Furthermore, Adjust the heating rate or cooling rate after laminating the light-emitting layer to make the light emission It has a multi-phase structure. In particular, MOCVD using cyclopentadiene indium (C5H5I η) as an indium raw material is used to laminate the light-emitting layer, and compound reactions in the gas phase such as ammonia (νη3) as a nitrogen source can be avoided. A multi-phase structure light-emitting layer having a substantially uniform existence density of the main phase and the subordinate phase can be formed. [Example] (Example) In this example, the size of the m-nitride laminated paper is illustrated by using Figs. 4 and 5. Applicable to China National Standard (CNS) A4 specification (210X297 mm) (Please read the notes on the back before filling out this page) 'Packing. Order printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economy 466783 A7 ____ _B7____ V. Description of the invention ( Hf) (Please read the notes on the back before filling out this page) Example of making LEDs with a semiconductor layer on a sapphire substrate. Fig. 4 is a plan view of the LED in this example. Fig. 5 is a cross-sectional model view along the dotted line A-A 'of the LED shown in the plan model view of Fig. 4. The laminated structure for LED applications is a buffer layer 50 made of gallium nitride (G a N) on a sapphire single crystal substrate 5 01 having a (0001) crystal plane. 2. A doped sand (Si) The n-type lower cladding layer (nth) of the n-type nitride ingot (GaN) (the n-type E [group nitride semiconductor layer) 503 and the main phase composed of Ga () 95ln () () 5N Η-type light-emitting layer 504 with a multi-phase structure composed of a dependent phase of GaQ.85In (). MN composed of indium with an average composition ratio of 0.15, and from 0.1 to 5 by doping in a thick direction To change the aluminum composition X of magnesium, A 1, _XG a χN, a P-type upper cladding layer (p-type melon nitride semiconductor layer) 505, and a sand-doped n-type gallium nitride layer (second η A m-type nitride semiconductor layer) 506 (see FIG. 5). The Ministry of Economic Affairs ’Intellectual Property Bureau ’s Consumer Cooperative printed 502 ~ 506 nitride semiconductor layers using trimethylgallium ((CH3) 3Ga), trimethylaluminum ((CH3) 3A1), cyclopentadienyl Indium (C5H5In) and ammonia (NH3) are produced by a normal pressure MOCVD method. A mixed gas of disilane and hydrogen containing disilane (S i 2H6) at a concentration of about 10 vol. Ppm was used as a doping material for silicon. For the doping of magnesium, dicyclopentadienyl magnesium (bi s-(C5H5) 2Mg) was used. The polycrystalline buffer layer 502 is laminated at 430 ° C. The lamination temperature of the light-emitting layer 504 of the multi-phase structure is 890 ° C, and the lamination temperature of the other III nitride semiconductor layers 503, 505, and 506 is 1030 ° C. The p-type upper cladding layer 50 5 is composed of aluminum having a composition ratio (X) at the joint interface with the light-emitting layer 504 of 0.1 5 and an inclination of aluminum composed of 0 at the surface layer X of -16. Chinese National Standard (CNS > A4 specification (210X297 mm) 466783 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of invention (ΙΓ) A 1! -XGaxN. The slope of aluminum composition is based on The layer thickness of the MOCVD method while reducing the trimethylaluminum added to the MOCVD method forming device to form a buffer layer 502 is about 17 mm. The thickness of the n-type underlayer 503 layer is + 3.5 #m, and the carrier (carrier ) Concentration is 2 × 10i8cm_3. The upper layer of the p-type 505 layer has a thickness of 0.25. The upper layer of the p-type layer. The inner layer is composed of GaQ.85 with a composition ratio of approximately 0.15 and nfl.MN. The layer thickness of the region is about 0 · 0 5 // m. The composition ratio of the surface layer is 0, that is, the layer thickness of the region made of gallium nitride is about 0.1. The doping amount of Mg in Mg is about 7 × 1018cm_3. Since n-type gallium nitride is next disposed on the p-type upper cladding layer 505, The cover layer 505 becomes a p-type low-electric group in a generated state (as-gr 〇w η), and the carrier concentration becomes 4X 1017cirT3. Hydrogen atoms in the p-type upper cover layer 505 The concentration is about 7 × 1017cnT3. The layer thickness of the n-type gallium nitride layer 506 is 0.15, and the carrier concentration is about 2 × 1018 cm −3. The product of the carrier concentration and the layer thickness 値 becomes 3.0 X 1 0 丨 3 cm · 2. After the lamination of the P-type upper cover layer 505 is finished, the lamination temperature is not changed and the n-type gallium nitride layer 506 is continued to grow. After depositing an n-type gallium nitride layer 506 and covering the p-type layer 5 05, the temperature of the laminated structure is reduced in an ammonia gas flow at 20 ° C per minute to 80 0 ° C. From 8 0 0 The temperature decrease from ° C to room temperature is naturally cooled in the hydrogen ambient gas. The temperature reduction operation is used to seek the composition, shape, and ruler of the main phase and the subordinate phase of the light-emitting layer 504 constituting the multiphase structure. 17- This paper size is in accordance with Chinese National Standard (CNS) A4 (210X297 mm) mu It— 1 nn mvr —r .--:. '(Please read the note on the back first Matters then fill the page) 466 783 A7 B7 Shu 1 1 " " five, description of the invention (a) the size of the uniform inches. After cooling to room temperature to form a laminated structure, it was taken out from the MOCVD method generation device. Then, the n-type gallium nitride layer 5 06 on the surface is removed to form a second n-type base electrode region 5 0 9 a, which is formed in accordance with a general pattern _ Kaixiang Technology Method (Photographic Engraving Method) and Electric Award Contact The etching method is used to remove the surface of the g-layer 505 over the p-type. As shown in FIG. 4, except for the area 509a of the second n-type base electrode forming a corner of the square LED, an n-type gallium nitride layer 506 remains on the p-type overlying layer 505. Therefore, a ρη junction 506a can be formed below the second n-type base electrode 509. The n-type gallium nitride layer 506 remaining on the p-type upper cladding layer 50 5 has a planar shape similar to that of the second n-type base electrode 5 0 9 It is a similarly shaped square with a side length of about 1 3 0 β m. The plane area of the second n-type base electrode 509a region 509a was 7 × 10′4cm2. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs n ^ i ϋ · n ^ i —f ^ in ^^^ 1-«— ^ 1 1 ^ 1 ^ 1 nn m ί IV. Wear i; ;;-(please first (Please read the notes on the back side and fill in this page again.) Next, on the surface of the n.-type gallium nitride layer 506 and the surface of the p-type upper cover layer 505 except for the formation of the second n-type base electrode 5 0 9 a, A general electron beam (beam) plating method is coated with a nickel oxide (NiO) film 507 at about 250 ° C. The layer thickness of the nickel oxide thin film 507 is about 3 nm. Under the same conditions, the nickel oxide thin film with a thickness of 1 3 nm laminated on other glass substrates has a transmittance of cyan light having a wavelength of 450 nm of 84%. On the nickel oxide film, a transparent and conductive indium tin oxide (I TO) film 508 is fully covered by a general high frequency sputtering method. The pressure of the sputtering method used to form the I TO film 508 is about 1 X 1 (T3Tor r, and the applied high cycle power is about 150 W. The layer thickness of the IT0 film 508 is about 0.3 // m. The IT0 film 508 The resistivity becomes approximately 8 X 10 "Ω · cm. It is composed of the above nickel oxide film 507 and I TO film 508--18- This paper size applies to China National Standard (CNS) A4 (210X29'7mm) 4 6 6 78 3 A7 B7___________ 5. Description of the invention (/?) P-type ohmic electrode 5 1 0. (Please read the precautions on the back before filling this page) In the area where the second n-type base electrode is formed. 509 a On the P-type ohmic electrode, a second n-type base electrode 5 0 9 is provided. The second n-type base electrode 5Ό 9 is connected to the lower part of the electrode of the I TO film 5 0 8.駄 is formed 'and the film thickness is about 250 nm. The upper part of the electrode 509-2 is formed of gold' and the film thickness is about 1.0 0 m. The first n-type base electrode 51 is formed The n-type gallium nitride layer 506 on the region 511a where the first 1 n ® base electrode is formed is sequentially removed by a plasma etching method using a mixed gas of argon (A r), A-house (CH4) and hydrogen. P-type Overlay Layer 505, and the n-type lower cover layer 503 exposed on the surface of the multi-phase structure light-emitting layer 504. The area 511a forming the first n-type base electrode 511 is 1 3 0 // m on one side, that is, the flat area is about Is a square area of 1.7 X 1 (Γ4 c m2. That is, the area ratio of 5 0 9 a forming the second n-type base electrode region with respect to the area where the first n-type base electrode region 511a is formed is 1. 〇. The first n-type base electrode 511 is composed of aluminum (A1), and the thickness of the layer is about 1.2 / im. The planar shape of the first n-type base electrode 511 is a square with a side of about 110. The first and The area 509a of the second n-type base electrode, printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, 5 1 1 a, and the first and second n-type base electrodes 5 0 9, 5 1 1 are arranged relative to the LED Symmetrical position of the center point. The distance between the first and second n-type base electrodes 5 0 9 and 5 1 1 in this configuration is the maximum limit, and the distance between the first and second n-type base electrodes is eliminated. Areas 509a, 511a, and the planar shape of the surface 5 0 5 a of the overlying layer over the P-type is symmetrical to the left and right through the center point C of the wafer Diagonal line B-B '.' -1 9-The Chinese standard (CNS) A4 specification (210X297 mm) is applicable to the scale of the sheet ~ " 4 6 6 78 3 A7 B7 _ V. Description of the invention (β) Second 'The above-mentioned laminated structure is divided into wafers with a side of about 350 #m, and LEDs are individually formed. After passing the first and second n-type base electrodes 509, (please read the precautions on the back before filling this page) 5 1 1 'When a 20mA current flows in the direction of the LED, the second n-type base The surface of the p-type upper cover layer 505a on the outer edge of the electrode forming region 5 0 9 a emits cyan light at approximately uniform intensity over the entire surface. The light emission wavelength measured by the spectroscope is about 460 nm, and the half-length of the light emission spectrum is 30 nm. The average voltage when a 20 mA current flows in the direction is 3.2 volts (V). The luminous intensity of the LED is about 20 microwatts (" W), and a high-output guar nitride semiconductor LED is manufactured. In addition, a lamp which is sealed with a general epoxy resin to have a microlens for collecting light on the head is suitable for a symmetric shape of the angular distribution of the luminous intensity. [Effects of Invention] Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs According to the present invention, the m-type nitride semiconductor layer added with p-type impurities can be changed to a low-resistance ρ-type in the as-gr (as-gr 〇w η) state. . In addition, an η-type nitride semiconductor layer (a second η-type group III nitride semiconductor layer) is used to form a p-type group nitride semi-conductor layer of a low-electric group in the as-grown state. As a result of mounting the base electrode of the p-type m-type nitride semiconductor layer on the pn junction, since the current can be prevented from flowing into the vertical portion of the second n-type base electrode by short-circuiting, the device driving current can be effectively distributed to the outside. Area, and can provide m-nitride semiconductor light-emitting devices with high light-emitting output. [Brief description of the drawings] Figure 1 shows the m-type nitride semiconductor-20 described in the example of the present invention. The paper size applies the Chinese National Standard (CNS) grid (210X297 mm) 4 6 6 78 3 A7 B7 V. Description of the Invention (I f) LED sectional model. FIG. 2 is a cross-sectional model diagram of a group m nitride semiconductor LED described in an example of the present invention. FIG. 3 is a cross-sectional model view of a conventional melon nitride semiconductor LED. FIG. 4 is a plan view of an LED plane according to an example of the present invention. Figure 5 is a cross-sectional model diagram along the dotted line A-A 'of the LED shown in Figure 4. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs [Symbol] 101 Monocrystalline substrate 102 Buffer layer 103 η-type undercoat layer 104 Light-emitting layer 105 P-type upper cladding layer 105a P-type upper cladding layer surface 106 Second n-type m-type nitride semiconductor layer 106a ρη junction 107 First n-type base electrode 107a Forming the first n-type base electrode Area 108 The second n-type base electrode 108a forms the area of the second n-type base electrode 109 P-type ohmic electrode 30 1 Sapphire substrate 302 Buffer layer-21- This paper size applies to China National Standard (CNS) A4 specification (210X297mm) (Li) ---------: Install -------- Order (Please read the notes on the back before filling this page) A7 466783 B7 V. Description of Invention U. ) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperative 303 n-type lower cover layer 304 light-emitting layer 305 P-type upper cover layer 306 P-type base electrode 307 P-type ohmic electrode 308 n-type base electrode 309 current blocking layer 501 502 Buffer layer 503 η-type lower cladding layer 504 Light-emitting layer 505 P-type upper cladding layer 5 0 5 a Surface of P-type upper cladding layer 506 η-type gallium nitride layer 5 0 6 a ρη junction 507 nickel oxide film 508 ITO film 509 2nd n-type base electrode 5 0 9 a Area forming the second n-type base electrode 5 0 9 -1 lower part of the electrode 5 0 9 -2 upper part of the electrode 5 10 ρ-type ohmic electrode 5 11 first η-type base electrode 5 11a The area forming the first η-type base electrode C The center point of the planar shape of the LED-22-(Please read the precautions on the back before filling this page) This paper size applies to Chinese National Standard (CNS) A4 specifications (210X297 mm)