JP2001068729A - Led array - Google Patents

Led array

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Publication number
JP2001068729A
JP2001068729A JP24404399A JP24404399A JP2001068729A JP 2001068729 A JP2001068729 A JP 2001068729A JP 24404399 A JP24404399 A JP 24404399A JP 24404399 A JP24404399 A JP 24404399A JP 2001068729 A JP2001068729 A JP 2001068729A
Authority
JP
Japan
Prior art keywords
light emitting
layer
emitting devices
led array
respective light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24404399A
Other languages
Japanese (ja)
Inventor
Genichi Ogawa
元一 小川
Hisashi Sakai
久 坂井
Kota Nishimura
剛太 西村
Shigeo Aono
重雄 青野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP24404399A priority Critical patent/JP2001068729A/en
Publication of JP2001068729A publication Critical patent/JP2001068729A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To resolve the variation of the illuminant intensities of respective light emitting devices caused by the variation of their sizes and resolve the difficulty of their electrical isolation from each other, by forming an oxidized AlGaAs layer on a buffer layer of each light emitting device. SOLUTION: An AlxGa1-xAs (0.9<=x<=1) layer 3 has its thickness of 50 to 5000 Å and exhibits its resisitivity not smaller than 1×105 Ωcm by its wet oxidation to make largely improvable the insulating quality of respective light emitting devices from each other. Also, since the respective light emitting devices are insulated electrically from each other by their wet-oxidized AlxGa1-xAs (0.9<=x<=1) layer 3 of 50 to 5000 Å in their thickness, the etching depth for isolating electrically the respective light emitting devices from each other can be made shallow to make reducible largely the variation of the sizes of the respective light emitting devices. As a result, the variation of the illuminant intensities of the respective light emitting devices are reduced largely to make improvable the manufacturing yield of an LED array and its printing quality when applying it to the exposure source of a printer, etc.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はLEDアレイに関
し、特に電子写真プロセスの露光源として用いられるL
EDアレイに関する。
[0001] 1. Field of the Invention [0002] The present invention relates to an LED array, and more particularly to an LED array used as an exposure source in an electrophotographic process.
For ED arrays.

【0002】[0002]

【従来の技術】シリコン基板上にGaAs、AlGaA
s、InGaP、InGaAs、InGaAsP、Ga
AsPなどの化合物半導体をエピタキシャル成長し、L
EDアレイを構成する際の従来の製造工程とその構造は
以下の通りである。
2. Description of the Related Art GaAs and AlGaAs are formed on a silicon substrate.
s, InGaP, InGaAs, InGaAsP, Ga
Epitaxially growing a compound semiconductor such as AsP
The conventional manufacturing process and its structure when configuring an ED array are as follows.

【0003】まず、LEDアレイの平面図を図3(b)
に示し、図3(b)のB−’B断面図を図3(a)に示
す。図3中、1は1×103 〜104 Ωcmの比抵抗を
もつシリコン基板、2は第一の導電性をもつ化合物半導
体から成るバッファ層、4は第一の導電性をもつ化合物
半導体から成る発光層、5は第二の導電性をもつ化合物
半導体から成る発光層、6はSiO2 、SiNx などか
ら成る絶縁層、7は第一の導電性をもつ化合物半導体か
ら成る発光層4の一部とオーミック接続された個別電
極、8は第二の導電性をもつ化合物半導体から成る発光
層の一部とオーミック接続された第一の共通電極、9は
第二の導電性をもつ化合物半導体から成る発光層5の一
部とオーミック接続された第二の共通電極である。
First, a plan view of an LED array is shown in FIG.
FIG. 3A is a cross-sectional view taken along the line B-′B in FIG. In FIG. 3, 1 is a silicon substrate having a specific resistance of 1 × 10 3 to 10 4 Ωcm, 2 is a buffer layer made of a compound semiconductor having a first conductivity, and 4 is a buffer layer made of a compound semiconductor having a first conductivity. 5 is a light emitting layer made of a compound semiconductor having a second conductivity, 6 is an insulating layer made of SiO 2 , SiN x, etc., 7 is a light emitting layer 4 made of a compound semiconductor having a first conductivity. An individual electrode that is ohmic-connected to a portion thereof; 8 is a first common electrode that is ohmic-connected to a portion of a light emitting layer made of a compound semiconductor having a second conductivity; 9 is a compound semiconductor that has a second conductivity Is a second common electrode that is ohmic-connected to a part of the light emitting layer 5 made of.

【0004】次に、従来のLEDアレイの製造方法の一
例を図4を用いて具体的に説明する。まず、図4(a)
に示すように、MOCVD法やMBE法で、シリコン基
板1上にGaAs、AlGaAs、InGaP、InG
aAs、InGaAsP、GaAsPなどの化合物半導
体から成るバッファ層2を通常の二段階成長法で、でき
るだけ高抵抗になるように成長し、その後、キャリア密
度として1×1017〜1×1018atoms・cm-3
n型発光層4と、キャリア密度として1×1017〜1×
1019atoms・cm-3のp型発光層5を成長した基
板を用いる。
Next, an example of a conventional method for manufacturing an LED array will be specifically described with reference to FIG. First, FIG.
As shown in FIG. 1, GaAs, AlGaAs, InGaP, InG
A buffer layer 2 made of a compound semiconductor such as aAs, InGaAsP, or GaAsP is grown by a normal two-step growth method so as to have as high a resistance as possible, and then has a carrier density of 1 × 10 17 to 1 × 10 18 atoms · cm. -3 n-type light-emitting layer 4 and a carrier density of 1 × 10 17 to 1 ×
A substrate on which a p-type light emitting layer 5 of 10 19 atoms · cm −3 is grown is used.

【0005】なお、p型発光層5上に、さらにGaA
s、InGaP、InGaAs、InGaAsP、ある
いはGaAsPなどでキャリア密度として1×1019
toms・cm-3以上のp型コンタクト層(不図示)を
設けてもよい。
Note that GaAs is further formed on the p-type light emitting layer 5.
s, InGaP, InGaAs, InGaAsP, or GaAsP as a carrier density of 1 × 10 19 a
A p-type contact layer (not shown) of not less than toms · cm −3 may be provided.

【0006】その後、図4(b)に示すように、発光部
を形成するために、その他の部分を通常のフォトリソグ
ラフィの後、硫酸(H2 SO4 )と過酸化水素水(H2
2)系の混合エッチング液により除去する。この際、
各発光部間を電気的に分離するために、弗化アンモニウ
ム(NH4 F)と過酸化水素水(H2 2 )の混合液で
シリコン基板1を0.1μm〜0.5μmエッチングす
る。これは、バッファ層2をエピタキシャル成長させる
際に、AsやPがシリコン基板1に拡散してn型の導電
性を呈するようになるため、各発光部をバッファ層2も
含めて電気的に分離するために必要となる。
Thereafter, as shown in FIG. 4B, in order to form a light emitting portion, the other portions are subjected to ordinary photolithography, and then sulfuric acid (H 2 SO 4 ) and a hydrogen peroxide solution (H 2 H 2 O).
It is removed with an O 2 ) -based mixed etchant. On this occasion,
In order to electrically separate the light emitting portions from each other, the silicon substrate 1 is etched with a mixed solution of ammonium fluoride (NH 4 F) and aqueous hydrogen peroxide (H 2 O 2 ) in a range of 0.1 μm to 0.5 μm. This is because when the buffer layer 2 is epitaxially grown, As and P diffuse into the silicon substrate 1 and exhibit n-type conductivity, so that each light emitting portion is electrically separated including the buffer layer 2. It is necessary for

【0007】次に、図4(c)に示すように、n型発光
層4の一部を露出させるため、フォトリソグラフィとエ
ッチングにより、p型発光層5の一部とn型発光層4の
一部を除去する。
Next, as shown in FIG. 4C, in order to expose a part of the n-type light emitting layer 4, a part of the p-type light emitting layer 5 and the n-type light emitting layer 4 are etched by photolithography and etching. Remove some.

【0008】次に、図4(d)に示すように、プラズマ
CVDやスパッタリングなどでSiO2 、SiNx など
から成る絶縁層6を形成する。
Next, as shown in FIG. 4D, an insulating layer 6 made of SiO 2 , SiN x or the like is formed by plasma CVD or sputtering.

【0009】次に、図4(e)に示すように、フォトリ
ソグラフィとHF系エッチャントによるエッチングで個
別電極7、第一の共通電極8、および第二の共通電極9
とn型発光層4およびp型発光層5をオーミック接触さ
せるための窓6’、6’’を形成する次に、図4(f)
に示すように、Cr/Auの積層膜を真空蒸着法で形成
して、フォトリソグラフィとリフトオフ法により、個別
電極7、第一の共通電極8、および第二の共通電極9を
形成する。
Next, as shown in FIG. 4E, the individual electrode 7, the first common electrode 8, and the second common electrode 9 are formed by photolithography and etching using an HF-based etchant.
Windows 6 ′ and 6 ″ for bringing the n-type light-emitting layer 4 and the p-type light-emitting layer 5 into ohmic contact are formed next to FIG.
As shown in FIG. 5, a laminated film of Cr / Au is formed by a vacuum deposition method, and an individual electrode 7, a first common electrode 8, and a second common electrode 9 are formed by photolithography and a lift-off method.

【0010】その後、水素ガスや窒素ガス雰囲気で、約
250〜450℃で約2〜20分間アニールすることで
個別電極7、第一の共通電極8、および第二の共通電極
9とn型発光層4およびp型発光層5がオーミック接触
させ、LEDアレイを形成していた。
Thereafter, the individual electrodes 7, the first common electrode 8, and the second common electrode 9 are annealed in a hydrogen gas or nitrogen gas atmosphere at a temperature of about 250 to 450 ° C. for about 2 to 20 minutes. The layer 4 and the p-type light-emitting layer 5 were brought into ohmic contact to form an LED array.

【0011】[0011]

【発明が解決しようとする課題】しかしながら、上記従
来技術のようにシリコン基板1上に形成したLEDアレ
イでは、図3(a)に示すように、各発光部を電気的に
分離するために、発光部以外のすべての化合物半導体層
2、3、4とシリコン基板1を0.1μm〜0.5μm
エッチングする必要があり、発光体サイズのばらつきが
大きかった。これにより、各発光体の発光強度ばらつき
も大きく、素子の製造歩留りと電子写真方式のプリンタ
ーなどに応用した時の印画品質を低下させていた。すな
わち、発光体サイズがばらつくとPN接合部もばらつ
く。発光強度は、発光部のPN接合の面積に比例するた
め、面積が減少すると発光に寄与する電子と正孔が再結
合する面積が減少するのである。
However, in the LED array formed on the silicon substrate 1 as in the above-mentioned prior art, as shown in FIG. All the compound semiconductor layers 2, 3, and 4 and the silicon substrate 1 except for the light emitting section are 0.1 μm to 0.5 μm.
Etching had to be performed, and the variation in the size of the luminous body was large. As a result, the luminous intensity of each luminous body varies greatly, and the production yield of the device and the printing quality when applied to an electrophotographic printer or the like are reduced. That is, when the size of the light emitting body varies, the PN junction also varies. Since the light emission intensity is proportional to the area of the PN junction of the light emitting portion, when the area decreases, the area where electrons and holes contributing to light emission recombine decreases.

【0012】また、GaAs、AlGaAs、InGa
Pはゲルマニウムと格子定数がほぼ一致するため、これ
らをシリコン基板1にエピタキシャル成長した場合に比
べて、転位密度を1/10以下に低減することができ、
LEDの発光強度を数倍以上改善することができる。と
ころが、ゲルマニウム基板の比抵抗は100Ωcm以下
であるため、各発光部を電気的に分離することができな
いという問題があった。
Also, GaAs, AlGaAs, InGa
Since P has substantially the same lattice constant as germanium, the dislocation density can be reduced to 1/10 or less as compared with the case where P is epitaxially grown on the silicon substrate 1.
The emission intensity of the LED can be improved several times or more. However, since the specific resistance of the germanium substrate is 100 Ωcm or less, there is a problem that each light emitting unit cannot be electrically separated.

【0013】本発明はこのような従来技術の問題点に鑑
みてなされたものであり、発光体サイズのばらつきに起
因する発光強度のばらつきと、各発光部の電気的分離の
困難性を解消したLEDアレイを提供することを目的と
する。
The present invention has been made in view of such problems of the prior art, and has solved the problem of variations in emission intensity due to variations in the size of the luminous bodies and the difficulty of electrical isolation of each luminous portion. An object is to provide an LED array.

【0014】[0014]

【課題を解決するための手段】上記目的を達成するため
に、請求項1に係るLEDアレイでは、半導体単結晶基
板上に化合物半導体から成るバッファ層と発光層とを設
けたLEDアレイにおいて、前記バッファ層上に酸化し
たAlx Ga1-x As(0.9≦x≦1)層を設けたこ
とを特徴とする。
According to a first aspect of the present invention, there is provided an LED array having a buffer layer made of a compound semiconductor and a light emitting layer provided on a semiconductor single crystal substrate. An oxidized Al x Ga 1 -x As (0.9 ≦ x ≦ 1) layer is provided on the buffer layer.

【0015】上記LEDアレイでは、前記酸化したAl
x Ga1-x As(0.9≦x≦1)層が50Å〜500
0Åの厚みを有することが望ましい。
In the above LED array, the oxidized Al
x Ga 1-x As (0.9 ≦ x ≦ 1) layer is 50 ° to 500
It is desirable to have a thickness of 0 °.

【0016】上記LEDアレイでは、前記半導体単結晶
基板がシリコンまたはゲルマニウムであることが望まし
い。
In the above-mentioned LED array, it is desirable that the semiconductor single crystal substrate is made of silicon or germanium.

【0017】[0017]

【発明の実施の形態】以下、本発明の実施形態を示す。
本発明に係るLEDアレイの平面図を図1(b)に、図
1(b)のA−’Aの断面図を図1(a)に示す。図1
(a)において、1は半導体単結晶基板、2はバッファ
層、3はAlx Ga1-x As(0.9≦x≦1)層、4
はn型発光層、5はp型発光層、6は絶縁層、7は個別
電極、8は第一の共通電極、9は第二の共通電極であ
る。
Embodiments of the present invention will be described below.
FIG. 1B is a plan view of the LED array according to the present invention, and FIG. 1A is a cross-sectional view taken along line A-′A of FIG. 1B. FIG.
In (a), 1 is a semiconductor single crystal substrate, 2 is a buffer layer, 3 is an Al x Ga 1 -x As (0.9 ≦ x ≦ 1) layer,
Denotes an n-type light emitting layer, 5 denotes a p-type light emitting layer, 6 denotes an insulating layer, 7 denotes an individual electrode, 8 denotes a first common electrode, and 9 denotes a second common electrode.

【0018】半導体基板1は、シリコンまたはゲルマニ
ウムなどから成る。量産性の点からはシリコンが望まし
く、化合物半導体層との格子定数の整合性の点からはゲ
ルマニウムが望ましい。
The semiconductor substrate 1 is made of silicon, germanium or the like. Silicon is desirable in terms of mass productivity, and germanium is desirable in terms of matching lattice constant with the compound semiconductor layer.

【0019】バッファ層2は、GaAs、AlGaA
s、InGaP、InGaAs、InGaAsP、Ga
AsPなどの化合物半導体から成り、0.2〜2μmの
膜厚を有する。1×104 Ωcm以上のように、できる
だけ高抵抗になるように成長する。
The buffer layer 2 is made of GaAs, AlGaAs
s, InGaP, InGaAs, InGaAsP, Ga
It is made of a compound semiconductor such as AsP and has a thickness of 0.2 to 2 μm. It is grown to have as high a resistance as possible, such as 1 × 10 4 Ωcm or more.

【0020】Alx Ga1-x As(0.9≦x≦1)層
3は、50Å〜5000Åの厚みを有し、後述するウエ
ット酸化により、1×105 Ωcm以上の比抵抗を示
し、各発光体間の絶縁性を大幅に向上させることができ
る。また、各発光素子はウエット酸化された50Å〜5
000ÅのAlx Ga1-x As(0.9≦x≦1)層3
で電気的に絶縁されているため、各発光体を電気的に分
離するためのエッチングの深さを浅くでき、発光体サイ
ズのばらつきを大幅に改善することができる。n型発光
層4はGaAs、AlGaAs、InGaP、InGa
As、InGaAsP、GaAsPなどの化合物半導体
から成り、0.2〜5μm程度の厚みを有する。このn
型発光層4は、5×1016〜1×1018atoms・c
-3程度の電子密度を有する。なお、キャリア密度、膜
厚、組成は所望とするLEDの発光強度、発光波長など
により適宜選択される。
The Al x Ga 1 -x As (0.9 ≦ x ≦ 1) layer 3 has a thickness of 50 ° to 5000 ° and exhibits a specific resistance of 1 × 10 5 Ωcm or more due to wet oxidation described later; It is possible to greatly improve the insulation between the light-emitting members. In addition, each light emitting element is wet-oxidized at 50 ° to 5 °.
Al x Ga 1-x As (0.9 ≦ x ≦ 1) layer 3 of 000 °
Therefore, the depth of the etching for electrically isolating the light emitters can be reduced, and the variation in the size of the light emitters can be greatly improved. The n-type light emitting layer 4 is made of GaAs, AlGaAs, InGaP, InGa
It is made of a compound semiconductor such as As, InGaAsP, or GaAsP, and has a thickness of about 0.2 to 5 μm. This n
The type light emitting layer 4 has a size of 5 × 10 16 to 1 × 10 18 atoms · c.
It has an electron density of about m -3 . Note that the carrier density, film thickness, and composition are appropriately selected depending on the desired light emission intensity and light emission wavelength of the LED.

【0021】p型発光層5はGaAs、AlGaAs、
InGaP、InGaAs、InGaAsP、GaAs
Pなどの化合物半導体から成り、0.2〜5μm程度の
厚みを有する。このp型発光層5は、5×1016〜1×
1019atoms・cm-3程度の電子密度を有する。な
お、キャリア密度、膜厚、組成は所望とするLEDの発
光強度、発光波長などにより適宜選択される。
The p-type light emitting layer 5 is made of GaAs, AlGaAs,
InGaP, InGaAs, InGaAsP, GaAs
It is made of a compound semiconductor such as P and has a thickness of about 0.2 to 5 μm. The p-type light emitting layer 5 has a size of 5 × 10 16 to 1 ×
It has an electron density of about 10 19 atoms · cm −3 . Note that the carrier density, film thickness, and composition are appropriately selected depending on the desired light emission intensity and light emission wavelength of the LED.

【0022】また、必要に応じて、オーミック抵抗を低
減させるために、p型発光層5の上にキャリア密度とし
て5×1017〜2×1019 atoms・cm-3のコン
タクト層となるp型の導電性を示す100〜2000Å
程度の厚みを有するGaAs、InGaP、InGaA
s、InGaAsP、GaAsPなどの化合物半導体層
を設けてもよい。絶縁層6は、SiO2 、SiNx など
から成る。
If necessary, a p-type contact layer having a carrier density of 5 × 10 17 to 2 × 10 19 atoms · cm -3 is formed on the p-type light emitting layer 5 in order to reduce the ohmic resistance. 100-2000Å showing conductivity of
GaAs, InGaP, InGaAs having a thickness of about
A compound semiconductor layer such as s, InGaAsP, or GaAsP may be provided. The insulating layer 6 is made of SiO 2 , SiN x or the like.

【0023】n型発光層4には、個別電極7が接続して
設けられ、p型発光層5には第一の共通電極8と第二の
共通電極9が接続して設けられる。このように、個別電
極7と共通電極8、9とを発光層4、5が形成された単
結晶半導体基板1の同じ側に形成すると、外部回路との
接続が容易になる。また、共通電極8、9を複数設ける
ことで、個別電極7の数を減少させることができる。
The n-type light emitting layer 4 is provided with an individual electrode 7 connected thereto, and the p-type light emitting layer 5 is provided with a first common electrode 8 and a second common electrode 9 connected thereto. As described above, when the individual electrode 7 and the common electrodes 8 and 9 are formed on the same side of the single crystal semiconductor substrate 1 on which the light emitting layers 4 and 5 are formed, connection with an external circuit becomes easy. Further, by providing a plurality of common electrodes 8 and 9, the number of individual electrodes 7 can be reduced.

【0024】次に、上記LEDアレイの製造方法を説明
する。図2(a)に示すように、MOCVD法やMBE
法で、シリコン基板1上に通常の2段階成長法を用い
て、バッファ層2を0.2〜2μmの膜厚に形成する。
Next, a method for manufacturing the LED array will be described. As shown in FIG. 2A, MOCVD or MBE
The buffer layer 2 is formed to a thickness of 0.2 to 2 μm on the silicon substrate 1 by a normal two-stage growth method.

【0025】次に、50〜5000ÅのAlx Ga1-x
As(0.9≦x≦1)層3を成長した後、n型発光層
4とp型発光層5を0.2〜5μmの膜厚に形成する。
Next, Al x Ga 1 -x of 50 to 5000 °
After growing the As (0.9 ≦ x ≦ 1) layer 3, the n-type light-emitting layer 4 and the p-type light-emitting layer 5 are formed to a thickness of 0.2 to 5 μm.

【0026】また、必要に応じて、コンタクト層となる
p型の導電性を示す化合物半導体層(不図示)を100
〜2000Å成長させてもよい。
If necessary, a p-type conductive compound semiconductor layer (not shown) serving as a contact layer may be
Å2000 may be grown.

【0027】その後、図2(b)に示すように、発光部
を形成するために、その他の部分を通常のフォトリソグ
ラフィの後、硫酸(H2 SO4 )と過酸化水素水(H2
2)系の混合エッチング液により除去する。この際、
後述するウェット酸化のために、発光部以外のAlx
1-x As(0.9≦x≦1)層3’を完全に除去する
まで、エッチングを行う。
Then, as shown in FIG. 2B, in order to form a light emitting portion, the other portions are subjected to ordinary photolithography, and then sulfuric acid (H 2 SO 4 ) and a hydrogen peroxide solution (H 2
It is removed with an O 2 ) -based mixed etchant. On this occasion,
For wet oxidation to be described later, Al x G
Etching is performed until the a 1-x As (0.9 ≦ x ≦ 1) layer 3 ′ is completely removed.

【0028】その後、図2(c)に示すように、50〜
5000ÅのAlx Ga1-x As(0.9≦x≦1)層
3のウエット酸化をおこなう。まず、図2(b)の試料
を石英チューブの加熱炉に入れる。その後、90℃前後
の恒温槽中の超純水に窒素を1〜10リットル/分バブ
リングすることで超純水の蒸気を石英チューブ内に供給
し、400〜500℃に加熱し、1〜10時間酸化する
ことで、図2(c)に示す、Alx Ga1-x As(0.
9≦x≦1)層3’の酸化層3を得る。なお、酸化に必
要な時間と温度は、Alx Ga1-x As(0.9≦x≦
1)層3’の膜厚、Al組成x、発光体サイズにより異
なる。
Thereafter, as shown in FIG.
Wet oxidation of the Al x Ga 1-x As (0.9 ≦ x ≦ 1) layer 3 at 5000 ° is performed. First, the sample shown in FIG. 2B is placed in a quartz tube heating furnace. Then, the ultrapure water in a thermostat at about 90 ° C. is bubbled with nitrogen at a rate of 1 to 10 liters / min to supply the vapor of the ultrapure water into the quartz tube and heated to 400 to 500 ° C. By oxidizing for a time, Al x Ga 1 -x As (0.
9 ≦ x ≦ 1) The oxide layer 3 of the layer 3 ′ is obtained. The time and temperature required for the oxidation are Al x Ga 1 -x As (0.9 ≦ x ≦
1) It depends on the thickness of the layer 3 ', the Al composition x, and the size of the light emitting body.

【0029】図1(b)で発光体サイズを定義し、L1
+L2 を30μm、Wを20μmとする。この場合、A
lAs層3の膜厚が100Åであれば、400℃、30
分のウエット酸化で、AlAs層3の酸化が完了する。
また、Alx Ga1-x As(0.9≦x≦1)層3の膜
厚が50Å未満の場合や、Al組成xが0.9未満の場
合、酸化時間が長時間となり、実用的でない。Alx
1-x As(0.9≦x≦1)層3の膜厚が5000Å
を超える場合は、その上の発光層4と5の結晶性が劣化
し、LEDの発光強度が著しく低下する。
In FIG. 1B, the size of the luminous body is defined and L 1
+ L 2 is 30 μm, and W is 20 μm. In this case, A
If the thickness of the lAs layer 3 is 100 °, 400 ° C., 30 ° C.
Oxidation of the AlAs layer 3 is completed by a minute wet oxidation.
Further, when the thickness of the Al x Ga 1 -x As (0.9 ≦ x ≦ 1) layer 3 is less than 50 ° or when the Al composition x is less than 0.9, the oxidation time becomes long and the practical use becomes difficult. Not. Al x G
a 1-x As (0.9 ≦ x ≦ 1) layer 3 has a thickness of 5000 °
In the case of exceeding, the crystallinity of the light emitting layers 4 and 5 thereon is deteriorated, and the light emission intensity of the LED is significantly reduced.

【0030】次に、図2(d)に示すように、n型発光
層4の一部を露出させるため、フォトリソグラフィとエ
ッチングにより、p型発光層5の一部とn型発光層4の
一部を除去する。
Next, as shown in FIG. 2D, in order to expose a part of the n-type light-emitting layer 4, a part of the p-type light-emitting layer 5 and the n-type light-emitting layer 4 are etched by photolithography and etching. Remove some.

【0031】次に、図2(e)に示すように、プラズマ
CVDやスパッタリングなどでSiO2 、SiNx など
から成る絶縁層6を形成する。
Next, as shown in FIG. 2E, an insulating layer 6 made of SiO 2 , SiN x or the like is formed by plasma CVD or sputtering.

【0032】次に、図2(f)に示すように、フォトリ
ソグラフィとHF系エッチャントによるエッチングで個
別電極7、第一の共通電極8、第二の共通電極9とn型
発光層4、p型発光層5がオーミック接触させるための
窓6’、6’’を形成する次に、図2(g)に示すよう
に、Cr/Auの積層膜を真空蒸着で形成して、フォト
リソグラフィとリフトオフ法により、個別電極7、第一
の共通電極8、第二の共通電極9を形成する。
Next, as shown in FIG. 2 (f), the individual electrode 7, the first common electrode 8, the second common electrode 9 and the n-type light emitting layer 4, p and p are formed by photolithography and etching with an HF-based etchant. Next, as shown in FIG. 2 (g), a Cr / Au laminated film is formed by vacuum evaporation to form windows 6 ′ and 6 ″ for the mold light emitting layer 5 to make ohmic contact. The individual electrode 7, the first common electrode 8, and the second common electrode 9 are formed by a lift-off method.

【0033】その後、水素ガスや窒素ガス雰囲気で、約
250〜450℃で約2〜20分間アニールすることで
個別電極7、第一の共通電極8、第二の共通電極9とn
型発光層4、p型発光層5をオーミック接触させ、LE
Dアレイを形成する。
Thereafter, annealing is performed at about 250 to 450 ° C. for about 2 to 20 minutes in an atmosphere of hydrogen gas or nitrogen gas, so that the individual electrode 7, the first common electrode 8, the second common electrode 9,
Type light-emitting layer 4 and p-type light-emitting layer 5 are brought into ohmic contact, LE
Form a D array.

【0034】[0034]

【発明の効果】以上のように、本発明のLEDアレイで
は、各発光素子をAlx Ga1-x As(0.9≦x≦
1)層の酸化膜により、半導体単結晶基板と電気的に絶
縁できるため、発光部の分離エッチングの深さを浅くで
き、発光体サイズのばらつきを大幅に低減することがで
きる。これにより、各発光体の発光強度のばらつきは大
幅に改善し、LEDアレイの製造歩留りとプリンターな
どの露光源に応用したときの印画品質を向上させること
ができる。
As described above, in the LED array of the present invention, each light emitting element is formed of Al x Ga 1 -x As (0.9 ≦ x ≦
1) Since the oxide film of the layer can be electrically insulated from the semiconductor single crystal substrate, the depth of the separation etching of the light emitting portion can be reduced, and the variation in the size of the light emitter can be greatly reduced. As a result, the variation in the luminous intensity of each luminous body is greatly improved, and the production yield of the LED array and the printing quality when applied to an exposure source such as a printer can be improved.

【0035】また、本発明のLEDアレイでは、半導体
単結晶基板として機械的強度の優れた4インチ以上の大
口径シリコン基板またはゲルマニウム基板を用いること
ができ、GaAs、AlGaAs、InGaP、InG
aAs、InGaAsP、あるいはGaAsPなどの化
合物半導体をエピタキシャル成長し、LEDアレイを構
成できるため、基板の割れに起因する製造歩留まりの低
下を大幅に改善できる。
Further, in the LED array of the present invention, a large-diameter silicon substrate or a germanium substrate of 4 inches or more having excellent mechanical strength can be used as a semiconductor single crystal substrate, and GaAs, AlGaAs, InGaP, InG
Since an LED array can be formed by epitaxially growing a compound semiconductor such as aAs, InGaAsP, or GaAsP, a reduction in manufacturing yield due to cracks in the substrate can be significantly improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)は本発明のLEDアレイの断面図、
(b)は本発明のLEDアレイの平面図である。
FIG. 1A is a sectional view of an LED array according to the present invention,
(B) is a plan view of the LED array of the present invention.

【図2】本発明のLEDアレイの製造プロセスを示す断
面図である。
FIG. 2 is a sectional view showing a manufacturing process of the LED array of the present invention.

【図3】(a)は従来例のLEDアレイの断面図、
(b)は従来例のLEDアレイの平面図である。
FIG. 3A is a cross-sectional view of a conventional LED array.
(B) is a plan view of a conventional LED array.

【図4】従来例のLEDアレイの製造プロセスを示す断
面図である。
FIG. 4 is a cross-sectional view showing a manufacturing process of a conventional LED array.

【符号の説明】[Explanation of symbols]

1‥‥‥半導体単結晶基板、2‥‥‥バッファ層、3‥
‥‥Alx Ga1-x As(0.9≦x≦1)層、4‥‥
‥n型発光層、5‥‥‥p型発光層、6‥‥‥絶縁層、
7‥‥‥個別電極、8‥‥‥第一の共通電極、9‥‥‥
第二の共通電極
1 semiconductor single crystal substrate, 2 buffer layer, 3
{ Al x Ga 1-x As (0.9 ≦ x ≦ 1) layer, 4}
{N-type light-emitting layer, 5p-type light-emitting layer, 6} insulating layer,
7 ‥‥‥ individual electrode, 8 ‥‥‥ first common electrode, 9 ‥‥‥
Second common electrode

フロントページの続き (72)発明者 青野 重雄 京都府相楽郡精華町光台3丁目5番地 京 セラ株式会社中央研究所内 Fターム(参考) 2C162 AE05 AE21 AE28 AE47 FA04 FA17 FA23 5F041 AA05 CA33 CA35 CA36 CA37 CA38 CA39 CA77 CB23 FF13Continued on the front page (72) Inventor Shigeo Aono 3-5 Koikadai, Seika-cho, Soraku-gun, Kyoto F-term in Central Research Laboratory, Kyocera Corporation 2C162 AE05 AE21 AE28 AE47 FA04 FA17 FA23 5F041 AA05 CA33 CA35 CA36 CA37 CA38 CA39 CA77 CB23 FF13

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 半導体単結晶基板上に化合物半導体から
成るバッファ層と発光層とを設けたLEDアレイにおい
て、前記バッファ層上に酸化したAlx Ga1-x As
(0.9≦x≦1)層を設けたことを特徴とするLED
アレイ。
1. An LED array having a buffer layer made of a compound semiconductor and a light emitting layer provided on a semiconductor single crystal substrate, wherein an oxidized Al x Ga 1 -x As is formed on the buffer layer.
LED provided with (0.9 ≦ x ≦ 1) layer
array.
【請求項2】 前記酸化したAlx Ga1-x As(0.
9≦x≦1)層が50Å〜5000Åの厚みを有するこ
とを特徴とする請求項1に記載のLEDアレイ。
2. The oxidized Al x Ga 1 -x As (0.
The LED array according to claim 1, wherein 9 ≦ x ≦ 1) the layer has a thickness of 50 ° to 5000 °.
【請求項3】 前記半導体単結晶基板がシリコンである
ことを特徴とする請求項1に記載のLEDアレイ。
3. The LED array according to claim 1, wherein said semiconductor single crystal substrate is silicon.
【請求項4】 前記半導体単結晶基板がゲルマニウムで
あることを特徴とする請求項1に記載のLEDアレイ。
4. The LED array according to claim 1, wherein the semiconductor single crystal substrate is made of germanium.
JP24404399A 1999-08-30 1999-08-30 Led array Pending JP2001068729A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24404399A JP2001068729A (en) 1999-08-30 1999-08-30 Led array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24404399A JP2001068729A (en) 1999-08-30 1999-08-30 Led array

Publications (1)

Publication Number Publication Date
JP2001068729A true JP2001068729A (en) 2001-03-16

Family

ID=17112879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24404399A Pending JP2001068729A (en) 1999-08-30 1999-08-30 Led array

Country Status (1)

Country Link
JP (1) JP2001068729A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009238963A (en) * 2008-03-26 2009-10-15 Kyocera Corp Light-emitting diode chip and manufacturing method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0324722A (en) * 1989-06-21 1991-02-01 Mitsubishi Monsanto Chem Co In alloy forming method of algaas semiconductor and in alloy electrode
JPH08330632A (en) * 1995-05-29 1996-12-13 Kyocera Corp Light-emitting semiconductor device
JPH10135513A (en) * 1996-10-28 1998-05-22 Oki Electric Ind Co Ltd Semiconductor device and semiconductor element used in the device
JPH1146016A (en) * 1997-07-28 1999-02-16 Oki Electric Ind Co Ltd Semiconductor light-emitting device
JPH11220164A (en) * 1997-06-06 1999-08-10 Oki Electric Ind Co Ltd Light-emitting element array and light-emitting element
JP2000312027A (en) * 1999-04-27 2000-11-07 Oki Electric Ind Co Ltd Light-emitting diode array device and manufacture of the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0324722A (en) * 1989-06-21 1991-02-01 Mitsubishi Monsanto Chem Co In alloy forming method of algaas semiconductor and in alloy electrode
JPH08330632A (en) * 1995-05-29 1996-12-13 Kyocera Corp Light-emitting semiconductor device
JPH10135513A (en) * 1996-10-28 1998-05-22 Oki Electric Ind Co Ltd Semiconductor device and semiconductor element used in the device
JPH11220164A (en) * 1997-06-06 1999-08-10 Oki Electric Ind Co Ltd Light-emitting element array and light-emitting element
JPH1146016A (en) * 1997-07-28 1999-02-16 Oki Electric Ind Co Ltd Semiconductor light-emitting device
JP2000312027A (en) * 1999-04-27 2000-11-07 Oki Electric Ind Co Ltd Light-emitting diode array device and manufacture of the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009238963A (en) * 2008-03-26 2009-10-15 Kyocera Corp Light-emitting diode chip and manufacturing method thereof

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