JPH0324722A - In alloy forming method of algaas semiconductor and in alloy electrode - Google Patents
In alloy forming method of algaas semiconductor and in alloy electrodeInfo
- Publication number
- JPH0324722A JPH0324722A JP1159329A JP15932989A JPH0324722A JP H0324722 A JPH0324722 A JP H0324722A JP 1159329 A JP1159329 A JP 1159329A JP 15932989 A JP15932989 A JP 15932989A JP H0324722 A JPH0324722 A JP H0324722A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- alloy
- ohmic
- semiconductor
- contact resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910045601 alloy Inorganic materials 0.000 title claims abstract description 11
- 239000000956 alloy Substances 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 title claims description 8
- 229910000846 In alloy Inorganic materials 0.000 title claims 4
- 229910052737 gold Inorganic materials 0.000 claims abstract description 9
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 9
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract 2
- 239000013078 crystal Substances 0.000 claims description 11
- 238000005275 alloying Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 10
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 239000002019 doping agent Substances 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000036963 noncompetitive effect Effects 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＡＩＧａＡｓ基板における接触抵抗の低いオー
ミック性電極の形成方法及び形成した電極に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming an ohmic electrode with low contact resistance on an AIGaAs substrate, and to the formed electrode.
従来、高輝度発光用ＬＥＤとしてホモ接合構造ＬＥＤに
比べて、キャリアの注入効率が高く、高出力、高応答速
度が得られるシングルへテロ接合構造ＬＥＤ，あるいは
ダブルへテロ接合構造ＬＥＤが用いられている。Conventionally, single heterojunction structure LEDs or double heterojunction structure LEDs have been used as high-intensity light emitting LEDs, which have higher carrier injection efficiency, higher output, and higher response speed than homojunction structure LEDs. There is.
これらへテロ接合構造ＬＥＤに特徴的なことは、光取り
出し側にＡｊ！Ａｓ混晶比Ｘの大きいＡ１イＧａｐ−，
Ａｓが用いられている点である。例えば、赤色発光高輝
度ＬＥＤ用基板のエビタキシャル或長の例を示すと、ｐ
型ＧａＡｓ基板Ｃ（１００）面〕上にｐクラッド層とし
て液相或長法等によりＺｎドーブＡ ＩｌＧ． ７５Ｇ
ａ ＠． ２ＳＡ ｓ層を２００μｍ（ｐ型）形成し
た後、ｐアクティブ層としてＺｎドープＡ ｌ ｏ．
＊ｓＧ ａ ｏ． ｓｓＡ Ｓ層を１〜３μｍ（ｐ型）
形成し、次いでｎクラッド層としてＴｅドーブＡ Ｒ
０． ７５Ｇ ａ ｏ． ２ＳＡ Ｓ層を５０μｍ程度
形或している。モしてＧａＡｓ基板選択性エッチャント
を用いて光吸収性ＧａＡｓ基板を除去して高輝度ＬＥＤ
チップを得ており、チップの表面の混晶比Ｘは０．７５
と高い。The characteristic feature of these heterojunction structure LEDs is that Aj! A1 Gap-, with a large As mixed crystal ratio X,
This is because As is used. For example, to show an example of the epitaxial length of a red-emitting high-brightness LED substrate, p
Zn-doped A IlG. 75G
a@. After forming a 200 μm thick (p-type) 2SA s layer, a Zn-doped AlO.
*sG ao. ssA S layer 1 to 3 μm (p type)
and then Te dove A R as n-cladding layer.
0. 75G ao. The 2SAS layer has a thickness of about 50 μm. The light-absorbing GaAs substrate is removed using a GaAs substrate-selective etchant to produce high-brightness LEDs.
A chip is obtained, and the mixed crystal ratio X on the surface of the chip is 0.75.
That's high.
しかしながら、このようなＡｆＡｓ混晶比Ｘの大きなＡ
１ ｍ Ｇ ａ ｌ−ｗ＋ Ａ ｓ基板は大気中で酸
化されやすく、その酸化物は電流の流れづらい絶縁物で
あることから、その上に電極を形成するとＶｆ値（２０
ｍＡ流すのに必要な順方向電圧）が高くなり、低電圧で
は駆動不可能となる。However, when A with such a large AfAs mixed crystal ratio
1 m G a l-w+ A s The substrate is easily oxidized in the atmosphere, and the oxide is an insulator that makes it difficult for current to flow, so when an electrode is formed on it, the Vf value (20
The forward voltage required to flow mA becomes high, making it impossible to drive with a low voltage.
この場合表面の酸化物を完全に除去することが必要であ
るが、ＡＩｌＧａΔＳをエッチングすることができない
場合（例えば、Ａｊ！ＧａＡｓ薄膜等に電極を形或する
必要がある場合）には有効な手段がなかった。In this case, it is necessary to completely remove the oxide on the surface, but this is an effective method when it is not possible to etch the AllGaΔS (for example, when it is necessary to form an electrode on the Aj!GaAs thin film, etc.). There was no.
本発明は上記課題を解決するためのもので、酸化物の形
成された表面でもエッチング処理を施すことなく、低接
触抵抗のオーミツク電極が形或できる電極形戒方法及び
電極を提供することを目的とする。The present invention is intended to solve the above-mentioned problems, and aims to provide an electrode forming method and an electrode that can form an ohmic electrode with low contact resistance without etching even on a surface where an oxide is formed. shall be.
本発明は、Ａｊ７ＧａＡｓ基板のＡＪ！Ａｓ混晶比が０
≦ＡＪ！Ａｓ＜ ｌであり、Ｉｎに少なくともＰｔとＡ
ｕの両方を含んだ合金電極を形成することを特徴とする
。The present invention provides AJ! of Aj7GaAs substrate! As mixed crystal ratio is 0
≦AJ! As < l, and In contains at least Pt and A
It is characterized by forming an alloy electrode containing both u.
本発明は、第１図に示すようにＡＩｌＧａＡｓ半導体ｌ
の表面に、Ｉｎ２ａ，Ａｕ２ｂ，Ｐｔ２ｃをそれぞれ蒸
着する。この場合蒸着の順序はどのようであってもよく
、また、必要に応じてドーバントとしてｎ型のＡｌＧａ
Ａｓの場合にはＴｅ、Ｓｎ，ＳｂＳＳｉを最大で５％、
通常１〜３％添加し、ｐ型の場合にはＺｎ，Ｂｅをｌ〜
８％添加する。蒸着後、３８０℃〜６１０℃で１０分以
上加熱処理すると、第２図に示すようにＩｎ２ａが半導
体との界面に入り込んで合金化が生じ、低接触抵抗のオ
ーミックコンタクト３が形成される。The present invention, as shown in FIG.
In2a, Au2b, and Pt2c are deposited on the surface of the substrate. In this case, the order of vapor deposition may be arbitrary, and if necessary, n-type AlGa may be used as a dopant.
In the case of As, Te, Sn, SbSSi at a maximum of 5%,
Usually 1 to 3% is added, and in the case of p-type, Zn and Be are added to 1 to 3%.
Add 8%. After vapor deposition, when heat-treated at 380° C. to 610° C. for 10 minutes or more, In2a enters the interface with the semiconductor and alloys occur, forming an ohmic contact 3 with low contact resistance, as shown in FIG.
この場合、ＩｎはＰｔとＡｕの存在によって酸化ＡＩが
存在していても低接触抵抗が得られる。この、ＰｔとＡ
ｕは合金化した界面において、それぞれ５重量％以上で
あることが望ましい。また、ドーパントを添加すると、
これが拡散されることで表面のキャリア濃度を高め、オ
ーミック接触を得やすくすることができる。ただし、ド
ーバント単体ではＡｌＧａＡｓ中に拡敗せず、Ａｕおよ
びＰｔが存在することによってはじめて効果的に作用す
る。In this case, due to the presence of Pt and Au in In, low contact resistance can be obtained even in the presence of oxidized AI. This, Pt and A
It is desirable that u be 5% by weight or more at each alloyed interface. Also, when dopants are added,
This diffusion increases the carrier concentration on the surface, making it easier to obtain ohmic contact. However, dopant alone does not spread into AlGaAs, and only works effectively in the presence of Au and Pt.
なお、電極のアロイ温度は３８０℃〜６１０℃の温度範
囲で可能であるが、通常は表面の平坦性と再現性とから
５１０℃付近で行うのが望ましい。Note that the alloying temperature of the electrode can range from 380°C to 610°C, but it is usually desirable to perform the alloying at around 510°C from the viewpoint of surface flatness and reproducibility.
本発明は、混晶比が０≦Ａｊ！Ａｓ＜ １であるＡＩｌ
ＧａＡＳ基板に電極を形或する場合、ＩｎにＰｔとＡｕ
の両方を含ませて加熱することにより、良好な合金電極
を形成することができ、またドーパントを添加すること
によりキャリア濃度を高めて、より良好なオーミック接
触を得ることができ、Ａｊ！Ａｓ混晶比が高く、表面層
が酸化されていてもエッチング処理を施すことなく低接
触抵抗のオーミック電極を形成することができる。勿論
、本発明はＡｊ！Ａｓ混晶比が低い場合にも適用できる
ことは言うまでもない。In the present invention, the mixed crystal ratio is 0≦Aj! AIl with As<1
When forming electrodes on a GaAS substrate, In is combined with Pt and Au.
A good alloy electrode can be formed by adding both Aj! and heating, and by adding a dopant, the carrier concentration can be increased and better ohmic contact can be obtained. Even if the As mixed crystal ratio is high and the surface layer is oxidized, an ohmic electrode with low contact resistance can be formed without performing an etching process. Of course, the present invention is Aj! Needless to say, this method can also be applied when the As mixed crystal ratio is low.
〔実施例１］
Ａｊ！Ａｓ混晶比が０．７０、キャリア濃度１×ＩＱｌ
ｆｆＣ『３のｎ型ＡＩＧａＡｓ基板上にＴｅを添加して
Ｉｎ％Ｐｔ％Ａｕを蒸着し、窒素雰囲気中で５１０℃、
１５分間加熱処理し、
Ｉｎ： ５４重量％
Ｔｅ： １重量％
Ｐｔ： 約７重量％
Ａｕ： ３８・重量％
の組戊の合金を１１０μｍφの大きさで５００μｍ間隔
で形或し、オーミック性および接触抵抗を測定した。[Example 1] Aj! As mixed crystal ratio is 0.70, carrier concentration is 1×IQl
In%Pt%Au was vapor-deposited on an n-type AIGaAs substrate of ffC ``3'' with Te added, and heated at 510°C in a nitrogen atmosphere.
After heat treatment for 15 minutes, a composite alloy of In: 54% by weight, Te: 1% by weight, Pt: about 7% by weight, and Au: 38% by weight was formed into a shape with a size of 110 μmφ at 500 μm intervals to improve ohmic property and contact. Resistance was measured.
測定総数９６０中、非才一ミック性のものは０、才一ミ
ック性のものは９６０で１００％の才−ミック性が達成
され、平均の接触抵抗は２．６３Ｘ１０−４Ωｃｄであ
った。Out of a total of 960 measurements, 100% contact resistance was achieved with 0 for non-competitive contact and 960 for non-competitive contact, and the average contact resistance was 2.63 x 10 -4 Ωcd.
〔比較例１〕
実施例１と同様の条件で、
Ｉｎ： ９７重量％
Ｔｅ： ３重量％
の組或の合金を形成し、オーミック性および接触抵抗を
測定した。[Comparative Example 1] An alloy containing 97% by weight In and 3% by weight Te was formed under the same conditions as in Example 1, and its ohmic properties and contact resistance were measured.
測定総数２４５中非オーミック性のものは２４５、オー
ミック性のものは０で、オーミック性は０％、平均の接
触抵抗は３．４４Ｘ１０−’ΩｃｒＩ以上であった。Out of a total of 245 measurements, 245 were non-ohmic, 0 were ohmic, the ohmic was 0%, and the average contact resistance was 3.44×10 −′ΩcrI or more.
〔比較例２〕
実施例１と同様の条件で、
Ｉｎ： ９７重量％
Ｔｅ： ３重量％
の組或の合金を形威し、才−ミック性および接触抵抗を
測定した。[Comparative Example 2] Under the same conditions as in Example 1, an alloy containing 97% by weight of In and 3% by weight of Te was tested, and the mechanical strength and contact resistance were measured.
測定総数７６７中非オーミック性のものは４６６、才一
ミック性のものは３０１で、オーミック性は３９．２％
、平均の接触抵抗は１．５３Ｘ１０−ｌΩｄであった。Of the total number of measurements of 767, 466 were non-ohmic, 301 were unidirectional, and 39.2% were ohmic.
, the average contact resistance was 1.53×10 −1 Ωd.
以上のように本発明によれば、ＡＩＧａＡｓ半導体上に
Ｉｎに少なくともＰｔ，Ａｕを蒸着して合金化処理する
ことにより、Ａｊ！Ａｓ混晶比が高く、酸化ＡＩの形成
された表面でも低接触抵抗の合金電極を形成することが
でき、エッチング処理を施すことなく、低接触抵抗のオ
ーミック電極が得られる。As described above, according to the present invention, Aj! An alloy electrode with a high As mixed crystal ratio and low contact resistance can be formed even on a surface where oxidized AI is formed, and an ohmic electrode with low contact resistance can be obtained without performing an etching process.
第１図、第２図は本発明のＩｎ電極形或を説明するため
の図である。
ｌ・・・ＡｌＧａＡｓ半導体、２・・・電極、３・・・
才一ミックコンタクト。
出 願 人 三菱モンサント化成株式会社（外ｌ名
）FIGS. 1 and 2 are diagrams for explaining the In electrode type of the present invention. l...AlGaAs semiconductor, 2... electrode, 3...
Saiichi Mick contact. Applicant: Mitsubishi Monsanto Chemicals Co., Ltd. (external name)
Claims (3)
ｓ半導体上にＩｎ及び少なくともＰｔ、Ａｕを蒸着し、
合金化処理することを特徴とするＡｌＧａＡｓ半導体の
Ｉｎ合金形成方法。(1) AlGaA with an AlAs mixed crystal ratio of 0≦AlAs<1
s Vapor depositing In and at least Pt and Au on the semiconductor,
A method for forming an In alloy in an AlGaAs semiconductor, which comprises performing an alloying treatment.
Ａｓ＜１であり、該半導体上に形成され、Ｉｎに少なく
ともＰｔとＡｕの両方を含んだ合金からなるＡｌＧａＡ
ｓ半導体のＩｎ合金電極。(2) AlAs mixed crystal ratio of AlGaAs semiconductor is 0≦Al
As<1, AlGaA is formed on the semiconductor and is made of an alloy containing both Pt and Au in In.
s semiconductor In alloy electrode.
以上である請求項２記載のＩｎ合金電極。(3) The content of Pt and Au is 0.1 ppm each.
The In alloy electrode according to claim 2, which is the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15932989A JP2792674B2 (en) | 1989-06-21 | 1989-06-21 | Method for forming In alloy of GaAs semiconductor and In alloy electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15932989A JP2792674B2 (en) | 1989-06-21 | 1989-06-21 | Method for forming In alloy of GaAs semiconductor and In alloy electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0324722A true JPH0324722A (en) | 1991-02-01 |
| JP2792674B2 JP2792674B2 (en) | 1998-09-03 |
Family
ID=15691439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15932989A Expired - Fee Related JP2792674B2 (en) | 1989-06-21 | 1989-06-21 | Method for forming In alloy of GaAs semiconductor and In alloy electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2792674B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001068729A (en) * | 1999-08-30 | 2001-03-16 | Kyocera Corp | Led array |
-
1989
- 1989-06-21 JP JP15932989A patent/JP2792674B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001068729A (en) * | 1999-08-30 | 2001-03-16 | Kyocera Corp | Led array |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2792674B2 (en) | 1998-09-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3739951B2 (en) | Semiconductor light emitting device and manufacturing method thereof | |
| JP2953468B2 (en) | Compound semiconductor device and surface treatment method thereof | |
| JP2803741B2 (en) | Gallium nitride based compound semiconductor electrode forming method | |
| JP4023121B2 (en) | N-type electrode, group III nitride compound semiconductor device, method for manufacturing n-type electrode, and method for manufacturing group III nitride compound semiconductor device | |
| JPS5932055B2 (en) | Method for manufacturing a semiconductor device having contacts | |
| JP2005340860A (en) | Semiconductor light-emitting element | |
| JP3807020B2 (en) | Translucent electrode for light emitting semiconductor device and method for producing the same | |
| JP2907452B2 (en) | Electrodes for compound semiconductors | |
| JP3665243B2 (en) | Nitride semiconductor device and manufacturing method thereof | |
| JPH0324722A (en) | In alloy forming method of algaas semiconductor and in alloy electrode | |
| JP4281569B2 (en) | Method for manufacturing epitaxial wafer for semiconductor light emitting device | |
| JPS6143846B2 (en) | ||
| JPH10308533A (en) | Galium-nitride-based compound semiconductor light emitting element, its manufacture and light emitting element | |
| JP3309745B2 (en) | GaN-based compound semiconductor light emitting device and method of manufacturing the same | |
| JP2000101134A (en) | Nitride semiconductor element and manufacture thereof | |
| JPH03184377A (en) | Electrode for compound semiconductor | |
| JP3410166B2 (en) | Red light emitting diode element | |
| JP3267480B2 (en) | Method of manufacturing compound semiconductor and method of forming ohmic electrode of compound semiconductor | |
| JPS6220383A (en) | Compound semiconductor device | |
| JPH10256184A (en) | Electrode for p-type nitride semiconductor semiconductor element having electrode and fabrication thereof | |
| JP4572430B2 (en) | Method for forming ohmic electrode | |
| JP4142958B2 (en) | Metal oxide film forming method | |
| JP2827862B2 (en) | Ohmic electrode of compound semiconductor and method of forming the same | |
| CN1039681A (en) | Technology for preparing electrode of gallium phosphide led | |
| JPH10125655A (en) | Manufacture of iii-v compound semiconductor element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |