JP2001068614A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2001068614A
JP2001068614A JP24510299A JP24510299A JP2001068614A JP 2001068614 A JP2001068614 A JP 2001068614A JP 24510299 A JP24510299 A JP 24510299A JP 24510299 A JP24510299 A JP 24510299A JP 2001068614 A JP2001068614 A JP 2001068614A
Authority
JP
Japan
Prior art keywords
die pad
semiconductor chip
insulating layer
semiconductor device
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24510299A
Other languages
Japanese (ja)
Inventor
Masahiro Kimura
政広 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP24510299A priority Critical patent/JP2001068614A/en
Publication of JP2001068614A publication Critical patent/JP2001068614A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/4805—Shape
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent a contact of thin metal wire with semiconductor chip and the like, and leakage of bonding agent, possibly caused by increased semiconductor size and decreased package thickness. SOLUTION: A semiconductor chip 1 is firmly formed on a die pad 3 by bonding material 2 and a projecting part 9 having the same height as the height of the semiconductor chip 1 is formed on the peripheral area of the die pad 3 completely surrounding the semiconductor chip 1. An insulation layer 8 is formed on all over the projecting part 9. Each bonding pad 5 and the corresponding inner lead 6 are connected by thin metal wires 4. Therefore, the thin metal wire 4 sagging from the prescribed locus will not touch the semiconductor chip end 1E as supported by the insulation layer 8.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】この発明は、半導体チップの
大型化及びパッケージの薄型化に対応可能な半導体装置
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which can cope with an increase in the size of a semiconductor chip and a reduction in the thickness of a package.

【０００２】[0002]

【従来の技術】従来のモールド成形された半導体装置に
おいては、半導体チップをその上に積載するためのダ
イパッド部と隣り合うリード同士が互いに接触しない
ように所定間隔で配置されたインナーリードとが一体的
に形成されたリードフレームを使用しており、半導体チ
ップのダイボンディングと金属細線のワイヤボンディン
グとを順次に行った上で、リードフレーム及び半導体チ
ップを樹脂で封止し、その後、隣り合うインナーリード
同士を結合せしめているリードフレームの各タイバー部
を切断した上でアウターリードを折り曲げる作業を行っ
ている。2. Description of the Related Art In a conventional molded semiconductor device, a die pad portion for mounting a semiconductor chip thereon and inner leads arranged at predetermined intervals so that adjacent leads do not contact each other are integrated. After the die bonding of the semiconductor chip and the wire bonding of the fine metal wire are sequentially performed, the lead frame and the semiconductor chip are sealed with resin, and then the adjacent inner After cutting each tie bar part of the lead frame that connects the leads, the outer lead is bent.

【０００３】図６は、その様なリードフレームを用いた
製造方法によって製造された従来の半導体装置１０Ｐの
構成例を示す縦断面図であり、図７は、モールド成形前
の、従ってダイボンド工程及びワイヤボンド工程終了後
の半導体装置１０Ｐを示す上面図である。両図６、７に
示す通り、半導体チップ１Ｐは、半田や樹脂等により成
る接合材２Ｐによってダイパッド３Ｐの表面上に固設さ
れている。又、各インナーリード６Ｐは互いに接触しな
いように所定の間隔で配置されており、半導体チップ１
Ｐの表面上に形成されている各ボンディングパッド５Ｐ
と対応するインナーリード６Ｐの先端部６ＡＰとは、金
属細線４Ｐを用いたワイヤボンディングによって配線さ
れている。そして、同装置１０Ｐは、上記各部１Ｐ〜６
Ｐ（但し、インナーリード６Ｐについてはその一部だ
け）を包含するように、封止樹脂７Ｐによってモールド
成形されている。尚、ダイパッドの側面３ＳＳＰとイン
ナーリード６Ｐの先端面６ＥＰとの間隔ｄは、既述した
通り、半導体チップ１の大型化に伴って比較的狭まって
いる。FIG. 6 is a longitudinal sectional view showing a configuration example of a conventional semiconductor device 10P manufactured by a manufacturing method using such a lead frame, and FIG. 7 is a diagram showing a die bonding process and a die bonding process before molding. FIG. 14 is a top view showing the semiconductor device 10P after the wire bonding step is completed. As shown in FIGS. 6 and 7, the semiconductor chip 1P is fixed on the surface of the die pad 3P by a bonding material 2P made of solder, resin, or the like. The inner leads 6P are arranged at predetermined intervals so as not to contact each other.
Each bonding pad 5P formed on the surface of P
And the corresponding end portion 6AP of the inner lead 6P are wired by wire bonding using a thin metal wire 4P. The device 10P includes the above components 1P to 6
It is molded with the sealing resin 7P so as to include P (however, only a part of the inner lead 6P). Note that the distance d between the side surface 3SSP of the die pad and the tip end surface 6EP of the inner lead 6P is relatively narrowed as the size of the semiconductor chip 1 increases, as described above.

【０００４】[0004]

【発明が解決しようとする課題】近年、半導体チップは
集積化及び高密度化に伴って大型化する傾向にあり、し
かも、モールド成形された半導体装置自体が薄型化する
傾向も高まっている。そのため、従来のモールド成形に
よる半導体装置の構成を用いて大型化した半導体チップ
をリードフレームのダイパッド部に搭載するにあたって
は、以下の様な問題点（１）及び（２）が生じている。In recent years, semiconductor chips have tended to increase in size with increasing integration and density, and moreover, the tendency of the molded semiconductor device itself to become thinner. Therefore, the following problems (1) and (2) arise when mounting a semiconductor chip, which has been increased in size using the configuration of a semiconductor device formed by conventional molding, on a die pad portion of a lead frame.

【０００５】（１）一方でパッケージの薄型化に伴い、
金属細線の配線時の高さを高くすると、封止樹脂表面か
ら金属細線の一部が露出してしまい、市場での使用時に
腐食や断線が生じるという問題がある。このことから、
配線時の金属細線の高さはできるだけ低く設定する必要
がある。他方で、半導体チップの大型化に伴いリードフ
レームのダイパッド部のサイズも必然的に大きくなり、
ダイパッドの側面とインナーリードの先端面の間隔（図
６の間隔ｄに相当）は狭く成らざるを得ない状況にあ
る。このため、金属細線の一部が封止後に封止樹脂から
はみ出さないようにするために金属細線の高さを予め低
く設定しすぎると、半導体チップのボンディングパッド
とインナーリードの先端部とを金属細線でワイヤボンデ
ィングするに際して、金属細線の配線経路の傾きないし
は湾曲度がインナーリード先端部側で大きいため、配線
済み後の金属細線の一部がダイパッドの端面及び半導体
チップ端、又は他のインナーリードと接触して電気的な
短絡が生じる場合があり、このときには半導体装置の電
気的特性が低下してしまうという問題点が生ずる。従っ
て、ダイパッド側面とインナーリードの先端面との間隔
を広げること無く、この様な接触をも回避する必要性が
大である（特にダイパッドの端面との接触を回避する必
要性は大きい）。(1) On the other hand, as the package becomes thinner,
If the height at the time of wiring of the fine metal wire is increased, a part of the fine metal wire is exposed from the surface of the sealing resin, and there is a problem that corrosion and disconnection occur when used in a market. From this,
It is necessary to set the height of the thin metal wires at the time of wiring as low as possible. On the other hand, as semiconductor chips become larger, the size of the die pad part of the lead frame also inevitably increases,
The distance between the side surface of the die pad and the tip surface of the inner lead (corresponding to the distance d in FIG. 6) must be narrow. For this reason, if the height of the thin metal wire is set too low in advance so that a part of the thin metal wire does not protrude from the sealing resin after sealing, the bonding pad of the semiconductor chip and the tip of the inner lead may be displaced. When performing wire bonding with a thin metal wire, the inclination or the degree of curvature of the wiring path of the thin metal wire is large on the tip side of the inner lead, so that a portion of the thin metal wire after wiring is partially removed from the end surface of the die pad and the end of the semiconductor chip or another inner wire. There is a case where an electrical short circuit occurs due to contact with the lead, and at this time, there is a problem that electrical characteristics of the semiconductor device are deteriorated. Therefore, there is a great need to avoid such contact without increasing the distance between the side surface of the die pad and the tip surface of the inner lead (especially, it is necessary to avoid contact with the end surface of the die pad).

【０００６】この様な問題点を克服する方法としては、
インナーリードの先端部と対向するダイパッドの周縁部
分上に絶縁層を形成しておき、本来の配線経路よりはず
れて垂れ下がった金属細線を当該絶縁層で受け取る構成
が考えられる（例えば特開平２−１６６７５９号公報参
照）。しかし、金属細線を受け止め得るだけの高さ・幅
寸法を有する絶縁層を形成することは、絶縁層の厚みが
比較的厚く成らざるを得ないことから、製造上容易では
ない。従って、この方法を採用することは現実的ではな
く、到底採用し難いと言わざるを得ない。[0006] As a method of overcoming such problems,
A configuration is conceivable in which an insulating layer is formed on the peripheral portion of the die pad facing the tip of the inner lead, and the thin metal wire, which is deviated from the original wiring path and hangs down, is received by the insulating layer (for example, JP-A-2-166759). Reference). However, it is not easy to manufacture an insulating layer having a height and a width dimension capable of receiving a thin metal wire because the insulating layer must be relatively thick. Therefore, it is not realistic to adopt this method, and it must be said that it is difficult to adopt it at all.

【０００７】そこで、金属細線が少なくともダイパッド
の端面に接触しないようにするために、ダイパッドの端
面と接触する前に垂れ下がってきたインナーリード側の
金属細線を受け止めて支持するという着想を、より現実
的な構成で以て実現することが要望されるのである。Therefore, in order to prevent the metal thin wire from contacting at least the end face of the die pad, the idea of receiving and supporting the metal thin wire on the inner lead side which has been hanging down before contacting the end face of the die pad is more realistic. It is desired to be realized with a simple configuration.

【０００８】（２）又、半導体装置の高密度化に起因し
た半導体チップの大型化に伴い、接合材とリードフレー
ムのダイパッドとのクリアランスが少なくなるため、リ
ードフレームのダイパッドの上面上に半導体チップを接
合材を用いて搭載するに際して、接合材がリードフレー
ムのダイパッドの上面からはみ出す場合が生じ得る。こ
の様なはみ出しにより接合材がダイパッドの側面から裏
面にまで廻ってしまうと、次工程であるワイヤボンド工
程において接合材がヒート駒（ダイパッドや半導体チッ
プ等を加熱しておくためのブロックより成る治具）に付
着・堆積してしまい、ダイパッドが傾いてヒート駒と密
着良く接触することができ無くなり、十分な加熱ができ
なくなるという弊害が生ずる。このため、ワイヤボンド
接合に必要な熱が十分に供給されず、接合性の悪化とい
う問題点が生ずる。しかも、半導体チップの大型化に伴
いリードフレームのダイパッド部のサイズが必然的に大
きくなり、その結果、ダイパッドの側面とインナーリー
ドの先端面との間隔（図６の間隔ｄに相当）は狭く成ら
ざるを得ない事から、リードフレームのダイパッドの上
面からはみ出した接合材がインナーリードと接触してし
まう場合が生じやすくなる。その様な接触が生ずると、
シート性の劣化となってしまう。従って、この様な接合
材のダイパッドの上面からのはみ出しをも有効に防止す
る必要性が大である。(2) Since the clearance between the bonding material and the die pad of the lead frame decreases with the increase in the size of the semiconductor chip due to the higher density of the semiconductor device, the semiconductor chip is placed on the upper surface of the die pad of the lead frame. When mounting is performed using a bonding material, the bonding material may protrude from the upper surface of the die pad of the lead frame. When the bonding material is turned from the side surface to the rear surface of the die pad due to such protrusion, the bonding material is heated in a wire bonding process, which is a next step, by using a block composed of a block for heating the die pad and the semiconductor chip. ), The die pad is tilted and cannot be in close contact with the heat piece, resulting in a problem that sufficient heating cannot be performed. For this reason, the heat required for wire bond joining is not sufficiently supplied, and there is a problem that the joinability is deteriorated. In addition, as the size of the semiconductor chip increases, the size of the die pad portion of the lead frame inevitably increases. As a result, the distance between the side surface of the die pad and the tip surface of the inner lead (corresponding to the distance d in FIG. 6) is reduced. Since it is inevitable, the bonding material protruding from the upper surface of the die pad of the lead frame is likely to come into contact with the inner lead. When such contact occurs,
The sheet properties will be degraded. Therefore, there is a great need to effectively prevent such a bonding material from protruding from the upper surface of the die pad.

【０００９】本発明は上記の様な問題点（１）及び
（２）に鑑みなされたものである。即ち、その第１の目
的は、半導体チップの大型化やパッケージの薄型化の傾
向にも拘わらず、ダイパッドの側面とインナーリードの
先端面との間隔を広げること無く、金属細線のボンディ
ング時において金属細線がダイパッドの端面、又は半導
体チップ端、更には他のインナーリードと接触するのを
防止するための金属細線支持部を実現可能にすることに
ある。更に本発明の第２の目的は、半導体チップのダイ
ボンデイングに際して接合材がダイパッドからはみ出る
のを防止することにある。The present invention has been made in view of the above problems (1) and (2). That is, the first object is to increase the distance between the side surface of the die pad and the tip end surface of the inner lead and to reduce the metallization when bonding a thin metal wire, despite the tendency of the semiconductor chip to become larger and the package to become thinner. It is an object of the present invention to provide a thin metal wire support for preventing a thin wire from coming into contact with an end surface of a die pad, an end of a semiconductor chip, or even another inner lead. It is a second object of the present invention to prevent a bonding material from protruding from a die pad during die bonding of a semiconductor chip.

【００１０】[0010]

【課題を解決するための手段】請求項１に係る発明は、
リードフレームのダイパッド上に載置した半導体チップ
の表面上に形成されたボンディングパッドと前記リード
フレームのインナーリードとを金属細線で接続すると共
に樹脂封止して成る半導体装置であって、前記ダイパッ
ドの周縁部の内で前記ボンディングパッドと当該ボンデ
ィングパッドに接続すべき前記インナーリードとの間の
部分に少なくとも前記半導体チップの高さと同一の高さ
を有する突起部を設けると共に、前記突起部の上面上に
絶縁層を形成したことを特徴とする。The invention according to claim 1 is
A semiconductor device comprising: bonding a bonding pad formed on a surface of a semiconductor chip mounted on a die pad of a lead frame to an inner lead of the lead frame with a thin metal wire and sealing with a resin; A protrusion having at least the same height as the height of the semiconductor chip is provided in a portion between the bonding pad and the inner lead to be connected to the bonding pad in the peripheral portion, and on a top surface of the protrusion. Wherein an insulating layer is formed on the substrate.

【００１１】請求項２に係る発明は、請求項１に記載の
半導体装置であって、前記突起部は、前記半導体チップ
を完全に取り囲むように前記ダイパッドの周縁部に形成
されており、且つ前記絶縁層は、前記突起部の上面全体
に渡って形成されていることを特徴とする。According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the protrusion is formed on a peripheral portion of the die pad so as to completely surround the semiconductor chip. The insulating layer is formed over the entire upper surface of the protrusion.

【００１２】請求項３に係る発明は、請求項１又は２に
記載の半導体装置であって、前記絶縁層は硬化樹脂より
成ることを特徴とする。A third aspect of the present invention is the semiconductor device according to the first or second aspect, wherein the insulating layer is made of a cured resin.

【００１３】請求項４に係る発明は、請求項１又は２に
記載の半導体装置であって、前記絶縁層は前記突起部の
幅よりも幅が広い板状絶縁体より成ることを特徴とす
る。According to a fourth aspect of the present invention, in the semiconductor device according to the first or second aspect, the insulating layer is made of a plate-like insulator having a width larger than a width of the protrusion. .

【００１４】[0014]

【発明の実施の形態】以下、本発明の実施の形態を図に
基づいて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

【００１５】（実施の形態１）図１は、実施の形態１に
係る半導体装置１０の内部構造を示す縦断面図であり、
図２は、モールド成形前の、従ってダイボンド工程及び
ワイヤボンド工程終了後の半導体装置１０を示す上面図
である。(First Embodiment) FIG. 1 is a longitudinal sectional view showing an internal structure of a semiconductor device 10 according to a first embodiment.
FIG. 2 is a top view showing the semiconductor device 10 before molding, that is, after the die bonding step and the wire bonding step are completed.

【００１６】両図１、２に示す通り、半導体チップ１の
裏面は半田や樹脂等により成る接合材２によってダイパ
ッド３の上面３Ｓ上に固設されている。又、封止樹脂７
を用いたトランスファモールド工程後に図示していない
タイバー部を切断する事によって互いに分離される各イ
ンナーリード６は、図２に示す様にダイパッド３の外周
辺の内で対抗し合う２つの側辺の各々側において、互い
に接触しない様に所定の間隔で配置されている。しか
も、ダイパッド３の外周端ないしは周縁側面３ＳＳと各
インナーリード６の先端面６Ｅとの間隔は、従来の半導
体装置１０Ｐと同様の距離ｄ（図６参照）に保たれてい
る。他方、半導体チップ１の表面１Ｓ上には、同チップ
１の素子の各電極と接続された各ボンディングパッド５
が形成されており、各ボンディングパッド５とこれに対
応する位置にあるインナーリード６の先端部６Ａとは、
金属細線４を用いたワイヤボンディングによる配線によ
って互いに接続されている。そして、同装置１０は、上
記各部１〜６（但し、インナーリード６についてはその
先端部６Ａ側だけ）を包含するように、封止樹脂７によ
ってモールド成形されている。本装置１０における構成
の中核部分は、特殊形状を有するダイパッド３と後述す
る絶縁層８とから成る金属細線支持部ないしは金属細線
の受け部を設けた点にある。以下、これらの点について
詳述する。As shown in FIGS. 1 and 2, the back surface of the semiconductor chip 1 is fixed on the upper surface 3S of the die pad 3 by a bonding material 2 made of solder, resin or the like. Also, the sealing resin 7
The inner leads 6 separated from each other by cutting a tie bar portion (not shown) after the transfer molding process using the die are formed on two sides of the opposing sides in the outer periphery of the die pad 3 as shown in FIG. On each side, they are arranged at predetermined intervals so as not to contact each other. Moreover, the distance between the outer peripheral end or peripheral side surface 3SS of the die pad 3 and the distal end surface 6E of each inner lead 6 is maintained at the same distance d (see FIG. 6) as the conventional semiconductor device 10P. On the other hand, on the surface 1S of the semiconductor chip 1, each bonding pad 5 connected to each electrode of the element of the chip 1 is formed.
Are formed, and each bonding pad 5 and the tip 6A of the inner lead 6 located at the corresponding position are
They are connected to each other by wiring by wire bonding using the thin metal wires 4. The device 10 is molded with a sealing resin 7 so as to include the above-described parts 1 to 6 (however, the inner lead 6 has only the tip 6A side). The core of the configuration of the present apparatus 10 is that a thin metal wire supporting portion or a thin metal wire receiving portion composed of a die pad 3 having a special shape and an insulating layer 8 described later is provided. Hereinafter, these points will be described in detail.

【００１７】先ず第一の特徴点は、ダイパッド３の周縁
部又は外周部に沿って半導体チップ１を完全に取り囲む
ように、突起部ないしは凸部９が形成されている点にあ
る。尚、突起部９は、ダイパッド３を形成した後にダイ
パッド３の周縁部を半導体チップ１を搭載後に取り囲め
るような形でＬ字型に折り曲げて形成されている。ここ
では、突起部９のダイパッド３の上面３Ｓからの高さ
は、接合材２を含めた上面３Ｓからの半導体チップ１の
表面１Ｓの高さとほぼ同一に設定されている。勿論、突
起部９の高さを半導体チップ１の高さよりも高く設定し
ても良く、その最大値は、後述する絶縁層８と封止樹脂
７の上面７ＵＳとの間に金属細線４の配線経路を確保で
きる程度にまでという観点から画される。他方では、少
なくとも金属細線４がダイパッド３の端面と接触するの
を防止し得るようにしておくという観点からみるときに
は、突起部９の高さを半導体チップ１の表面１Ｓの高さ
よりも低く設定しても良い。その意味では、突起部９の
高さは任意の値で有れば良く、半導体チップ１の表面１
Ｓのそれと略同一に設定しておく必要性は必ずしも無
い。First, the first characteristic point is that a projection or a projection 9 is formed so as to completely surround the semiconductor chip 1 along the periphery or the periphery of the die pad 3. The projection 9 is formed by bending the peripheral edge of the die pad 3 into an L-shape so as to surround the semiconductor chip 1 after mounting the die pad 3 after the die pad 3 is formed. Here, the height of the protrusion 9 from the upper surface 3S of the die pad 3 is set substantially equal to the height of the surface 1S of the semiconductor chip 1 from the upper surface 3S including the bonding material 2. Of course, the height of the projection 9 may be set higher than the height of the semiconductor chip 1, and the maximum value is determined by the wiring of the thin metal wire 4 between the insulating layer 8 and the upper surface 7US of the sealing resin 7 described later. It is drawn from the viewpoint that a route can be secured. On the other hand, from the viewpoint of preventing at least the thin metal wire 4 from contacting the end face of the die pad 3, the height of the protrusion 9 is set to be lower than the height of the surface 1 S of the semiconductor chip 1. May be. In that sense, the height of the protrusion 9 may be an arbitrary value, and the height of the surface 1
It is not always necessary to set almost the same as that of S.

【００１８】次の特徴点は、突起部９の幅９ｄよりも広
い幅８ｄ（例えば0.3mm〜0.4mm）を有するフィルム状の
絶縁層（板状絶縁体とも称す）８が、突起部９の上面９
ＵＳに形成されている点にある。ここで、絶縁層８は、
フィラー等の絶縁物が添加された絶縁性接着材を突起部
９の上面９ＵＳ上に塗付し圧延によって加圧した上で加
熱処理を加えることにより形成されている。その際、上
述の通り８ｄ＞９ｄの関係が成立するので、絶縁層８の
接着位置精度に高精度を要することなく突起部９の上面
９ＵＳ上に絶縁層８を形成することができるという利点
がある。これにより、突起部９で支持された絶縁層８の
上面８ＵＳとモールド成形後に封止樹脂７の上面７ＵＳ
がくるべき位置との間に、金属細線４を配置すべき空間
が形成される。即ち、あるボンディングパッド５から見
れば、ワイヤボンディングすべき対象のインナーリード
６の先端部６Ａにまで金属細線４を張わすためには、半
導体チップ１の表面１Ｓよりも若干高い位置に存在する
絶縁層８を乗り越えていかなければならない金属細線４
の配線経路ないしは所定の軌跡が形成されるのである。The next feature is that a film-shaped insulating layer (also referred to as a plate-shaped insulator) 8 having a width 8d (for example, 0.3 mm to 0.4 mm) wider than the width 9d of the protrusion 9 is formed by Upper surface 9
The point is that it is formed in the US. Here, the insulating layer 8
It is formed by applying an insulating adhesive material to which an insulator such as a filler is added on the upper surface 9US of the projection 9, applying pressure by rolling, and applying a heat treatment. At this time, since the relationship of 8d> 9d is satisfied as described above, there is an advantage that the insulating layer 8 can be formed on the upper surface 9US of the protrusion 9 without requiring high precision in the bonding position accuracy of the insulating layer 8. is there. Thereby, the upper surface 8US of the insulating layer 8 supported by the protrusion 9 and the upper surface 7US of the sealing resin 7 after molding are formed.
A space where the thin metal wire 4 is to be arranged is formed between the position where the metal wire is to be formed. That is, from the viewpoint of a certain bonding pad 5, in order to stretch the thin metal wire 4 to the tip portion 6 </ b> A of the inner lead 6 to be wire-bonded, the insulation existing at a position slightly higher than the surface 1 </ b> S of the semiconductor chip 1. Fine metal wire 4 that must get over layer 8
A wiring path or a predetermined trajectory is formed.

【００１９】次に、本装置１０の作用・効果を説明す
る。Next, the operation and effect of the present apparatus 10 will be described.

【００２０】（１）以上の通り、ダイパッド３の周縁部
に半導体チップ１とほぼ同一の高さを有し且つ同チップ
１を取り囲む突起部９を設けると共に、更に突起部９の
上面９ＵＳ上にフィルム状の絶縁層８を形成しているた
め、半導体チップ１の大型化に伴うダイパッド３の大型
化や樹脂ケースの薄型化に起因してワイヤボンディング
時に金属細線４を配設すべきスペースが狭まり、その結
果、ワイヤボンディング時に金属細線４が所定の軌跡か
らはずれて下方に垂れたとしても、図１に破線で示す様
に、金属細線４ａの一部がフィルム状の絶縁層８の一部
に接触して同細線４ａが同絶縁層８により支持されるに
留まり、それよりも更に垂れ下がらないので、金属細線
４ａがダイパッド３に接触しなくなることは勿論、更に
半導体チップ端１Ｅ及び他のインナーリード６とも接触
することは無く、電気特性の不具合は生じ得ない。(1) As described above, the protrusion 9 having substantially the same height as the semiconductor chip 1 and surrounding the chip 1 is provided on the periphery of the die pad 3, and is further provided on the upper surface 9 US of the protrusion 9. Since the film-shaped insulating layer 8 is formed, the space for arranging the fine metal wires 4 at the time of wire bonding is reduced due to the enlargement of the die pad 3 and the thinning of the resin case accompanying the enlargement of the semiconductor chip 1. As a result, even when the thin metal wire 4 is deviated from a predetermined trajectory and hangs downward during wire bonding, a part of the thin metal wire 4a becomes part of the film-like insulating layer 8 as shown by a broken line in FIG. Since the fine wires 4a are in contact with each other and are only supported by the insulating layer 8 and do not hang down further, the fine metal wires 4a do not contact the die pad 3 and, of course, the semiconductor chip ends 1 And it is not to other inner leads contact 6 both can not occur inconvenience of electrical properties.

【００２１】（２）半導体装置１０の高密度化及び半導
体チップ１の大型化により接合材２とダイパッド３との
クリアランスが少なくなっても、ダイパッド３に半導体
チップ１を接合材２を用いて搭載する際に、突起部９が
半導体チップ１の周囲をを完全に取り囲んでいるので、
突起部９の内側壁面が接合材２の流れを塞き止める役割
を担う結果、接合材２がダイパッド３の上面３Ｓからは
み出すのを完全に防止する事ができる。(2) Even if the clearance between the bonding material 2 and the die pad 3 is reduced due to the increase in the density of the semiconductor device 10 and the size of the semiconductor chip 1, the semiconductor chip 1 is mounted on the die pad 3 using the bonding material 2. Since the projection 9 completely surrounds the periphery of the semiconductor chip 1,
As a result of the inner wall surface of the projection 9 playing a role of blocking the flow of the bonding material 2, the bonding material 2 can be completely prevented from protruding from the upper surface 3 </ b> S of the die pad 3.

【００２２】尚、例えば図２中に破線で囲んで示す部分
Ｒに、即ち、ダイパッド３の周縁部の内で、ある１つの
インナーリード６の先端部６Ａとそれに対応するワイヤ
ボンディングすべき相手側であるボンディングパッド５
との間の部分にのみ、例えば図１に示した様な寸法・断
面形状を有する突起部９を局所的に設け、該突起部９の
上面９ＵＳに絶縁層８を形成すれば、少なくとも当該突
起部９が配設された領域Ｒにおいては、金属細線４の垂
れに伴う同細線４のダイパッド３の端面や半導体チップ
端１Ｅ等との接触は局所的ではあるが有効に防止され、
上述した（２）の効果は得られないけれども、該部分に
ついて上述の（１）の効果は得られる。そして、その様
な１つの突起部９とその上面９ＵＳ上に形成された１つ
の絶縁層８とからなる構造物をボンディングパッド５な
いしはインナーリード６の各々に対応してダイパッド３
の周縁部に個別に設けていくことによって、全ての金属
細線４の配線箇所において上記（１）の効果を達成する
ことも可能である。その様な観点から見る限り、「ダイ
パッド３の周縁部の内で少なくとも１つのボンディング
パッド５と当該ボンディングパッド５に接続すべきイン
ナーリード６の先端部６Ａとの間に位置する部分に、任
意の高さを有する１つの突起部９とその上に形成された
絶縁層８とを具備させること」が、半導体装置１０にと
って有益であることが十分に理解されるところである。Incidentally, for example, in a portion R indicated by a broken line in FIG. 2, that is, in the peripheral portion of the die pad 3, the tip end portion 6A of one inner lead 6 and the corresponding partner to be wire-bonded corresponding thereto. Bonding pad 5
If, for example, a projection 9 having a dimension and a cross-sectional shape as shown in FIG. 1 is locally provided only in a portion between them and the insulating layer 8 is formed on the upper surface 9US of the projection 9, at least the projection In the region R where the portion 9 is provided, the contact of the fine metal wire 4 with the end face of the die pad 3 or the semiconductor chip end 1E due to the dripping of the fine metal wire 4 is effectively prevented although it is local,
Although the above-mentioned effect (2) cannot be obtained, the above-mentioned effect (1) can be obtained for this portion. Then, a structure composed of one such protrusion 9 and one insulating layer 8 formed on the upper surface 9US of the die pad 3 corresponding to each of the bonding pad 5 or the inner lead 6 is formed.
The effect (1) described above can be achieved at all the wiring locations of the thin metal wires 4 by providing them individually at the peripheral edge of the metal wire. From such a point of view, any part of the peripheral portion of the die pad 3 located between the at least one bonding pad 5 and the tip end portion 6A of the inner lead 6 to be connected to the bonding pad 5 may have any shape. Providing one protruding portion 9 having a height and the insulating layer 8 formed thereon is useful for the semiconductor device 10.

【００２３】（実施の形態１の変形例１）図３は、実施
の形態１の変形例１における半導体装置１０Ａの内部構
造を示す縦断面図である。(First Modification of First Embodiment) FIG. 3 is a longitudinal sectional view showing the internal structure of a semiconductor device 10A according to a first modification of the first embodiment.

【００２４】本変形例の特徴点は、リードフレームの各
パターン（リード部やダイパッドやタイバー部等）をエ
ッチングによって形成する際に突起部９をも同時に形成
してしまうことにある。これにより、図３に示す通り、
インナーリード６ａの裏面６ａＤからインナーリード６
ａの表面６ａＳまでの高さないしは厚みと突起部９のダ
イパッド３の裏面３Ｄから突起部９の上面９ＵＳまでの
高さとは、同一に設定されることになる。具体的には、
リードフレームのパターンをエッチングによって形成す
るに際して、リードフレーム中、突起部９が形成される
べきダイパッド３の周縁部分にマスクをかけて、半導体
チップ１の搭載後における接合材２を含めたダイパッド
３の裏面３Ｄからの半導体チップ１の表面１Ｓまでの高
さと同面３Ｄからの突起部９の高さとが同程度になる様
にダイパッド３が形成されるべき部分を凹状又は溝状に
エッチングし、その後、上記マスクを除去することによ
りダイパッド３の周縁部分に垂直上方向に延びた突起部
９が形成される。The feature of this modification is that the projections 9 are formed simultaneously when the respective patterns (leads, die pads, tie bars, etc.) of the lead frame are formed by etching. Thereby, as shown in FIG.
From the back surface 6aD of the inner lead 6a to the inner lead 6
The height or thickness of the protrusion a from the back surface 3D of the die pad 3 to the upper surface 9US of the protrusion 9 is set to be the same. In particular,
When forming the pattern of the lead frame by etching, a mask is applied to the peripheral portion of the die pad 3 where the projection 9 is to be formed in the lead frame, and the die pad 3 including the bonding material 2 after the semiconductor chip 1 is mounted. A portion where the die pad 3 is to be formed is etched in a concave or groove shape so that the height from the back surface 3D to the front surface 1S of the semiconductor chip 1 and the height of the protrusion 9 from the same surface 3D are substantially the same. By removing the mask, a protrusion 9 extending vertically upward is formed on the peripheral portion of the die pad 3.

【００２５】本変形例によれば、ダイパッド３を形成し
た後にダイパッド３の周縁部分をＬ字型に折り曲げて突
起部９を形成する場合と比較して、容易に高精度で確実
に突起部９を形成することができ、ダイパッド３の表面
３Ｓに対する同部９の上面９ＵＳの平行度を向上させる
ことができ、傾きの少ない上面９ＵＳ上に確実に絶縁層
８を配設することがより一層可能となる。According to the present modification, the projection 9 is easily formed with high precision and accuracy compared to the case where the periphery of the die pad 3 is bent into an L-shape after the die pad 3 is formed. Can be formed, the degree of parallelism of the upper surface 9US of the same portion 9 with respect to the surface 3S of the die pad 3 can be improved, and the insulating layer 8 can be more reliably disposed on the upper surface 9US with a small inclination. Becomes

【００２６】（実施の形態１の変形例２）図４は、実施
の形態１の変形例２における半導体装置１０Ｂの内部構
造を示す縦断面図である。(Modification 2 of Embodiment 1) FIG. 4 is a longitudinal sectional view showing the internal structure of a semiconductor device 10B in Modification 2 of Embodiment 1.

【００２７】本変形例の特徴点は、図１の絶縁層８の製
法及び形状・材質を改善した点に有り、図４に示す通
り、絶縁層８ａが、突起部９の上面９ＵＳと同面９ＵＳ
の周囲近傍の突起部９の側面の一部分を含む様に、硬化
樹脂によって形成されている。ここでは、絶縁層８ａ
は、例えばエポキシ樹脂を主成分とする硬化樹脂をディ
スペンサで塗布し、摂氏１５０度の温度でキュア装置に
より同樹脂を加熱して硬化させる事により形成されてい
る。The feature of this modification is that the manufacturing method, shape and material of the insulating layer 8 of FIG. 1 are improved. As shown in FIG. 4, the insulating layer 8a is flush with the upper surface 9US of the projection 9. 9US
Is formed of a cured resin so as to include a part of the side surface of the protruding portion 9 in the vicinity of the periphery. Here, the insulating layer 8a
Is formed, for example, by applying a cured resin mainly composed of an epoxy resin with a dispenser, and heating and curing the resin with a curing device at a temperature of 150 degrees Celsius.

【００２８】この様な構成を使用した理由は次の観点に
よる。即ち、実施の形態１においては、フィルム状の絶
縁層８を突起部９の上面９ＵＳ上に形成しているが、絶
縁層８の上面９ＵＳへの接着時に位置ずれが生じない様
に所定のマージンを予め確保しておく必要がある。とい
うのは、突起部９の上面９ＵＳ側のマージンが少ないた
めにもし絶縁層８が所定の配置位置から位置ずれを起こ
すと、絶縁層８が突起部９の上面９ＵＳ上自体に載らな
くなったり、仮に絶縁層８が突起部９の上面９ＵＳ上に
載置されたとしても傾いてしまい金属細線４を確実に支
持できなくなるおそれも生じ、場合によっては絶縁層８
が突起部９から落ちてしまう事もあり得るからである。
これらの問題点を回避するためにも、所定のマージンを
確保することが必須事項となる。そこで、この様なマー
ジンの設定を不必要とすることができるならば、絶縁層
８の形成方法も容易となり、歩留まり向上によるコスト
低減化も図り得る。かかる観点から、本変形例では、絶
縁層８ａを上記の製法を用いて硬化樹脂により形成する
こととしているのである。The reason for using such a configuration is as follows. That is, in the first embodiment, the film-shaped insulating layer 8 is formed on the upper surface 9US of the projection 9, but the predetermined margin is set so that no displacement occurs when the insulating layer 8 is bonded to the upper surface 9US. Must be reserved in advance. That is, because the margin on the upper surface 9US side of the projection 9 is small, if the insulating layer 8 is displaced from a predetermined arrangement position, the insulating layer 8 will not be placed on the upper surface 9US of the projection 9 itself, Even if the insulating layer 8 is placed on the upper surface 9US of the projection 9, there is a risk that the insulating layer 8 is inclined and cannot support the thin metal wire 4 reliably.
Is likely to fall from the projection 9.
In order to avoid these problems, it is essential to secure a predetermined margin. Therefore, if it is not necessary to set such a margin, the method of forming the insulating layer 8 becomes easy, and the cost can be reduced by improving the yield. From this point of view, in the present modification, the insulating layer 8a is formed of a cured resin using the above-described manufacturing method.

【００２９】従って、本変形例によれば、絶縁層８をフ
ィルム状の絶縁体で形成した場合に比べて、突起部９の
上面９ＵＳへの接着時の加工が格段に容易となり、絶縁
層８ａの剥がれや位置ずれ等が無く、金属細線４と半導
体チップ端１Ｅ等との間の絶縁性に関する品質上の信頼
性が極めて高い半導体装置を提供できるという効果があ
る。Therefore, according to the present modification, the process of bonding the projection 9 to the upper surface 9US is much easier than the case where the insulating layer 8 is formed of a film-shaped insulator, and the insulating layer 8a There is an effect that it is possible to provide a semiconductor device which is free from peeling, misalignment and the like, and has extremely high quality reliability regarding insulation properties between the thin metal wire 4 and the semiconductor chip end 1E.

【００３０】（まとめ）図６の従来の半導体装置１０Ｐ
の場合では、ワイヤボンド工程において金属細線４Ｐと
半導体チップ端等との接触を回避するためには、図５に
示す通り、ループコントロールを使用する（反面、処
理能力が低下してしまう）、又は検査頻度を高めて不
良選別を行う、更には不良選別の見逃しによる客先不
具合のためにＳＰＣ管理を適用するという様な回避策を
採る必要性が生じていた。しかし、本半導体装置１０、
１０Ａ、１０Ｂによれば、既述した通り、突起部９とそ
の上の絶縁層８、８ａとによって金属細線４のダイパッ
ド３や半導体チップ端１Ｅ等との接触を完全に防止する
ことが可能となり（突起部９の高さいかんに拘わらず、
絶縁層８、８ａの薄膜化を達成しつつ、少なくとも金属
細線４とダイパッド３との接触を完全に防止し得る）、
前述の〜の回避策を採る必要性が全く無くなる。従
って、ワイヤボンド工程におけるプロセスマージンの増
大化に伴う高速化、品質安定化、検査工程の省略化を図
ることができる。(Summary) Conventional semiconductor device 10P shown in FIG.
In the case of (1), in order to avoid contact between the thin metal wire 4P and the end of the semiconductor chip or the like in the wire bonding step, a loop control is used as shown in FIG. 5 (while the processing capability is reduced), or There has been a need to take measures such as increasing the inspection frequency to perform defect selection, and applying SPC management for customer trouble due to overlooking the defect selection. However, the present semiconductor device 10,
According to 10A and 10B, as described above, it is possible to completely prevent the contact of the thin metal wire 4 with the die pad 3 or the semiconductor chip end 1E or the like by the protrusion 9 and the insulating layers 8 and 8a thereon. (Regardless of the height of the projection 9,
At least the contact between the fine metal wires 4 and the die pad 3 can be completely prevented while achieving the thinning of the insulating layers 8 and 8a).
There is no need to take the above-mentioned workarounds. Therefore, it is possible to increase the speed, stabilize the quality, and omit the inspection process with the increase in the process margin in the wire bonding process.

【００３１】又、本半導体装置１０、１０Ａ、１０Ｂに
よれば、接合材２とインナーリード６、６ａの先端面６
Ｅ、６ａＥとの接触がないため、半導体チップ１の大型
化に伴うリードフレームのダイパッド３のサイズの必然
的な大型化によるダイパッド３の側面３ＳＳとインナー
リード６、６ａの先端面６Ｅ、６ａＥとの間隔ｄの狭域
化に対応でき、半導体装置の高密度化を図ることができ
る。According to the semiconductor devices 10, 10A and 10B, the bonding material 2 and the tip surfaces 6 of the inner leads 6 and 6a are provided.
Since there is no contact with E and 6aE, the side surface 3SS of the die pad 3 and the tip surfaces 6E and 6aE of the inner leads 6 and 6a due to the inevitable increase in the size of the die pad 3 of the lead frame accompanying the enlargement of the semiconductor chip 1. Can be narrowed, and the density of the semiconductor device can be increased.

【００３２】更に、ダイボンド工程において、図６の半
導体装置１０Ｐの場合では、ダイパッド３Ｐの上面３Ｓ
Ｐからの接合材２Ｐのはみ出しの回避策として、図５に
示す通り、接合材２Ｐがダイパッド３Ｐの上面に安定
して広がるように半導体チップ１Ｐをダイパッド３Ｐへ
搭載するスピード及び荷重を下げるとか、検査頻度を
増やして不良選別を行ったり、更に不良選別の見逃し
による客先不具合のためにＳＰＣ管理を適用するという
様な対策を採る必要性が生じていた。しかしながら、本
半導体装置１０、１０Ａ、１０Ｂによれば、前述の〜
の対策を採る必要性が全くなくなり、ダイボンド工程
におけるプロセスマージンの増大化に伴う高速化、品質
安定化、検査工程の省略化を図ることができる。Further, in the die bonding step, in the case of the semiconductor device 10P of FIG. 6, the upper surface 3S of the die pad 3P is formed.
As a countermeasure for preventing the bonding material 2P from protruding from P, as shown in FIG. 5, reducing the speed and load at which the semiconductor chip 1P is mounted on the die pad 3P so that the bonding material 2P spreads stably on the upper surface of the die pad 3P. There has been a need to take measures such as increasing the frequency of inspections to carry out defect sorting, and further applying SPC management for customer problems due to overlooking the defect sorting. However, according to the present semiconductor devices 10, 10A, and 10B, the above-described ~
Therefore, there is no need to take the above-mentioned measure, and the speed, quality stabilization, and the inspection step can be omitted with an increase in the process margin in the die bonding step.

【００３３】（付記） （１）ここで、ダイパッドの周縁部に金属細線の垂れ下
がり部分を受け止めて支持するための絶縁層を有する支
持体を形成するにあたって、単に絶縁層のみを以て上記
垂れ下がり部分の支持体をダイパッドの周縁部に形成す
るのではなくて、本半導体装置１０、１０Ａ、１０Ｂに
おいては、ダイパッド３の周縁部に一且突起部９をダイ
パッド３自身で以て形成した上で当該突起部９の上面に
更に絶縁層８、８ａを配設するという構造を採用してい
る。そのため、本半導体装置１０、１０Ａ、１０Ｂは、
当該突起部９の高さの分だけ絶縁層８、８ａの薄型化を
可能にしてると言える。(Supplementary Note) (1) Here, when forming a support having an insulating layer for receiving and supporting the hanging portion of the fine metal wire at the peripheral portion of the die pad, the above-mentioned hanging portion is supported only by the insulating layer alone. Instead of forming the body on the periphery of the die pad, in the present semiconductor device 10, 10A, 10B, the projection 9 is formed on the periphery of the die pad 3 by the die pad 3 itself, and then the projection 9 is formed. The structure in which insulating layers 8 and 8a are further provided on the upper surface of the substrate 9 is adopted. Therefore, the present semiconductor devices 10, 10A, and 10B
It can be said that the thickness of the insulating layers 8 and 8a can be reduced by the height of the projections 9.

【００３４】（２）又、既述した特開平２−１６６７５
９号公報には、金属細線の垂れの防止及び金属細線と半
導体チップ端等との接触を防止するという観点から、半
導体チップを搭載するダイパッドと、当該半導体チップ
との間に金属細線が接続されるインナーリードとを備え
るリードフレームにおいて、当該ダイパッドの周辺部に
耐熱性樹脂からなる枠を表面上に突出するように形成す
る技術が開示されている。しかしながら、当該先行技術
はダイパッドの周辺部に耐熱性樹脂からなる枠を表面上
に突出形成することを単に提案するものであるのに対し
て、本半導体装置１０、１０Ａ、１０Ｂにおいては、ダ
イパッド３の周縁部にダイパッド３自身より成る突起部
９を設けた上で、当該突起部９の上面に比較的薄い厚み
の絶縁層８、８ａを形成している。従って、本半導体装
置１０、１０Ａ、１０Ｂにおいては、突起部９を有する
ことにより絶縁層８、８ａを薄膜化して容易に形成する
ことができるという利点がある。これに対して、当該先
行技術では、金属細線を支持するために必要な耐熱性樹
脂の高さ及び幅の形成が困難である。この点で、本半導
体装置１０、１０Ａ、１０Ｂは上記先行技術と比較して
有益な構成を有するものであると言える。(2) Also, as already described in JP-A-2-16675.
No. 9, from the viewpoint of preventing sagging of a thin metal wire and preventing contact between the thin metal wire and the end of a semiconductor chip, a thin metal wire is connected between a die pad on which a semiconductor chip is mounted and the semiconductor chip. In a lead frame provided with inner leads, a technique is disclosed in which a frame made of a heat-resistant resin is formed around the die pad so as to protrude above the surface. However, the prior art merely proposes to form a frame made of a heat-resistant resin on the periphery of the die pad so as to protrude above the surface, whereas in the present semiconductor devices 10, 10A and 10B, the die pad 3 Are provided on the periphery of the die pad 3, and the insulating layers 8, 8a having a relatively small thickness are formed on the upper surface of the projection 9. Therefore, the present semiconductor devices 10, 10A, and 10B have the advantage that the presence of the projections 9 allows the insulating layers 8, 8a to be easily formed with a reduced thickness. On the other hand, in the related art, it is difficult to form the height and width of the heat-resistant resin necessary to support the thin metal wire. In this regard, it can be said that the present semiconductor devices 10, 10A, and 10B have an advantageous configuration as compared with the above-described prior art.

【００３５】[0035]

【発明の効果】請求項１の発明によれば、ダイパッドの
周縁部の内でインナーリードと対応するボンディングパ
ッドとの間の部分に突起部を設けると共に突起部の上面
上に薄膜の絶縁層を形成しているため、半導体チップ及
びダイパッドの大型化や樹脂ケースの薄型化に伴いボン
ディング時に金属細線を配設すべきスペースが狭まり、
その結果、金属細線の垂れが生じたとしても、金属細線
は樹脂外にはみ出すことなく突起部の高さ分だけ上方の
位置において絶縁層で確実に支持されることとなり、金
属細線がダイパッド端、半導体チップ端及び隣接金属細
線と接触したり異常接近することを防止できるという効
果がある。従って、ダイパッドの周縁部の内でインナー
リードと対応するボンディングパッドとの間のすべて部
分に突起部を設けると共に突起部の上面上に絶縁層を形
成すれば、半導体装置全体として上記の効果が得られ
る。According to the first aspect of the present invention, a protrusion is provided at a portion between the inner lead and the corresponding bonding pad in the peripheral portion of the die pad, and a thin insulating layer is formed on the upper surface of the protrusion. Due to the formation, the space for arranging fine metal wires at the time of bonding becomes narrower with the enlargement of semiconductor chips and die pads and the thinner resin case,
As a result, even if sagging of the thin metal wire occurs, the thin metal wire will be reliably supported by the insulating layer at a position above the height of the protrusion without protruding out of the resin, and the thin metal wire will have a die pad end. There is an effect that it is possible to prevent contact or abnormal approach to the semiconductor chip end and adjacent metal fine wires. Therefore, if the protrusions are provided in all the portions between the inner leads and the corresponding bonding pads in the peripheral portion of the die pad, and the insulating layer is formed on the upper surface of the protrusions, the above-described effects can be obtained as a whole semiconductor device. Can be

【００３６】請求項２の発明によれば、半導体装置の高
密度化及び半導体チップの大型化により接合材とダイパ
ッドのクリアランスが少なくなっても、ダイパッドに半
導体チップを接合材を用いて搭載する際に、突起部が、
半導体チップを完全に取り囲むように前記ダイパッドの
周縁部に形成されているため、接合材がダイパッドから
はみ出すのを防止できるという効果がある。According to the second aspect of the present invention, even when the clearance between the bonding material and the die pad is reduced due to the increase in the density of the semiconductor device and the size of the semiconductor chip, the semiconductor chip is mounted on the die pad using the bonding material. The projections
Since the die pad is formed on the periphery of the die pad so as to completely surround the semiconductor chip, there is an effect that the bonding material can be prevented from protruding from the die pad.

【００３７】請求項３の発明によれば、絶縁層をフィル
ム状の絶縁体で形成した場合に比べて絶縁層の剥がれや
位置ずれ等が無く、金属細線と半導体チップ等との間の
絶縁性に関する品質上の信頼性が極めて高い半導体装置
を提供できるという効果がある。According to the third aspect of the present invention, there is no peeling or displacement of the insulating layer as compared with the case where the insulating layer is formed of a film-like insulator, and the insulating property between the thin metal wire and the semiconductor chip or the like. There is an effect that a semiconductor device having extremely high quality reliability can be provided.

【００３８】請求項４の発明によれば、ダイパッドの周
縁部に金属細線の垂れを支持する絶縁層を形成するに際
して、ダイパッドの周縁部で突起部を形成し当該突起部
の上面に当該突起部の幅よりも幅が広い板状絶縁体を配
設しているので、絶縁層の接着位置精度につき高精度を
要することなく、金属細線を支持可能な薄型の絶縁層を
実現することができるという効果がある。According to the fourth aspect of the present invention, when forming the insulating layer for supporting the hanging of the fine metal wire on the peripheral portion of the die pad, a projection is formed on the peripheral portion of the die pad, and the projection is formed on the upper surface of the projection. Since a plate-shaped insulator wider than the width of the insulating layer is provided, it is possible to realize a thin insulating layer capable of supporting a thin metal wire without requiring high precision in bonding position of the insulating layer. effective.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 この発明の実施の形態１に係る半導体装置の
縦断面図である。FIG. 1 is a longitudinal sectional view of a semiconductor device according to a first embodiment of the present invention.

【図２】 この発明の実施の形態１に係る半導体装置の
平面図である。FIG. 2 is a plan view of the semiconductor device according to the first embodiment of the present invention;

【図３】 この発明の実施の形態１の変形例１における
半導体装置の縦断面図である。FIG. 3 is a longitudinal sectional view of a semiconductor device according to a first modification of the first embodiment of the present invention;

【図４】 この発明の実施の形態１の変形例２における
半導体装置の縦断面図である。FIG. 4 is a longitudinal sectional view of a semiconductor device according to a second modification of the first embodiment of the present invention.

【図５】 従来の半導体装置の問題点とこの発明による
改善点とを比較列挙した説明図である。FIG. 5 is an explanatory diagram comparing and enumerating a problem of a conventional semiconductor device and an improvement by the present invention.

【図６】 従来の半導体装置の縦断面図である。FIG. 6 is a longitudinal sectional view of a conventional semiconductor device.

【図７】 従来の半導体装置の平面図である。FIG. 7 is a plan view of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１ 半導体チップ、２ 接合材、３ ダイパッド、４
金属細線、５ ボンディングパッド、６，６ａ インナ
ーリード、７ 封止樹脂、８，８ａ 絶縁層、９ 突起
部、１０，１０Ａ，１０Ｂ 半導体装置。1 semiconductor chip, 2 bonding material, 3 die pad, 4
Thin metal wires, 5 bonding pads, 6, 6a inner leads, 7 sealing resin, 8, 8a insulating layer, 9 protrusions, 10, 10A, 10B semiconductor device.

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 リードフレームのダイパッド上に載置し
た半導体チップの表面上に形成されたボンディングパッ
ドと前記リードフレームのインナーリードとを金属細線
で接続すると共に樹脂封止して成る半導体装置であっ
て、 前記ダイパッドの周縁部の内で前記ボンディングパッド
と当該ボンディングパッドに接続すべき前記インナーリ
ードとの間の部分に突起部を設けると共に、 前記突起部の上面上に絶縁層を形成したことを特徴とす
る、半導体装置。1. A semiconductor device comprising a bonding pad formed on a surface of a semiconductor chip mounted on a die pad of a lead frame and an inner lead of the lead frame connected by a thin metal wire and sealed with a resin. And providing a projection at a portion between the bonding pad and the inner lead to be connected to the bonding pad in a peripheral portion of the die pad, and forming an insulating layer on an upper surface of the projection. A semiconductor device, which is characterized by the following. 【請求項２】 請求項１に記載の半導体装置であって、 前記突起部は、前記半導体チップを完全に取り囲むよう
に前記ダイパッドの周縁部に形成されており、且つ前記
絶縁層は、前記突起部の上面全体に渡って形成されてい
ることを特徴とする、半導体装置。2. The semiconductor device according to claim 1, wherein the protrusion is formed on a periphery of the die pad so as to completely surround the semiconductor chip, and the insulating layer is formed on the protrusion. A semiconductor device formed over the entire upper surface of the portion. 【請求項３】 請求項１又は２に記載の半導体装置であ
って、 前記絶縁層は硬化樹脂より成ることを特徴とする、半導
体装置。3. The semiconductor device according to claim 1, wherein the insulating layer is made of a cured resin. 【請求項４】 請求項１又は２に記載の半導体装置であ
って、 前記絶縁層は前記突起部の幅よりも幅が広い板状絶縁体
より成ることを特徴とする、半導体装置。4. The semiconductor device according to claim 1, wherein the insulating layer is made of a plate-like insulator having a width larger than a width of the protrusion.
JP24510299A 1999-08-31 1999-08-31 Semiconductor device Pending JP2001068614A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24510299A JP2001068614A (en) 1999-08-31 1999-08-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24510299A JP2001068614A (en) 1999-08-31 1999-08-31 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2001068614A true JP2001068614A (en) 2001-03-16

Family

ID=17128654

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24510299A Pending JP2001068614A (en) 1999-08-31 1999-08-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2001068614A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103762200A (en) * 2013-12-31 2014-04-30 三星半导体(中国)研究开发有限公司 Chip packaging part and packaging method of chip packaging part
US10186498B2 (en) 2015-07-27 2019-01-22 Semiconductor Components Industries, Llc Semiconductor leadframes and packages with solder dams and related methods
US10290907B2 (en) 2015-07-27 2019-05-14 Semiconductor Components Industries, Llc Automatically programmable battery protection system and related methods
US10686317B2 (en) 2015-07-27 2020-06-16 Semiconductor Components Industries, Llc Programmable battery protection system and related methods

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103762200A (en) * 2013-12-31 2014-04-30 三星半导体(中国)研究开发有限公司 Chip packaging part and packaging method of chip packaging part
CN103762200B (en) * 2013-12-31 2016-09-07 三星半导体(中国)研究开发有限公司 Chip package and method for packing thereof
US10186498B2 (en) 2015-07-27 2019-01-22 Semiconductor Components Industries, Llc Semiconductor leadframes and packages with solder dams and related methods
US10290907B2 (en) 2015-07-27 2019-05-14 Semiconductor Components Industries, Llc Automatically programmable battery protection system and related methods
US10686317B2 (en) 2015-07-27 2020-06-16 Semiconductor Components Industries, Llc Programmable battery protection system and related methods
US10756553B2 (en) 2015-07-27 2020-08-25 Semiconductor Components Industries, Llc Programmable battery protection system and related methods
US10937763B2 (en) 2015-07-27 2021-03-02 Semiconductor Components Industries, Llc Semiconductor leadframes and packages with solder dams and related methods

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