JP2001067277A - 試験ユニット - Google Patents

試験ユニット

Info

Publication number
JP2001067277A
JP2001067277A JP2000215443A JP2000215443A JP2001067277A JP 2001067277 A JP2001067277 A JP 2001067277A JP 2000215443 A JP2000215443 A JP 2000215443A JP 2000215443 A JP2000215443 A JP 2000215443A JP 2001067277 A JP2001067277 A JP 2001067277A
Authority
JP
Japan
Prior art keywords
bus
data
unit
test
data pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000215443A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001067277A5 (enExample
Inventor
Herbert Tiedemann
ヘルベルト・ティーデマン
Tilmann Wendel
ティルマン・ウェンデル
Jochen Rivoir
ヨーヘン・リフォイル
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of JP2001067277A publication Critical patent/JP2001067277A/ja
Publication of JP2001067277A5 publication Critical patent/JP2001067277A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/277—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault-free response

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP2000215443A 1999-07-26 2000-07-17 試験ユニット Pending JP2001067277A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP99114613.5 1999-07-26
EP99114613A EP1020798B1 (en) 1999-07-26 1999-07-26 Unidirectional verification of bus-based systems

Publications (2)

Publication Number Publication Date
JP2001067277A true JP2001067277A (ja) 2001-03-16
JP2001067277A5 JP2001067277A5 (enExample) 2007-08-16

Family

ID=8238661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000215443A Pending JP2001067277A (ja) 1999-07-26 2000-07-17 試験ユニット

Country Status (4)

Country Link
US (1) US6735728B1 (enExample)
EP (1) EP1020798B1 (enExample)
JP (1) JP2001067277A (enExample)
DE (1) DE69900971T2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060200720A1 (en) * 2005-03-01 2006-09-07 David Grimme Generating and verifying read and write cycles in a PCI bus system
US8095769B2 (en) * 2008-08-19 2012-01-10 Freescale Semiconductor, Inc. Method for address comparison and a device having address comparison capabilities
CN104795802B (zh) * 2014-01-16 2018-07-10 西门子公司 具有通信总线故障诊断功能的保护装置、系统及方法
US11106788B2 (en) 2018-11-08 2021-08-31 Hewlett Packard Enterprise Development Lp Security for active data request streams

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2158433C3 (de) * 1971-11-25 1975-07-31 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren und Einrichtung zur Fehlerprüfung und Fehlerlokalisierung in einer moduleren Datenverarbeitungsanlage
US4622669A (en) * 1983-02-07 1986-11-11 Motorola, Inc. Test module for asynchronous bus
JPH01214949A (ja) * 1988-02-23 1989-08-29 Fujitsu Ltd バス異常監視方式
US5197062A (en) * 1991-09-04 1993-03-23 Picklesimer David D Method and system for simultaneous analysis of multiplexed channels
DE4333953A1 (de) * 1992-12-04 1994-06-09 Siemens Ag Verfahren zur Überprüfung eines unidirektionalen Datenkanals
US5596715A (en) * 1993-07-06 1997-01-21 Digital Equipment Corporation Method and apparatus for testing high speed busses using gray-code data
US5822513A (en) * 1996-09-27 1998-10-13 Emc Corporation Method and apparatus for detecting stale write data

Also Published As

Publication number Publication date
US6735728B1 (en) 2004-05-11
DE69900971T2 (de) 2004-03-18
EP1020798A1 (en) 2000-07-19
EP1020798B1 (en) 2002-03-06
DE69900971D1 (de) 2002-04-11

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