JP2001053818A - Carrier recovery circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To always optimally constitute the loop band of a PLL in the carrier recovery circuit of a composite modulated wave signal obtained by frequency modulating a quadrature modulated signal with an SC signal. SOLUTION: An input IF signal Si of this carrier recovery circuit is a composite modulated wave signal. In this carrier recovery circuit, a phase locked loop(PLL) is constituted of multiplier circuits 1 and 2, LPF 3 and 4, amplifier circuits 5 and 6, A/D converters 7 and 8, an identifier 9, an APC signal detector circuit 10, an LPF 13, and a VCO 12. A carrier control information signal S6 from the APC signal detector circuit 10 is amplified by an SC amplifier circuit 14, and frequency-demodulated, and an SC signal Sc is reproduced. The identifier 9 is the identifying circuit of a main signal. An error pulse detecting circuit 15 receives a digital signal Sd from the A/D converter 7 or 8, and controls the band of the LPF 13 according to the BER of an error pulse. An SC level detecting circuit 17 connected with the SC amplifier circuit 14 controls the band of the LPF 13 according to the presence or absence of the SC signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carrier recovery circuit, and more particularly, to a method for converting a quadrature modulated signal into a service channel signal (S
The present invention relates to a carrier recovery circuit for a composite modulated wave signal frequency-modulated by the C signal.

[0002]

2. Description of the Related Art Conventionally, quadrature modulated wave signals such as phase displacement modulation (PSK modulation) wave signals and quadrature amplitude modulation (QAM modulation) wave signals have been used in radio communication such as microwave communication. In the demodulation of these quadrature modulated signals, it is necessary to ensure good signal error characteristics, quick pull-in when the carrier is asynchronous, and prevention of erroneous switching of lines due to residual errors of error pulses. In the demodulation of the quadrature modulated signal, the carrier of the quadrature modulated signal is reproduced to generate a reproduced carrier signal, and the carrier of the quadrature modulated signal and the reproduced carrier signal are synchronously detected to obtain a baseband signal. A method of multi-level identification of a band signal by an A / D converter is often used.

In order to obtain the reproduced carrier signal, a phase locked loop (PLL) is often used. This phase-locked loop may be conveniently switched to a narrow band for good signal error characteristics, or to a wide band for rapid pull-in when asynchronous. In order to switch the loop band, control is often performed based on an alarm or information from the subsequent stage of the demodulator. However, since it takes time to detect and control such information, it has been difficult to quickly switch loop bands.

When transmitting a composite modulation wave signal obtained by frequency-modulating the quadrature modulation wave signal with the SC signal (in the case of an analog SC signal, including a line monitoring signal and a voice signal), generally, the presence or absence of the SC signal Often does not change the loop band. However, when the same wide band loop band configuration as that for transmitting the SC signal is used, there is a problem that a residual error of the main (quadrature modulation) signal and its error pulse is likely to occur. On the other hand, when the SC signal is not transmitted in the same broadband loop configuration, there is a problem that good signal error characteristics cannot be obtained for the main signal.

Further, when transmitting an analog SC signal, an audio signal (transmission baseband signal band: 300 Hz)
(-3.4 KHz), because of the strength of the sound, it was necessary to design a line assuming a higher level sound than a standard level. Also in this case, it is necessary to widen the loop band of the reproduction carrier circuit of the demodulator in accordance with the composite modulated wave signal including the SC signal, so that the residual error of the main signal and the residual error of the error pulse occur. There was a problem that it would increase. Similarly, when transmitting only a line monitoring signal (for example, a signal obtained by frequency-dividing a 300 Hz to 12 KHz band into 3CHs of 4 KHz bands) as an analog SC signal, a loop band is separately designed assuming only a standard level. In consideration of the common design with the audio signal transmission, the loop band is designed to be widened in accordance with the audio signal transmission.

[0006]

As described above, in the conventional carrier recovery circuit for a composite modulated signal, the loop band of the phase locked loop for obtaining the recovered carrier signal is determined by whether or not the SC signal is transmitted and the BER of the main signal. Since it could not be changed quickly, the optimal loop band could not be set according to the presence or absence of the SC signal.
In order to obtain good signal error characteristics of the main signal, quick pull-in when the carrier signal is asynchronous, and prevention of erroneous switching of the line due to the residual error of the main signal and the residual error of the error pulse, the loop band of the carrier recovery circuit is required. There is a disadvantage that the optimum setting cannot be made according to each transmission signal.

[0007]

According to one aspect of the present invention, a carrier recovery circuit according to the present invention uses a reproduced carrier signal orthogonal to a composite modulated signal obtained by frequency-modulating a quadrature modulated signal with a service channel signal (hereinafter, referred to as SC signal). A multiplier that generates a baseband signal by performing quadrature synchronous detection; an A / D converter that generates a digital signal by performing an analog-to-digital conversion (hereinafter, A / D conversion) on each of the baseband signals; A discriminator that discriminates and demodulates the digital signal at a predetermined level and generates a phase difference information signal that is a phase difference between a carrier of the composite modulated wave signal and the reproduced carrier signal from the digital signal; An automatic phase control (APC) signal detection circuit for generating a reproduced carrier control information signal from an information signal, and low-pass filtering (Hereinafter, LPF) to receive the reproduced carrier control information signal, generate the reproduced carrier signal that reduces the phase difference of the phase difference signal, and generate a 90-degree signal to the local oscillation signal terminals of the two series of multipliers. A voltage controlled oscillator (VCO) supplied by a phase difference, and the digital signal is supplied from the A / D converter to detect an error pulse of the digital signal, and a bit error rate (BER) of the error pulse is detected. And an error pulse detection circuit that controls the band of the LPF according to the estimated error rate.

[0008] One of the carrier recovery circuits is the LPF.
The band of the LPF, which is continuously or stepwise expanded when the BER becomes larger than a predetermined error rate, can be continuously widened as the estimated BER becomes larger.

Another one of the carrier recovery circuits is the L
When the BER becomes smaller than a predetermined error rate, the band of the PF can be narrowed continuously or stepwise.

A carrier recovery circuit according to another aspect of the present invention converts a quadrature modulated signal into a service channel signal (hereinafter, referred to as a service channel signal).
A multiplier that generates a baseband signal by quadrature synchronous detection of a composite modulated wave signal that is further frequency-modulated by an SC signal) with a reproduced carrier signal that is orthogonal, and an analog-to-digital conversion (hereinafter, A) for each of the baseband signals. A / D converter that generates a digital signal by performing digital / digital conversion, discriminates and demodulates the two series of digital signals at a predetermined level, and performs a carrier wave of the composite modulated wave signal and a reproduced carrier wave signal from the digital signal. A classifier that generates a phase difference information signal that is a phase difference between
Receiving the reproduced carrier control information signal via an automatic phase control (hereinafter, APC) signal detection circuit for generating a reproduced carrier control information signal from the phase difference information signal and a low-pass filter (hereinafter, LPF); A voltage controlled oscillator (hereinafter referred to as VCO) which generates the reproduced carrier signal for reducing the phase difference of the phase difference signal and supplies it to the local oscillation signal terminals of the two series of multipliers with a phase difference of 90 degrees; An SC amplifier circuit that amplifies and demodulates the carrier control information signal from a detection circuit to a predetermined level to reproduce and output the SC signal, and controls the band of the LPF according to the detection level of the reproduced and output SC signal. An SC level detection circuit.

[0011] One of the carrier recovery circuits may have a configuration in which a reproduction output of the SC signal is detected by detecting a frequency modulation component of the carrier control information signal.

Another one of the carrier recovery circuits is the L
When the detection level of the reproduced and output SC signal is higher than a predetermined level, the band of the PF can be increased continuously or stepwise.

Still another one of the carrier recovery circuits is as follows.
When the detection level of the SC signal reproduced and output becomes lower than the predetermined level, the LPF band may be narrowed continuously or stepwise.

One of the LPFs is a series circuit of a first resistor connected between a signal input terminal and an output terminal, and a capacitor and a second resistor connected between the output terminal and a ground. Wherein the resistance value of the first resistor can be automatically changed by applying a control voltage.

In one of the LPFs, the first resistor is:
A configuration that is a diode can be employed.

Another one of the LPFs includes a first resistor connected between a signal input terminal and an output terminal, and a capacitor and a second resistor connected between the output terminal and ground. A lag-lead filter having a series circuit
Is selected when the system is controlled stepwise in a wide band, and the second system is selected when the band is controlled stepwise in a wide band.

Still another one of the carrier recovery circuits is as follows.
The error pulse detecting circuit is supplied with the digital signal from one of the A / D converters to identify an error pulse, and an error pulse identifier is supplied with the digital signal from the A / D converter to a predetermined level. A discriminator for discriminating and demodulating the error pulse, a comparator for comparing the discriminated error pulse with a demodulated output of the discriminator and outputting the error pulse, and the LPF according to an estimated error rate of BER of the error pulse. In place of the error pulse detection circuit for controlling the band of the above.

[0018]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a carrier recovery circuit according to the present invention. This figure shows a demodulator for the composite modulated wave signal.

The composite modulated wave signal having a microwave or the like as a carrier wave is received by an antenna, converted into an intermediate frequency signal (IF signal) Si having an appropriate frequency, and a multiplication circuit 1 which is a receiving head of a demodulator and 2 to 2 minutes (Sp and S
q) is input. The reproduced carrier signal S8 generated by the voltage controlled oscillator (VCO) 12 is supplied to the local oscillation signal terminals of the multiplier circuits 1 and 2 with a phase difference of 90 °. The multiplier 1 is supplied with a reproduced carrier signal S8a having a 90 ° phase delay, and the multiplier 2 is supplied with a reproduced carrier signal S8b having no phase delay. This phase difference is caused by the 90 ° phase shifter 11 inserted between the VCO 12 and the local oscillation signal terminal of the multiplier 1.

The multiplication circuits 1 and 2 provide IF signals Sp and S
q and the reproduced carrier signals S8a and S8b, respectively.
resulting in q1. The baseband signals Sp1 and Sq1 are low-pass filters (LPF) 3 for removing unnecessary waves such as harmonic components.
And 4 are analog-based baseband signals Sp2 and Sq2 band-limited by. Baseband signal S
p2 and Sq2 are respectively Sp Sp by amplifier circuits 5 and 6.
After being amplified to 3 and Sq3, they are converted into multivalued digital baseband signals (digital signals) Sp4 and Sq4 by A / D converters 7 and 8, respectively. A
The / D converter 7 or 8 (both A / D converters 7 and 8 may be used) also outputs the identification result Sd to the error pulse detection circuit 15 in order to detect an error pulse from the identification result.

The digital signals Sp4 and Sq4 are input to a discriminator 9, which discriminates the digital signals Sp4 and Sq.
After performing a predetermined signal conversion process on q4, a level determination is performed using the predetermined level as an identification point, and the determination result is output as encoded demodulated main signal data Dp and Dq, respectively. The discriminator 9 also outputs the reproduced carrier signal S8
A phase information signal S5, which is information for causing
Output to the C signal detection circuit 10. The detailed operation of the discriminator 9 will be described later.

The APC signal detection circuit 10 receives the phase information signal S5, performs a predetermined operation, and controls the frequency (phase) of the output S8 of the VCO 12 as a voltage controlled oscillator.
This produces the C signal S6. The APC signal S6 is sent to the variable band LPF 13 which almost defines the loop band of the phase locked loop that generates the reproduced carrier signal S8. The LPF 13 limits the APC signal S6 to a specified band. The band-limited APC signal S7 controls the frequency of the VCO 12 to generate a reproduced carrier signal S8. The detailed operation of the APC signal detection circuit 10 will also be described later.

The error pulse detection circuit 15 outputs error pulse generation information Se1 which is an error pulse generation status (equivalent to an estimated error rate) of the digital signal Sp4 or Sq4 to L.
Output to PF13. The band of the LPF 13 is controlled in accordance with error pulse generation information Se1 indicating the estimated error rate of the error pulse. When the band is controlled in accordance with the error pulse generation information Se1, the SC level detection circuit 1
The wiring of the SC signal information S1 from 7 is omitted. The details of the error pulse detection circuit 15 will be described later.

As described above, the demodulator shown in FIG. 1 finally demodulates the quadrature modulated wave signal by the discriminator 9 and outputs the demodulated result as demodulated main signal data Dp and Dq. Multiplication circuits 1, 2, LPF 3, 4, amplification circuits 5, 6, A / D converters 7, 8, discriminator 9, AP
The C signal detection circuit 10, the LPF 13 and the VCO 12 constitute the above-described phase locked loop (phase locked loop or PLL). That is, in the reproduced carrier wave reproducing circuit according to the embodiment of FIG. 1, the reproduced phase of the reproduced carrier wave signal S8 is synchronized with the IF signal Si by the above-mentioned phase synchronization circuit.

The demodulator of FIG. 1 also performs a demodulation operation on the SC signal.

The SC AMP circuit 14 generates an APC signal S6
From the carrier wave of the quadrature modulated wave signal, the SC signal further modulates the frequency component, which is the frequency-modulated portion by the SC signal, by using a known method,
The C signal Sc is extracted (reproduced: also referred to as demodulation). That is, the SC AMP circuit 14 receives the input APC signal S
6 is amplified to a predetermined level and demodulated and output as an SC signal Sc by a frequency modulation wave demodulation circuit. In addition,
The baseband band of the SC signal is 300 Hz to 12K
When the frequency is Hz, the loop band, which is the band of the phase locked loop, and the band of the LPF 16 need to have a band of up to several hundred KHz in order to pass the frequency-modulated SC signal. The APC signal S is output by the SC AMP circuit 14.
6 is amplified and demodulated, and the SC signal Sc is branched and output. The branch signal S9 passes through the BPF 16 that passes only the modulation frequency band of the SC signal Sc, and a level signal S10 of the SC signal Sc is obtained.

The SC level detection circuit 17 outputs the level signal S
10 levels are detected, and the level detection result SC
The signal information Sl is sent to the LPF 13. LPF13 is
The band is controlled according to the SC signal information S1. Note that S
When the band is controlled according to the C signal information S1, the error pulse generation information S from the error pulse detection circuit 15 is output.
The wiring of e1 is omitted.

One of the examples applicable as the above-described classifier 10 is disclosed in Japanese Patent Application Laid-Open No. 9-107384. This discriminator discriminates the levels of the digital signals Sp4 and Sq4 with the A / D converter, respectively. The levels of the digital signals Sp4 and Sq4 are determined to be approximately the intermediate level between the digital signals Sp4 and Sq4. That is, the MSB bit (first bit) of the multilevel output data is the main signal demodulation (in-phase) data Dp and the main signal demodulation (quadrature).
Output as data Dq.

The example disclosed in Japanese Patent Application Laid-Open No. 9-107384 can be applied to the APC signal detection circuit 10 described above. In this example, the phase information signal S5 output to the APC signal detection circuit 10 is obtained as the in-phase error data Ep and the quadrature error data Eq from the second bit of the multi-valued digital signal. That is, the APC signal detection circuit 10 takes an EX-OR gate of the in-phase data Dp and the quadrature error data Eq and an EX-OR gate of the quadrature data Dq and the quadrature error data Ep, respectively.
Add the outputs of the OR gates to produce the APC signal S6; As is well known, the APC signal S6 is composed of the phase of the carrier frequency f0 of the quadrature modulated signal and the reproduced carrier signal S8.
Is a voltage corresponding to the difference from the phase. Therefore, the APC signal S6 becomes a frequency control signal of the reproduced carrier signal S8 generated by the VCO 12.

One example applicable to the above-described error pulse detection circuit 15 is disclosed in Japanese Patent Application Laid-Open No. Hei 5-336182. The error pulse detection circuit shown in FIG. 1 of this publication uses an A / D converter corresponding to one of the A / D converters 7 or 8 of the present invention and an input baseband signal (Vesband of FIG. 1 of the present application). The signal A3 corresponds to the signal Sp3 or Sq3), and the A / D converter outputs an N-bit (N is an integer) digital signal. The MSB (first bit) of the digital signal identified as the multi-level signal becomes demodulated main signal data Dp or Dq. This error pulse detection circuit
When the N-bit digital signal is outside the determination area set in a predetermined range including the MSB identification point, an error pulse indicating a malfunction is output.

FIG. 2 is another block diagram of an example applicable to the error pulse detection circuit 15 of FIG. This error pulse detector 15A is disclosed in Japanese Unexamined Patent Publication No. Hei.
The configuration is basically the same as that of the error pulse detector of FIG.

The error pulse detector 15A is connected to the amplifier 5
Alternatively, the digital signal Sp3 or Sq3 from 6 is supplied to the error pulse discriminator 21 and the main signal discriminator 9A.
The main signal discriminator 9A and the demodulated main signal data D output therefrom are the same as the discriminator 9 and the demodulated main signal data Dp and Dq described with reference to FIG. The error pulse discriminator 21 has the same configuration as the discriminator 9A, but sets the discrimination level to a level at which an error pulse is likely to occur. The comparator 22 compares the output of the discriminator 9A with the output of the error pulse discriminator 21, and outputs an error pulse Se2 when both are different. Therefore, the error pulse detector 15A is different from the error pulse detection circuit disclosed in FIG.
When digital signals Sp3 or Sq3 having the same communication quality are supplied, the BER tends to be large. Therefore, there is an effect that a situation in which line switching is required can be quickly grasped.

The LPF which is an important feature of the present invention is
The thirteenth band control will be described in detail. FIG. 3 is a circuit diagram of the LPF 13 used in the embodiment of FIG.

A LP filter is used as the LPF 13. The lagged filter includes a first resistor connected between an input terminal and an output terminal of a signal, and a series circuit of a capacitor and a second resistor connected between the output terminal and ground. 3 is a first resistor connected between the input terminal of the APC signal S6 and the output terminal of the LPF 13, that is, a diode D1 such as a PIN diode or the like having a resistive property in the operating frequency band. And resistor R
And a series circuit of a capacitor C1 and a second resistor R4 connected between the output terminal of the LPF 13 and the ground.

When a voltage is applied to the diode D1 of the first resistor, the resistance value of the first resistor changes. For example, when a positive potential is applied to a connection point between the diode D1 and the resistor R2, a reverse voltage is applied to the diode D1 to increase the resistance value, and the band of the lag filter is narrowed. Conversely, when a negative potential is applied to the connection point between the diode D1 and the resistor R2, the resistance of the diode D1 to which a forward voltage is applied decreases, and the band of the lag filter increases. Note that, even if the diode D1 and the resistor R2 are exchanged, a variable resistor (first resistor) can be realized similarly.

If a variable capacitance diode (also called a varactor diode or a varicap) capable of changing the interelectrode capacitance is used for the capacitor C1 instead of the fixed capacitor, the band can be changed similarly to the diode D1. If the polarity of the diode D1 or the variable capacitance diode is connected in the opposite direction, the polarity of the applied voltage is opposite in the wide band. That is, when a variable capacitance diode whose capacity can be changed is used in place of the diode D1 or the capacitor C1 exhibiting resistive properties such as a PIN diode,
The band of the LPF 13 can be continuously changed by a continuous change of a voltage applied to a connection point between the diode D1 and the resistor R2.

The LPF 13 is connected to the SC level detection circuit 1 from the error pulse detection circuit 15 as the voltage application terminal.
Although two terminals from 7 are provided, only one of the terminals is used in the embodiment of FIG. The error pulse detection circuit 15 supplies the error pulse generation information Se1 to the band-pass filter 31 to pass only a prescribed frequency component. The error pulse generation information that has passed through the band-pass filter 31 is further applied to the diode D1 via the resistor R1 with a value (voltage) integrated by the integrator 32 at predetermined time intervals.

In order to change the band of the LPF 13 stepwise, a threshold value (a level setting value of a predetermined error rate) of the integrated value of the error pulse generation information Se1 is provided, and a comparator determines whether or not the integrated voltage exceeds the threshold value. (Not shown).
The voltage applied to the diode D1 is changed in two steps according to the result of this determination, and the band of the LPF 13 is changed in two steps. It is needless to say that the number of stages can be changed by appropriate circuit design.

The SC level detection circuit 17 outputs S
The C signal information Sl is directly input to the resistor R1, and the LPF 13
Is set to a band corresponding to the SC signal information Sl, that is, the level of the SC signal Sc output from the SC level detection circuit 17. As described above, the level of the SC signal Sc can change both continuously and stepwise.

Referring again to FIG. 1, the band control of the LPF 13 by the error pulse generation information Se1 will be described.

If the BER of the demodulated main signal data Dp and Dq from the discriminator 9 is larger than a predetermined error rate, the error pulse detection circuit 15 generates error pulse generation information Se1 of a negative pulse.
Is generated in a short time. Then, the output of the integrator 32 gives a large negative potential to the resistor R1, and the resistance value of the diode D1 becomes low, so that the band of the LPF 13 becomes wide. That is, the fact that the BER of the demodulated main signal data Dp and Dq is large means that although the SC signal is included in the composite modulated signal, the loop band is narrow, and the carrier signal cannot follow the SC signal, It is conceivable that the carrier signal reproduction is insufficient or that the carrier wave is out of synchronization. Therefore, the band of the LPF 13 is widened to the extent that the carrier signal can be sufficiently reproduced, and the carrier wave is quickly drawn.

On the other hand, B of demodulated main signal data Dp and Dq
When the ER is sufficiently smaller than the predetermined error rate, the above-described problem does not occur. Therefore, the error pulse detection circuit 15
Generates error pulse generation information Se1 of a positive pulse. Then, the output of the integrator 32 gives a positive potential to the resistor R1, and the resistance value of the diode D1 increases.
The band of No. 3 becomes narrow. That is, when the BER of the demodulated main signal data Dp and Dq is sufficiently smaller than the predetermined error rate,
It is considered that there was no input of the C signal and the carrier signal reproduction was normally performed. Therefore, at this time, if the band of the LPF 13 is narrowed, the frequency offset is reduced, and the BER is further improved. Although the above-described band control of the LPF 13 is performed continuously, it is possible to control the band to an appropriate band stepwise as described above.

Next, the LPF 13 based on the SC signal information Sl
Will be described.

When the level signal S10 is higher than a predetermined level, the SC level detection circuit 17 sends to the LPF 13 SC signal information Sl indicating that the SC signal Sc is included in the composite modulated wave signal (IF signal Si). . When receiving the SC signal information Sl from the SC level detection circuit 17, the LPF
Reference numeral 13 broadens the loop band of the phase locked loop so that the SC signal Sc can pass through. That is, the SC level detection circuit 1
7 sends the negative potential SC signal information Sl to the LPF 13 to broaden the band of the LPF 13 and
A carrier signal can be reproduced by setting a band through which the C signal can pass.

On the other hand, when detecting that the level signal S10 is lower than the above-mentioned predetermined level, the SC level detection circuit 17 determines that the composite modulated wave signal does not include the SC signal Sc. The SC signal information S1 from the SC level detection circuit 17 is supplied with an appropriate potential to the LPF 13 to narrow the band of the LPF 13 and control the band of the LPF 13 to an optimum width for demodulating the quadrature modulated signal. I do. In normal operation, this band can be narrower than when the SC signal Sc is included, and the residual error can be reduced.
ER is obtained. The LPF based on the SC signal information S1
Thirteen band control can be performed continuously or stepwise.

FIG. 4 shows the LPF 1 in the embodiment of FIG.
FIG. 13 is a circuit diagram of an LPF 13A that can be used in place of FIG.

The LPF 13A switches between a wide band and a narrow band LPF 13a and LPF 13b by a switch SW1 to switch between a wide band and a narrow band.
The APC signal S6 is supplied to the input terminal of the switch SW1, and the SC signal information S1 or the error pulse detection circuit 15
Control of the error pulse generation information Se1 from the
Switching to F13a or LPF13b. The error pulse generation information Se1 passes between the switch SW1 and the BPF 31 and the integrator 32 described above. The APC signal S6 becomes an APC signal S7 whose band is limited through the LPF 13a or the LPF 13b. The LPF 13a
And the band-limiting frequency of the LPF 13b is determined by the resistor R1
2, R13, R14, and R15 are represented by r1
2, r13, r14 and r15, and the capacitance values of the capacitors C11 and C12 are c11 and c12, respectively, then (r12 + r13) × c11 or (r14 + r
15) Starts early from the larger of xc12.

[0049]

As described above, the carrier recovery circuit according to one embodiment of the present invention performs orthogonal synchronous detection on a composite modulated wave signal obtained by further frequency-modulating a quadrature modulated wave signal with an SC signal, using a orthogonally reproduced carrier signal. A multiplier that generates a band signal, an A / D converter that generates a digital signal by A / D-converting each of the baseband signals, and demodulates and identifies the two series of digital signals at a predetermined level. A discriminator for generating a phase difference information signal which is a phase difference between the carrier of the composite modulated wave signal and the reproduced carrier signal from the digital signal, and an APC signal detection for generating a reproduced carrier control information signal from the phase difference information signal And a circuit for receiving the reproduced carrier control information signal via an LPF and reducing the phase difference of the phase difference signal. VC supplied with 90 degree phase difference to the local oscillation signal terminal of the multiplier 2 sequence occurs a carrier signal
O, and an error pulse detection circuit that receives the digital signal from the A / D converter, detects an error pulse of the digital signal, and controls the band of the LPF according to the estimated error rate of the BER of the error pulse. Therefore, when the SC signal is included in the composite modulated wave signal, the loop band is widened so that the carrier signal can be sufficiently reproduced, and the carrier wave pull-in can be performed quickly when the carrier wave is out of synchronization. There is an effect that can be. Further, when the BER error rate is lower than a predetermined error rate, there is an effect that the BER can be further improved by narrowing the band of the LPF.

If the carrier recovery circuit uses an error pulse detection circuit described in Japanese Patent Application Laid-Open No. H5-207089, an increase in the residual error of the error pulse can be detected at an early stage. It also has the effect of preventing switching.

Further, a carrier recovery circuit according to another aspect of the present invention provides a baseband signal by performing quadrature synchronous detection on a composite carrier signal obtained by frequency-modulating a quadrature modulated signal with an SC signal and using a reproduced carrier signal that is orthogonal. Each of the resulting multipliers and each of the baseband signals are A / D
An A / D converter for converting to produce a digital signal;
A discriminator that discriminates and demodulates the two series of digital signals at a predetermined level and generates a phase difference information signal that is a phase difference between a carrier wave of the composite modulated wave signal and the reproduced carrier wave signal from the digital signals; An APC signal detection circuit for generating a reproduced carrier control information signal from the phase difference information signal; receiving the reproduced carrier control information signal via an LPF and generating the reproduced carrier signal for reducing a phase difference of the phase difference signal; A VCO that supplies a local oscillation signal terminal of the two series of multipliers with a phase difference of 90 degrees, and amplifies and demodulates the carrier control information signal from the APC signal detection circuit to a predetermined level to demodulate the SC signal. An SC amplifier circuit for reproducing and outputting, and an S for controlling a band of the LPF according to a detection level of the reproduced and output SC signal.
Since a C level detection circuit is provided, when transmitting an SC signal, the band of the LPF can be widened so that the carrier signal can follow the SC signal, and the carrier signal can be sufficiently reproduced. In addition, there is an effect that it is possible to quickly pull in synchronization when the carrier wave is out of synchronization, and it is possible to reduce the occurrence of residual errors. Further, when the SC signal is not included, there is an effect that the band can be narrowed, the residual error is reduced, and a good BER is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a carrier recovery circuit according to the present invention.

FIG. 2 is a block diagram of an error pulse detector 15A that can be used in the embodiment of FIG.

FIG. 3 is a circuit diagram of an LPF 13 used in the embodiment of FIG.

FIG. 4 is a circuit diagram of an LPF 13A that can be used in place of the LPF 13 of FIG.

[Explanation of symbols]

 1, 2 Multiplier 3, 4, 13, 13A Low-pass filter (LPF) 5, 6 Amplification circuit 7, 8 A / D converter 9, 9A Discriminator 10 APC signal detection circuit 11 Phase shifter 12 Voltage control Oscillator (VCO) 14 SC AMP circuit 15 Error pulse detection circuit 16, 31 Band-pass filter 17 SC level detection circuit 21 Error pulse discriminator 22 Comparator 32 Integrator C1, C11, C12 Capacitor D1 Diodes R1 to R4 R12-R15 resistor SW1 switch

Claims (11)

[Claims] A multiplier for performing a quadrature synchronous detection of a composite modulated wave signal obtained by further frequency-modulating the quadrature modulated wave signal with a service channel signal (hereinafter, referred to as SC signal) by a reproduced carrier signal orthogonal to generate a baseband signal; An analog-to-digital converter (hereinafter, A / D conversion) for each of the baseband signals to generate a digital signal; a two-series digital signal identified and demodulated at a predetermined level; An identifier for generating a phase difference information signal which is a phase difference between a carrier of the composite modulated wave signal and the reproduced carrier signal from the digital signal, and an automatic phase control for generating a reproduced carrier control information signal from the phase difference information signal , APC) signal detection circuit and a low-pass filter (hereinafter, LPF) through which the reproduced carrier control information signal is transmitted. And a voltage-controlled oscillator (hereinafter referred to as VCO) which generates the reproduced carrier signal for reducing the phase difference of the phase difference signal and supplies the reproduced carrier signal to the local oscillation signal terminals of the two series of multipliers with a phase difference of 90 degrees. An error pulse which receives the digital signal from the A / D converter, detects an error pulse of the digital signal, and controls a band of the LPF according to an estimated error rate of a bit error rate (hereinafter, BER) of the error pulse. A carrier recovery circuit, comprising: a detection circuit. 2. The carrier recovery circuit according to claim 1, wherein the band of the LPF is increased continuously or stepwise when the BER exceeds a predetermined error rate. 3. The carrier recovery circuit according to claim 1, wherein the band of the LPF is narrowed continuously or stepwise when the BER becomes smaller than a predetermined error rate. 4. A multiplier that performs quadrature synchronous detection on a composite modulated wave signal obtained by further frequency-modulating the quadrature modulated wave signal with a service channel signal (hereinafter, referred to as SC signal) by a reproduced carrier signal orthogonal to generate a baseband signal. An analog-to-digital converter (hereinafter, A / D conversion) for each of the baseband signals to generate a digital signal; a two-series digital signal identified and demodulated at a predetermined level; An identifier for generating a phase difference information signal which is a phase difference between a carrier of the composite modulated wave signal and the reproduced carrier signal from the digital signal, and an automatic phase control for generating a reproduced carrier control information signal from the phase difference information signal , APC) signal detection circuit and a low-pass filter (hereinafter, LPF) through which the reproduced carrier control information signal is transmitted. And a voltage-controlled oscillator (hereinafter referred to as VCO) which generates the reproduced carrier signal for reducing the phase difference of the phase difference signal and supplies the reproduced carrier signal to the local oscillation signal terminals of the two series of multipliers with a phase difference of 90 degrees. An SC amplifier circuit that amplifies and demodulates the carrier control information signal from the APC signal detection circuit to a predetermined level and reproduces and outputs the SC signal; and the LPF according to the detection level of the reproduced and output SC signal. A carrier recovery circuit comprising: an SC level detection circuit for controlling a band. 5. The carrier recovery circuit according to claim 4, wherein a reproduction output of the SC signal is extracted by detecting a frequency modulation component of the carrier control information signal. 6. The carrier recovery according to claim 4, wherein the band of the LPF is increased continuously or stepwise when the detection level of the reproduced and output SC signal becomes higher than a predetermined level. circuit. 7. The carrier wave reproduction according to claim 4, wherein the band of the LPF is narrowed continuously or stepwise when the detection level of the reproduced SC signal is lower than a predetermined level. circuit. 8. A series circuit comprising a first resistor connected between an input terminal and an output terminal of a signal, a capacitor connected between the output terminal and ground, and a second resistor. The carrier regeneration according to claim 1, wherein the resistance value of the first resistor can be automatically changed by applying a control voltage. circuit. 9. The carrier recovery circuit according to claim 8, wherein said first resistor is a diode. 10. An LPF comprising: a first resistor connected between a signal input terminal and a signal output terminal; and a series circuit of a capacitor and a second resistor connected between the output terminal and ground. The first system is selected when the band is controlled stepwise over a wide band, and the second system is selected when the band is controlled stepwise over a wide band. The carrier recovery circuit according to claim 1, wherein the carrier recovery circuit comprises: 11. The error pulse detection circuit according to claim 11, wherein
An error pulse discriminator supplied with the digital signal from one of the / D converters to identify an error pulse;
A discriminator supplied with the digital signal from the A / D converter and discriminating and demodulating the discriminated signal at a predetermined level; and a comparator for comparing the discriminated error pulse with a demodulated output of the discriminator and outputting the error pulse. 2. A carrier wave recovery circuit according to claim 1, wherein said error pulse detection circuit controls said LPF band in accordance with a BER estimation error rate of said error pulse.