JP2000236364A - Digital demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute more shorted frequency pulling processing by compensating frequency detuning at the time of channel tuning. SOLUTION: An error detecting part 105 detects a frequency error in digital in-phase and quadrature signal and stores the detected error. In response to a control signal, a stored frequency error 121 is outputted. On the basis of a reproducing signal 181, a carrier reproducing part 107 generates digital demodulation signals 123 and 125 by applying complex multiplying processing to the digital in-phase and quadrature signal. On the basis of the stored frequency error 121, data 163 provided by applying phase detecting and smoothing processing to the digital demodulation signals are corrected and a regenerative signal is newly generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital demodulator, and more particularly, to a digital demodulator capable of implementing a process of compensating for frequency detuning during channel selection in a short time.

[0002]

2. Description of the Related Art Digital modulation and demodulation techniques have attracted attention. In a receiver, a digital demodulator is required to flexibly cope with detuning from a reference frequency in a transmitter.

As a known technique related to the present invention, Japanese Patent Application Laid-Open No. Hei 6-78009 discloses a technique relating to a carrier recovery circuit for digitally modulated waves. This carrier recovery circuit substantially eliminates frequency detuning at the input of a low-pass filter as spectral shaping means.

In Japanese Patent Application Laid-Open No. 8-335959,
A technique related to a digital demodulator that compensates for frequency detuning of a digital modulation signal is disclosed. Further, this digital demodulator compensates for the frequency deviation of the I and Q baseband signals due to the frequency deviation of the intermediate frequency that occurs after the establishment of the carrier recovery processing.

FIG. 6 shows a conventional digital demodulator. The outline of the operation of the digital demodulator is described below.

An n-phase shift keying (PSK) signal 201 as an input signal is a PLL (Phase Locked Loo
p) Quadrature quasi-synchronous detection is performed based on the local oscillation frequency of the circuit 207. The local oscillation frequency is calculated by the arithmetic unit (CPU) 2
Signal 205 generated based on the tuning data from
Is determined according to

The quadrature quasi-coherently detected n-phase phase shift keying (PSK) signal is quadrature-coherently detected by a local oscillation frequency 213 via a band-pass filter 211, and an in-phase (In-Phase) signal (I signal) ) And orthogonal (Quadratu
re) A signal (Q signal) is generated. Each of the I signal and the Q signal is converted into a digital signal by each of the analog-to-digital converters 221 and 223. Converted I
Each of the signal and the Q signal is spectrally shaped by each of the digital low-pass filters 225 and 227.

A complex multiplier 229 performs a complex multiplication process on the spectrally shaped I signal and Q signal based on the reproduced signal 244. At this time, the complex multiplied I signal 245
And the Q signal 247 are output as demodulated signals.

On the other hand, the phase detector 231 and the loop filter 233 provide the complex multiplied I signal 245 and Q signal 2
A phase difference is detected from 47, and a smoothing process is performed on the detected phase difference. The frequency error detection circuit 235 detects a frequency error from the complex multiplied I signal 245 and Q signal 247. The detected frequency error is the input n-phase P
This is detected as a frequency detuning between the frequency in the SK signal 201 and the local oscillation frequency in the quadrature quasi-synchronous detection.

[0010] Further, the detected phase difference is corrected based on the detected frequency error. The corrected phase difference is
It is input to a frequency control terminal of a numerically controlled oscillator (NCO) 239 and subjected to addition processing. The added phase difference is used as a data conversion circuit (COS,
And SIN) 241 and 243 to generate a new reproduced signal (not shown).

The complex multiplier 229, phase detector 231, loop filter 233, NCO 239, COS 241 and SIN 243 execute one cycle of processing as a digital PLL system. When a circuit of a complete integration system is adopted as the loop filter 233, the frequency pull-in range (frequency pull-up range) of the digital PLL becomes infinite. Therefore, an ideal operation as a digital PLL system is realized.

In digital satellite broadcasting technology, a dielectric resonator is employed as a local oscillator of a BS converter.
Thus, the frequency of the local oscillator detunes from the reference frequency. This detuning frequency can reach several MHz.
Further, the oscillation frequency of the local oscillator detunes due to a change in environmental temperature when the power is turned on, in addition to the average frequency detuning from the reference frequency. These frequency drifts cannot be ignored. Therefore, frequency detuning appears at the input stage of the demodulation device.

The input n-phase PSK signal is converted into a digital signal, and then converted to a digital low-pass filter 2.
25 and 227. The frequency characteristics of the low-pass filters 225 and 227 are symmetric with respect to DC. Therefore, the spectrum is partially cut off based on the frequency detuning. This indicates that transmission characteristics for preventing intersymbol interference are not satisfied. Therefore, the feedback control approaches an unstable state, and the jitter characteristic and the pull-in range deteriorate.

In the conventional system shown in FIG. 6, the above-mentioned problem is solved by the frequency error detection circuit 235. During the frequency pull-in process, the phase difference is corrected within the pull-in range of the digital PLL system.

A digital demodulator for compensating for frequency detuning during channel selection is desired. It is also desirable that the digital demodulation device has a function for executing the phase difference correction process when the phase synchronization of the digital PLL is released. Further, it is desired that the digital demodulation apparatus be realized by paying attention to the fact that the frequency detuning after the power is turned on does not greatly change every channel selection. or,
Further, it is desired that the digital demodulation device executes the frequency pull-in process in a short time when the phase synchronization is released.

[0016]

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital demodulator for compensating for frequency detuning during channel selection. Another object of the present invention is to
Another object of the present invention is to provide a digital demodulation device having a function for executing the phase difference correction processing when the phase synchronization of the digital PLL is released. Still another object of the present invention is to provide a digital demodulator by focusing on a change in frequency drift after power is turned on. Still another object of the present invention is to provide a digital demodulation device which executes a frequency pull-in process in a short time when phase synchronization is released.

[0017]

In order to achieve the above object, a digital demodulator according to the present invention (see FIG. 1) comprises an arithmetic operation unit (101), a demodulation unit (103), and an error detection unit (1).
05) and a carrier recovery unit (107).

In response to the channel selection data (109), the arithmetic section (101) outputs a channel switching signal (111) indicating a change in the oscillation frequency and a control signal (113) notifying the change in the channel. I do. The demodulation unit (103)
Based on the channel switching signal (111), the input modulated signal (115) is subjected to quadrature demodulation processing to generate a digital in-phase signal (117) and a digital quadrature signal (119). The digital in-phase signal (117) and the digital quadrature signal (119) are baseband signals.

The error detecting section (105) detects a frequency error in the digital in-phase signal (117) and the digital quadrature signal (119). The error detection unit (105)
The detected frequency error is stored. Error detector (10
5) outputs the stored frequency error (171) in response to the control signal (113).

The carrier reproducing section (107) outputs the reproduced signal (1).
81, see FIG. 2) based on the digital in-phase signal (1).
17) and the digital orthogonal signal (119) are subjected to complex multiplication processing to generate digital demodulated signals (123, 125). The carrier recovery unit (107) corrects data (163, see FIG. 2) obtained by performing phase detection and smoothing processing on the digital demodulated signal based on the stored frequency error (121 (171)). , A new reproduction signal is generated.

Further, it is preferable that the error detecting section (105) (see FIG. 2) includes a detecting means (165), a delay means (169) and a switching means (172).
The detecting means (165) outputs the digital in-phase signal (117)
And a digital orthogonal signal (119) are input to detect a frequency error.

The delay means (169) stores the detected frequency error (167) so as to be output when the control signal (113) is generated. The switching means (172)
In response to the control signal (113), the output processing of the frequency error (167) detected after the generation of the control signal (113) is switched to the output processing of the stored frequency error (171). In this case, the detected frequency error (167) is
Detection is performed based on the frequency of the input modulated signal (115) and the local oscillation frequency (related to 126) in the orthogonal quasi-synchronous detection in the orthogonal demodulation processing.

Further, the carrier recovery section (107) (see FIG. 2) includes a complex multiplication means (157) and a phase error detection /
Smoothing means (159 and 161) and correction means (17
3) and reproducing means (175, 177 and 179).

The complex multiplying means (157) executes the above-described complex multiplying process, and generates a digital demodulated signal (123, 1).
25) Output. Phase difference detection / smoothing means (159)
Detects the phase difference based on the digital demodulated signals (123, 125). Phase difference detection / smoothing means (161)
Performs a smoothing process on the detected phase difference data (160). In this case, the detected phase difference (detected phase difference data (160)) corresponds to the input modulated signal (115).
And a signal (176) related to the reproduction signal (181).

The correcting means (173) corrects the smoothed phase difference data (163) based on the stored frequency error (121 (171)). Reproduction means (175,
177 and 179) are the corrected phase difference data (17
In response to 4), a new reproduction signal (not shown) is generated.

When the system according to the above configuration is realized, data (163) obtained by performing the phase difference detection and smoothing processing based on the stored frequency error is formed by the carrier reproduction unit (107). It is corrected within the frequency lock-in range in a digital phase locked loop (Phase Locked Loop) system.

Further, at the time of channel switching after the power is turned on, the frequency pull-in time is shortened by diverting the locked frequency error (the stored frequency error (171)) before channel selection. In the above configuration, it is preferable that the input modulation signal (115) is a multiple phase shift keying (PSK) signal.

It should be noted that the reference numerals given to the above constituent elements are for facilitating the understanding of the present invention, and should not be taken into account when interpreting the claims.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the digital demodulator according to the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 shows a conceptual diagram of a digital demodulator according to the present invention.

The digital demodulator according to the present invention has a
01, a demodulation unit 103, an error detection unit 105, and a carrier reproduction unit 107. The arithmetic unit 101 responds to the channel selection data 109 by sending the channel switching signal 1
11 and a control signal 113 are output. The channel switching signal 111 gives an oscillation frequency to be changed. The channel control signal 113 notifies the switching of the channel.

The demodulation unit 103 comprises first, second and third means. The first means is that the channel switching signal 111
, The input modulated signal 115 is subjected to quadrature demodulation processing to generate an in-phase signal (I signal) 141 and a quadrature signal (Q signal) 143. Details of the quadrature demodulation processing will be described later.

The second means converts each of the in-phase signal 141 and the quadrature signal 145 into a digital signal. The third means performs a spectrum shaping process on each of the converted in-phase signal 149 and the converted quadrature signal 151, and executes a spectrum-shaped in-phase signal (digital in-phase signal) 117.
And a spectrum-shaped orthogonal signal (digital orthogonal signal) 119.

The error detector 105 detects a frequency error in the digital in-phase signal 117 and the digital quadrature signal 119. The error detection unit 105 stores the detected frequency error in order to cope with the channel switching (when the control signal 113 is generated). Error detecting section 105 outputs stored frequency error 121 in response to control signal 113.

[0034] The carrier recovery section 107 outputs the reproduced signal (18).
1, see FIG. 2), the spectrum-shaped in-phase signal 117 and the spectrum-shaped quadrature signal 119 are subjected to complex multiplication processing to obtain a complex multiplied in-phase signal 123 and a complex multiplied quadrature signal 125. (Digital demodulated signal).

When the control signal 113 is generated, the carrier recovery unit 107 detects a phase difference and smoothes the complex multiplied in-phase signal 123 and the complex multiplied quadrature signal 125 based on the stored frequency error 121. The data (163, see FIG. 2) obtained by performing the processing is corrected, and a new reproduction signal is generated.

FIG. 2 shows a block diagram of a digital demodulator according to the first embodiment of the present invention. The configuration of this digital demodulation device is described corresponding to the conceptual diagram shown in FIG.

The operation at the time of channel switching is controlled by a central control unit (CPU (arithmetic unit)) 101 '. CP
U101 ′ responds to the channel selection data 109,
It outputs a channel switching signal 111 and a control signal 113. The channel selection data 109 is externally input. The channel switching signal 111 is an oscillation frequency (first oscillation frequency) corresponding to the channel indicated by the channel selection data 109.
give.

In the demodulation section 103, the first means described above is a PLL (Phase Locked Loop) circuit 126
, A mixer circuit 127, and a band-pass filter (BP
F) 131, a fixed frequency oscillator 135, a mixer circuit 136, a 90 ° phase shifter (π / 2) 137, and a mixer circuit 140.

The PLL circuit 126 generates a signal (not shown) for providing the first oscillation frequency based on the channel switching signal 111. The orthogonal quasi-synchronous detection processing is executed based on the first oscillation frequency. The mixer circuit 127 converts the frequency of the input modulation signal 115 into an intermediate frequency band based on the first oscillation frequency. In the present embodiment, input modulation signal 115 is an n-phase phase shift keying (PSK) signal.

The frequency-converted signal 129 is output from the BPF 1
After the filtering processing of 31, the quadrature synchronous detection processing according to the second oscillation frequency is performed. A signal (not shown) providing the second oscillation frequency is generated by fixed frequency oscillator 135. The band pass signal 131 is split into two.

One frequency of the split bandpass signal is frequency-converted by the mixer circuit 136 based on the second oscillation frequency. The other frequency of the split bandpass signal is frequency-converted by mixer circuit 140 based on the frequency of 90 ° phase shift signal 139. 90 °
The phase shift signal 139 is a signal giving the second oscillation frequency of 9
It is generated by performing a 0 ° phase shift process.

The in-phase signal 141 and the quadrature signal 143 are generated by performing quadrature demodulation on the input modulated signal 115 based on the channel switching signal 111. In-phase signal 1
41 and the orthogonal signal 143 are baseband signals.

The above-mentioned second means is constituted by analog / digital converters (A / D) 145 and 147. The A / D 145 converts the in-phase signal 141 into a digital signal, and outputs it as a converted in-phase signal 149. The A / D 147 converts the orthogonal signal 145 into a digital signal, and outputs the digital signal as the converted orthogonal signal 151.

The above-mentioned third means is constituted by digital low-pass filters (LPF) 153 and 155. The LPF 153 performs a spectrum shaping process on the converted in-phase signal 149. The LPF 155 performs a spectrum shaping process on the converted orthogonal signal 151.

The LPF 153 and the LPF 155 have substantially the same frequency characteristics. LPFs 153 and 155
Have transmission characteristics required to prevent intersymbol interference in digital data transmission. Further, LPFs 153 and 1
55 is designed so as to obtain a roll-off characteristic in consideration of the filter characteristics and combination of the transmitter.

Although not shown in FIG. 2, the clock recovery circuit receives the spectrum-shaped in-phase signal 117 and the spectrum-shaped quadrature signal 119 and extracts a symbol timing component from the signal. The extracted symbol timing components are fed back to the conversion timing clock input units of the A / Ds 145 and 147.

The error detecting section 105 comprises a frequency error detecting circuit 165, a delay circuit 169 and a switching circuit 172. The frequency error detection circuit 165 receives the spectrally shaped in-phase and quadrature signals (117 and 119) and detects a frequency error. Frequency error detection circuit 16
5 detects a frequency error corresponding to the channel selection data 109 (channel switching signal 111).

The delay circuit 169 stores the detected frequency error 167 in order to cope with the channel switching. When the control signal 113 is generated, the switching circuit 172 detects the frequency error 16 detected after the control signal 113 is generated.
7 is switched to the output processing of the stored frequency error 171. The switching circuit 172 outputs a frequency error 171 detected before the channel switching in response to the control signal 113.

The channel switching signal 111 (control signal 11
In response to 3), a quadrature synchronous detection process is performed. The frequency error detection circuit 165 detects a frequency error at the time of the quadrature synchronous detection process corresponding to the channel switching.

The switching circuit 121 responds to the control signal 113 by using the frequency error 171 stored in the delay circuit 169.
Is output. The detected frequency error 167 is related to the difference between the frequency of the input modulated signal 115 and the first oscillation frequency in the above-described quadrature quasi-synchronous detection.

The carrier recovery unit 107 includes a complex multiplier 157
A phase detector 159, a loop filter 161, a correction circuit 173, a numerically controlled oscillator (NCO) 175,
Data conversion circuit (COS) 177 having COS characteristics and data conversion circuit (SIN) 179 having SIN characteristics
It is composed of The carrier recovery unit 107 forms a digital PLL system.

The complex multiplier 157 performs a complex multiplication process based on the reproduced signal 181, and outputs a complex multiplied in-phase signal 123 and a complex multiplied quadrature signal 125 as demodulated signals. Complex multiplier 157 executes the same processing as the frequency conversion processing by fixed frequency oscillator 135 and mixer (136, 140) in the baseband.

The phase detector 159 receives the complex multiplied in-phase signal 123 and the complex multiplied quadrature signal 125 and detects a phase difference. The loop filter 161 receives the detected phase difference data 160 and executes a smoothing process. As the loop filter 161, a circuit having a complete integration system is employed.

When the control signal 113 is generated, the correction circuit 173 corrects the smoothed phase difference data 163 based on the stored frequency error 121 (171).
The correction circuit 173 corrects the smoothed phase difference data 163 based on the stored frequency error 121 such that the frequency of the smoothed phase difference data 163 falls within the frequency pull-in range in the digital PLL system.

The numerically controlled oscillator 175 inputs the corrected phase difference data 174 to its frequency control input section and outputs a numerically controlled signal 176. The detected phase difference (detected phase difference data 160) gives a phase difference between the input modulation signal 115 and the numerical control signal 176.

The numerically controlled oscillator 175 is a cumulative addition circuit that allows an overflow. Numerically controlled oscillator 175
Performs an addition operation up to the dynamic range according to the value of the corrected phase difference data 174. The numerically controlled oscillator 175 is a voltage controlled oscillator (VC
The same processing as in O) is performed.

The numerical control signal 176 branches. One of the branched numerical control signals 176 is input to a data conversion circuit 177 having COS characteristics. The other of the branched numerical control signals 176 is input to a data conversion circuit 179 having SIN characteristics. Data conversion circuit (177, 1
79) are input to the complex multiplier 157 as new reproduced signals.

FIGS. 3 and 4 are flowcharts showing the operation of the digital demodulation circuit according to the present embodiment. The operation of the digital demodulation circuit according to the present embodiment will be described with reference to FIGS. 3 and 4, the flow of time is considered.

At the start of the system, channel selection data 109 is externally input (step S101).
The above-described quadrature demodulation processing is executed based on the channel switching signal 111 corresponding to the channel selection data 109 (step S102).

Next, a frequency error detection process is executed.
The detected frequency error 167 is output for generating a reproduction signal (step S103). Further, the detected frequency error 167 is stored as "previous frequency error" (step 104).

At substantially the same time as the processing in step S103, the complex multiplied in-phase signal 123 and the complex multiplied quadrature signal 125 are output as demodulated signals. The phase detection and smoothing processing are performed, and the smoothed phase difference data 163 is output (step S105).

[0062] The smoothed phase difference data 163 is corrected based on the detected frequency error (step S1).
06). A reproduction signal 181 is output based on the corrected phase difference data 174 (step S107).

By the above processing, a frequency pull-in operation as a digital PLL system is executed. Therefore, in the stationary state where the channel is fixed, the demodulated signal (12
3, 125) is generated (step S108). In this state, the phase of the digital PLL system is locked.

Next, a channel change request (control signal 11
When 3) is generated (step S109), the stored “pre-frequency error” 171 is output in response to the control signal 113 (step S110). At this point, the phase locked state of the digital PLL system is released.
At substantially the same time as step S110, quadrature demodulation processing accompanying the channel change is executed (step S11).
1).

In the time interval T, “pre-frequency error” 1
Based on 71, a correction process is performed on the smoothed phase difference data 163 before the channel change (step S112). The time interval T is a substantial time difference between the time when the “pre-frequency error” 171 is output in response to the control signal 113 and the time when the smoothed phase difference data after the channel change is first output. Show.

After step S112, a new reproduction signal is generated based on the corrected phase difference data 174 (step S114), and a demodulated signal is output (step S115).

After step S111, a phase difference detection and smoothing process is performed, and the smoothed phase difference data after the channel change is output (step S113).

[0068] The smoothed phase difference data after the channel change is corrected based on the "pre-frequency error" (step S116). A new reproduction signal is generated based on the corrected phase difference data 174 (step S117),
A demodulated signal is output (step S118).

After step S111, a frequency error detection process is executed (step S119). The detected frequency error 167 is stored as "current frequency error" (step S120). "Current frequency error" is the frequency error detected after the channel change. “Current frequency error” corresponds to “previous frequency error” in step S104.

In the same manner, when a new channel is selected, a frequency pull-in process is executed based on the stored frequency error 171. Therefore, the time of the frequency pull-in process is reduced.

FIG. 5 shows a block diagram of a digital demodulator according to a second embodiment of the present invention. still,
The same components and signals as those in the first embodiment described above are denoted by the same reference numerals (numbers), and description thereof is omitted. In the present embodiment, the CPU 101 ″
Are the error monitoring means 101 ''-1 and the clocking means 10
1 ''-2 and adaptation means 101 ''-3.

The error monitoring means 101 ″ -1 outputs the frequency error 167 detected by the frequency error detection circuit 165.
To monitor. The timer 101 ″ -2 has a timer function. The timer 101 ″ -2 measures a time change. The adaptive means 101 ″ -3 controls the control signal 11 based on the frequency detuning state and the time change given by the frequency error.
3 to learn the operation timing to be generated.

The CPU 101 ″ optimally controls the control signal 113 for giving the channel switching timing based on the detuning of the detected frequency error 167 when the power is turned on and the channel detuning at the time of channel switching.

[0074]

The digital demodulator according to the present invention compensates for frequency detuning during channel selection and shortens the time required for frequency pull-in processing.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram for explaining a digital demodulation device according to the present invention.

FIG. 2 is a block diagram for explaining a digital demodulator according to the first embodiment of the present invention.

FIG. 3 is a flowchart for explaining a part of the operation of the digital demodulator according to the first embodiment of the present invention.

FIG. 4 is a flowchart for explaining a part of the operation of the digital demodulator according to the first embodiment of the present invention.

FIG. 5 is a block diagram for explaining a digital demodulation device according to a second embodiment of the present invention.

FIG. 6 is a block diagram for explaining a conventional digital demodulation device.

[Explanation of symbols]

101: arithmetic units 101 ′, 101 ″, 203: CPU 101 ″ -1: error monitoring unit 101 ″ -2: clocking unit 101 ″ -3: adaptation unit 103: demodulation unit 105: error detection unit 107: Carrier reproduction unit 109: channel selection data 111, 205: channel switching signal 113: control signal 115, 201: input modulation signal 117: spectrum-shaped in-phase signal 119: spectrum-shaped quadrature signal 121: stored Frequency errors 123, 245: In-phase signals multiplied by complex 125, 247: Quadrature signals 126, 207 multiplied by complex: PLL circuits 127, 209: Mixer circuits 129: Modulated signals 131, 211: band-passed Type filter (B
PF) 133: Band pass signal 135, 213: Fixed frequency oscillator 136, 217: Mixer circuit 137, 215: 90 ° phase shifter (π / 2) 139: 90 ° phase shift signal 140, 219: Mixer circuit 141: Same Phase signal (I signal) 143: Negative phase signal (Q signal) 145, 147, 221, 223: Analog / Digital converter (A / D) 149: Converted in-phase signal 151: Converted quadrature signal 153 155, 225, 227: Digital low-pass filter (LPF) 157, 229: Complex multiplier 159, 231: Phase detector 160: Detected phase difference data 161, 233: Loop filter 163: Smoothed position Phase difference data 165, 235: frequency error detection circuit 167: detected frequency error 169: delay circuit 171: stored frequency error 172: switching circuit 173, 237: correction circuit 174: corrected phase difference data 175, 239: numerically controlled oscillator (NC)
O) 176: phase difference addition signal 177, 241: data conversion circuit having COS characteristics 179, 243: data conversion circuit having SIN characteristics 181, 244: reproduction signal

Claims (7)

[Claims] An arithmetic unit for outputting a channel switching signal indicating a change in oscillation frequency and a control signal indicating a change in a channel in response to channel selection data, based on the channel switching signal, A demodulation unit for performing quadrature demodulation processing on the input modulation signal to generate a digital in-phase and digital quadrature signal, detecting and storing a frequency error in the digital in-phase and quadrature signal, and responding to the control signal. An error detection unit for outputting the stored frequency error, and performing a complex multiplication process on the digital in-phase and quadrature signals based on the reproduced signal to generate a digital demodulated signal, based on the stored frequency error. Carrier recovery for correcting data obtained by performing a phase difference detection and smoothing process on the digital demodulated signal to generate a new reproduced signal. Digital demodulation apparatus characterized by comprising a. 2. The digital phase-locked loop system according to claim 2, wherein said correction processing is performed by said carrier recovery unit to form said data obtained by performing said phase difference detection and smoothing processing based on said stored frequency error. 2. The digital demodulation device according to claim 1, wherein the correction is performed within the frequency pull-in range. 3. The error detecting section comprises: detecting means for detecting the frequency error; and delay means for storing the detected frequency error so as to be output when the control signal is generated. Switching means for switching from output processing of the frequency error detected after generation of the control signal to output processing of the stored frequency error in response to the control signal. Item 3. The digital demodulation device according to Item 1. 4. The apparatus according to claim 3, wherein said frequency error is detected based on a frequency of said input modulated signal and a local oscillation frequency in quadrature quasi-synchronous detection of said quadrature demodulation processing. Digital demodulator. 5. The carrier recovery section executes the complex multiplication processing based on the reproduction signal, detects complex multiplication means for outputting the digital demodulated signal, and detects a phase difference in the digital demodulated signal. Phase difference detection / smoothing means for performing a smoothing process on the detected phase difference data, and correction means for correcting the smoothed phase difference data based on the stored frequency error; 2. The digital demodulation device according to claim 1, further comprising a reproducing unit for generating the new reproduction signal in response to the corrected phase difference data. 6. The digital demodulation device according to claim 5, wherein the detected phase difference gives a phase difference between the input modulation signal and a signal related to the reproduction signal. 7. The apparatus according to claim 1, wherein the input modulation signal is a phase shift keying signal having a plurality of phases.
7. The digital demodulation device according to claim 4 or 6.