JP2001053292A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a crystalline silicon film by forming an island-like film containing nickel, iron, cobalt, platinum and palladium, and annealing it at a temperature lower than a crystallization temperature of amorphous silicon. SOLUTION: A base silicon oxide film 1B is formed on a substrate 1A by a plasma CVD method and a film containing nickel, iron, cobalt, platinum and palladium is deposited on the base silicon oxide film 1 by sputtering. A region 2 as an island-like film is formed by patterning the film. Dehydrogenation is carried out by annealing it for 1 to 2 hours at 350 to 450 deg.C and an amorphous crystalline silicon film 1 is formed making hydrogen concentration in a film at most 5 atomic%. Therefore, cost reduction for heat treatment conditions can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film insulated gate field effect transistor (thin film transistor or TF).
The present invention relates to a method for obtaining a crystalline semiconductor used for a thin film device such as T).

[0002]

2. Description of the Related Art Conventionally, a crystalline silicon semiconductor thin film used for a thin film device such as a thin film insulated gate field effect transistor (TFT) is manufactured by a plasma CVD method or a thermal CV method.
The amorphous silicon film formed by the method D was crystallized in a device such as an electric furnace at a temperature of 600 ° C. or more for a long time of 12 hours or more. In particular, a longer heat treatment has been required to obtain sufficient characteristics (high field effect mobility and high reliability).

[0003]

However, such a conventional method has many problems. One is lower throughput and therefore higher cost. For example, assuming that the crystallization step requires 24 hours, if the processing time per substrate is 2 minutes, 720 substrates must be processed simultaneously. However, for example, in a commonly used tubular furnace, at most 50 substrates can be processed at a time, and when only one apparatus (reaction tube) is used, it takes 30 minutes per substrate. I have. That is, 1
In order to set the processing time per sheet to 2 minutes, as many as 15 reaction tubes had to be used. This meant that the size of the investment would increase, and that the investment would be significantly depreciated, which would return to the cost of the product.

[0004] Another problem was the temperature of the heat treatment. In general, substrates used for manufacturing TFTs are roughly classified into those made of pure silicon oxide such as quartz glass and non-alkali borosilicate glass such as Corning No. 7059 (hereinafter referred to as Corning 7059). Among them, the former has excellent heat resistance and can be handled in the same manner as a wafer process of a normal semiconductor integrated circuit, so that there is no problem regarding the temperature. However, its cost is high, and it increases exponentially rapidly as the substrate area increases. Therefore, at present, a relatively small area T
Used only for FT integrated circuits.

On the other hand, alkali-free glass has a sufficiently low cost as compared with quartz, but has a problem in terms of heat resistance, and generally has a strain point of about 550 to 650 ° C. Therefore, the heat treatment at 600 ° C. caused a problem of irreversible shrinkage and warpage of the substrate. In particular, it was remarkable for a large substrate having a diagonal exceeding 10 inches. For the above reasons, regarding crystallization of a silicon semiconductor film, a heat treatment condition of 550 ° C. or lower and within 4 hours has been indispensable for cost reduction. An object of the present invention is to provide a method for manufacturing a semiconductor which satisfies such a condition and a method for manufacturing a semiconductor device using such a semiconductor.

[0006]

SUMMARY OF THE INVENTION The present invention relates to an amorphous state or a disordered crystalline state that can be said to be substantially amorphous (for example, a state in which a portion having good crystallinity and an amorphous portion are mixed). Nickel, iron, cobalt, platinum, above or below the silicon film
Form island-like films, dots, particles, clusters, lines, etc. containing palladium and anneal them at a temperature below the crystallization temperature of normal amorphous silicon or below the glass transition temperature of the substrate Thus, a crystalline silicon film is obtained.

With respect to the conventional crystallization of a silicon film, a method of solid-phase epitaxial growth using a crystalline island-like film as a nucleus and using this as a seed crystal (for example, Japanese Patent Laid-Open No. 1-21)
4110). However, in such a method, crystal growth hardly proceeded at a temperature of 600 ° C. or less. In a silicon system, generally, in order to transition from an amorphous state to a crystalline state, a molecular chain in an amorphous state is divided, and furthermore, the divided molecule is brought into a state where it does not bind to another molecule again. It goes through the process of recombining a molecule into a part of the crystal in accordance with some crystalline molecule. However, during this process, the energy required to break the initial molecular chain and keep it unbound to other molecules is large,
This is a barrier in the crystallization reaction. In order to provide this energy, at a temperature of about 1000 ° C. for several minutes,
Alternatively, at a temperature of about 600 ° C., several tens of hours are required, and since the time depends exponentially on the temperature (= energy), at 600 ° C. or less, for example, at 550 ° C., the crystallization reaction hardly progresses. It could not be observed. The conventional idea of solid phase epitaxial crystallization did not provide a solution to this problem.

The present inventor has considered, apart from the conventional idea of solid-phase crystallization, to reduce the barrier energy of the above-mentioned process by some catalytic action. The present inventors have nickel (Ni), iron (Fe), cobalt (Co), platinum (Pt), palladium (Pd) is apt to bond to silicon, for example, in the case of nickel, easily nickel silicide (Formula NiSi _x, 0.4 ≦ x ≦ 2.5), and
We noticed that the lattice constant of nickel silicide is close to that of silicon crystal. Therefore, crystalline silicon-nickel silicide-
As a result of simulating the energy of a ternary system called amorphous silicon, amorphous silicon easily reacts at the interface with nickel silicide, and amorphous silicon (silicon A) + nickel silicide (silicon B) → nickel silicide (silicon A) + It has been found that a reaction of crystalline silicon (silicon B) (silicon A and B indicate the position of silicon) occurs. The potential barrier for this reaction is sufficiently low and the temperature of the reaction is low. This reaction equation shows that nickel proceeds while transforming amorphous silicon into crystalline silicon. Actually, the reaction starts below 580 ° C.
It became clear that the reaction was observed even at 0 ° C. Naturally, the higher the temperature, the faster the reaction proceeds. Similar effects were also observed with platinum, iron and cobalt.

In the present invention, island-like, stripe-like, linear,
Dot-like nickel, iron, cobalt, platinum, palladium alone or silicides thereof, nickel such as acetate, nitrate, etc.
Starting from a film, particle, cluster, etc. containing at least one of iron, cobalt, platinum, and palladium, from there, nickel, iron, cobalt, platinum, and palladium are developed to the surroundings with the above reaction. As a result, the region of crystalline silicon is expanded. Note that an oxide is not preferable as a material containing nickel, iron, cobalt, and platinum. This is because oxides are stable compounds and cannot initiate the above reaction.

[0010] The crystalline silicon expanded from a specific location in this way is different from the conventional solid phase epitaxial growth, but has a good crystal continuity and a structure close to a single crystal. It is convenient for use in an element. When a material containing nickel, iron, cobalt, platinum, and palladium is uniformly provided on a substrate, there are numerous starting points for crystallization, and therefore, it has been difficult to obtain a film having good crystallinity. The amorphous silicon film as a starting material for this crystallization showed better results as the hydrogen concentration was lower. However, since hydrogen is released as the crystallization progresses, the hydrogen concentration in the obtained silicon film did not show a clear correlation with the hydrogen concentration in the amorphous silicon film as the starting material.
The hydrogen concentration in the crystalline silicon according to the present invention was typically 1 × 10 ¹⁵ atoms / cm ³ or more and 5 atom% or less.

Although nickel, iron, cobalt, platinum and palladium are used in the present invention, these materials are not preferable for silicon as a semiconductor material. Therefore, if excessively contained in the silicon film, it is necessary to remove it. Regarding nickel, nickel silicide that has reached the end of crystallization as a result of the above reaction is hydrofluoric acid or Since it is easily dissolved in hydrochloric acid, nickel can be reduced from the substrate by treatment with these acids. In addition, nickel, iron, cobalt, platinum,
To reduce palladium, after completion of the crystallization step, hydrogen chloride, various methane chlorides (CH ₃ Cl, CH ₂ Cl ₂ , C
HCl ₃ ), various ethane chlorides (C ₂ H ₅ Cl, C ₂ H ₄ Cl _{2)
, C 2 H 3 Cl 3,} C 2 H 2 Cl 4, C 2 HCl 5) , or various ethylene chloride _{(C 2 H 3 Cl, C} 2 H 2 Cl 2, C 2 H
400-650 ° C. in an atmosphere containing chlorine such as Cl ₃ )
Should be processed. In particular, trichlorethylene (C ₂ H
Cl ₃ ) is an easy-to-use material. The concentration of nickel, iron, cobalt and platinum in the silicon film according to the present invention is 1
× 10 ¹⁵ cm ^-3 to 1 atomic%, more preferably 1 × 10 ¹⁶
It has been found that cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ is preferable. Below this range, crystallization does not proceed sufficiently. On the other hand, when it exceeds this range, the characteristics and reliability deteriorate.

Various physical and chemical methods can be used to form film-like nickel, iron, cobalt, platinum and palladium. For example, the method can be performed in the air such as a method requiring a vacuum apparatus such as a vacuum deposition method, a sputtering method, and a CVD method, a spin coating method, a dipping method (coating method), a doctor blade method, a screen printing method, and a spray pyrolysis method. Is the way. In particular, the spin coating method and the dipping method do not require extra equipment, but have excellent uniformity of film thickness.
In addition, it is a means capable of finely adjusting the density. Solutions used for these means include nickel, iron, cobalt, platinum, palladium acetate and nitrate, or various carboxylate and other organic acid salts with water, various alcohols (lower or higher), petroleum ( What is dissolved or diffused in a saturated hydrocarbon or an unsaturated hydrocarbon) may be used.

However, in this case, there is a concern that oxygen and carbon contained in these salts diffuse into the silicon film and deteriorate semiconductor characteristics. However, as a result of research by thermobalance method and differential thermal analysis method,
It was confirmed that at a temperature of 450 ° C. or less, an appropriate material was decomposed into an oxide or a simple substance, and then hardly diffused into the silicon film. In particular, when a lower-order substance such as an acetate or a nitrate was heated under a reducing atmosphere such as a nitrogen atmosphere, the substance was decomposed at a temperature of 400 ° C. or lower to become a simple metal. Similarly, it was observed that when heated in an oxygen atmosphere, an oxide was formed first, and at higher temperatures oxygen was released to form a simple metal.

In utilizing the crystalline silicon film produced according to the present invention for a semiconductor device such as a TFT, as is apparent from the above description, the termination of crystallization (here, the crystallization started from a plurality of starting points) Is where it hits)
There are large grain boundaries (crystal discontinuities),
Since the concentrations of nickel, iron, cobalt, platinum, palladium and the like are high, it is not preferable to provide a semiconductor element. In particular, a TFT channel region should not be provided. In addition, the place where crystallization starts, that is, nickel,
In a region where a substance having iron, cobalt, platinum, palladium, or the like is provided, sufficient attention is required in forming a semiconductor element because the concentration of these elements is high, and these elements are not included. Compared to silicon film, it is generally easier to etch with hydrofluoric acid based solution,
When a contact hole or the like is formed, it causes a contact failure. Therefore, in forming a semiconductor device using the present invention, it is necessary to optimize the pattern of the nickel-, iron-, cobalt-, platinum-, and palladium-containing coating film and the semiconductor device pattern, which are the starting points of crystallization. . Hereinafter, the present invention will be described in more detail with reference to Examples.

[0015]

[Embodiment 1] This embodiment uses a Corning 70
Forming a plurality of island-shaped nickel films on a 59 glass substrate,
Starting from these points, a method of crystallizing an amorphous silicon film and manufacturing a TFT using the obtained crystalline silicon film will be described. There are two methods for forming an island-like nickel film in terms of whether to provide it above or below an amorphous silicon film.
FIG. 2 (A-1) shows a method of providing the device below, and FIG.
2) is a method provided above. In particular, the latter must be noted because nickel is formed on the entire surface of the amorphous silicon film and then this is selectively etched, so that nickel and amorphous silicon react in a small amount to form silicide. Nickel is formed. If this is left as it is, a silicon film having good crystallinity as intended by the present invention cannot be obtained. Therefore, it is required to sufficiently remove the nickel silicide with hydrochloric acid, hydrofluoric acid, or the like. . Therefore, the amorphous silicon becomes thinner than the initial state.

On the other hand, in the former case, such a problem does not occur, but also in this case, it is desired that the nickel film other than the island portion is completely removed by etching. Further, in order to suppress the influence of the remaining nickel, the substrate may be treated with oxygen plasma, ozone, or the like to oxidize nickel in regions other than the island region.

In each case, the substrate (Corning 705)
9) On top of 1A, underlying silicon oxide film 1B having a thickness of 2000
Was formed by a plasma CVD method. The amorphous silicon film 1 has a thickness of 200 to 3000 °, preferably 500 to 1500 °, and is manufactured by a plasma CVD method or a low pressure CVD method. The amorphous silicon film is dehydrogenated by annealing at 350 to 450 ° C. for 0.1 to 2 hours to reduce the hydrogen concentration in the film to 5%.
Crystallization was easy when the content was less than atomic%. FIG. 2 (A
In the case of -1), a nickel film having a thickness of 50 to 100 is formed by a sputtering method before the formation of the amorphous silicon film 1.
0 °, preferably 100 to 500 °, was deposited and then patterned to form island-shaped nickel regions 2.

On the other hand, in the case of FIG. 2A-2, after the formation of the amorphous silicon film 1, a nickel film having a thickness of 50 to 1000 Å, preferably 100 to 1000 に よ っ て is formed by sputtering.
An island-shaped nickel region 2 was formed by depositing 500 ° and patterning it. Figure 1 shows this situation viewed from above.
It is shown in (A).

The island nickel was a square having a side of 2 μm, and the interval was 5 to 50 μm, for example, 20 μm. Similar effects can be obtained by using nickel silicide instead of nickel. When depositing nickel, the substrate should be 100 to 5 mm.
Good results were obtained by heating to 00 ° C, preferably 180-250 ° C. This is because the adhesion between the underlying silicon oxide film and the nickel film is improved, and the silicon oxide reacts with the nickel to produce nickel silicide. Similar effects can be obtained by using silicon nitride, silicon carbide, or silicon instead of silicon oxide.

Next, this is heated at 450-650 ° C.,
Annealing was performed at 50 ° C. for 8 hours in a nitrogen atmosphere. FIG.
FIG. 2B shows the intermediate state. In FIG. 2A, nickel proceeds from the island-like nickel film at the end to the central portion as nickel silicide 3A, and the portion 3 through which nickel has passed is crystal. It is silicon. Eventually, FIG.
As shown in (C), the crystallization starting from the two island-shaped nickel films hits, leaving nickel silicide 3A in the middle, and the crystallization ends.

FIG. 1B shows a state of the substrate in this state viewed from above. The nickel silicide 3 shown in FIG.
A is the grain boundary 4. If the annealing is further continued, nickel moves along the grain boundaries 4 and gathers in the intermediate region 5 of these island-like nickel regions (although the original shape is not retained at this stage).

Although crystalline silicon can be obtained by the above steps, it is not preferable that nickel diffuses into the semiconductor film from the nickel silicide 3A generated at this time. Therefore, it is desired to perform etching with hydrofluoric acid or hydrochloric acid. Note that neither hydrofluoric acid nor hydrochloric acid affects the silicon film. FIG. 2D shows the state after the etching. The portion having the grain boundary becomes the groove 4A. T so as to sandwich this groove
It is not preferable to form an FT semiconductor region (such as an active layer). As for the arrangement of TFTs, an example is shown in FIG.
As shown in FIG. 3, the semiconductor region 6 was arranged so as not to cross the grain boundary 4. On the other hand, the gate wiring 7 may cross the grain boundary 4.

FIGS. 3 and 4 show an example of manufacturing a TFT using the crystalline silicon obtained in the above steps. FIG.
In (A), the X at the center means the location where the groove 4A in FIG. 2 was located. As shown in the drawing, the semiconductor region of the TFT is arranged so as not to cross the X portion. That is, the crystalline silicon film 3 obtained in the step shown in FIG. 2 was patterned to form the island-shaped semiconductor regions 11a and 11b. Then, a silicon oxide film 12 functioning as a gate insulating film was formed by a method such as an RF plasma CVD method, an ECR plasma CVD method, or a sputtering method.

Further, phosphorus is reduced to 1 × by a low pressure CVD method.
10 ²⁰ -5 × 10 ²⁰ cm ^-3 doped thickness 3000-
A 6000 ° polycrystalline silicon film was formed, and this was patterned to form gate electrodes 13a and 13b.
(FIG. 3 (A))

Next, impurity doping was performed by a plasma doping method. As the doping gas, for example, phosphine (PH ₃ ) was used for the N-type, and diborane (B ₂ H ₆ ) was used for the P-type. The figure shows an N-type TFT. The accelerating voltage is 80 keV for phosphine and 65 for diborane.
keV. Further, the impurity is activated by annealing at 550 ° C. for 4 hours, and the impurity region 1
4a to 14d were formed. For the activation, a method using light energy such as laser annealing or flash lamp annealing can also be used. (FIG. 3
(B))

Finally, a 5000-nm-thick silicon oxide film is deposited as an interlayer insulator 15 in the same manner as in normal TFT fabrication, and contact holes are formed in the silicon oxide film to form wiring / electrodes 16a to 16d in source and drain regions. Was formed.
(FIG. 3 (C)) Through the above steps, a TFT (N-channel type in the figure) was manufactured. The field effect mobility of the obtained TFT is 40 to 60 cm ² / Vs for the N channel type, and 30 to 60 cm ² / Vs for the P channel type.
It was 50 cm ² / Vs.

FIG. 4 shows a case in which an aluminum gate TFT is manufactured. In FIG. 4A, the X in the center means the location where the groove 4A in FIG. 2 was located. As shown in the drawing, the semiconductor region of the TFT is arranged so as not to cross the X portion. That is, the crystalline silicon film 3 obtained in the step shown in FIG. 2 was patterned to form the island-shaped semiconductor regions 21a and 21b. And RF
A silicon oxide film 22 functioning as a gate insulating film was formed by a method such as a plasma CVD method, an ECR plasma CVD method, and a sputtering method. When the plasma CVD method is adopted, the source gas is TEOS (tetra ethoxy
Preferred results were obtained using silane) and oxygen. Then, an aluminum film containing 1% silicon (thickness 50
00Å) was deposited by a sputtering method, and this was patterned to form gate wiring / electrodes 23a and 23b.

Next, the substrate was immersed in a 3% solution of tartaric acid in ethylene glycol, and anodization was performed by passing a current through platinum as a cathode and aluminum wiring as an anode. The current was initially applied so as to increase the voltage at 2 V / min. When the voltage reached 220 V, the voltage was kept constant. When the current became 10 μA / m ² or less, the current was stopped. As a result, the anodic oxides 24a, 2
4b was formed. (FIG. 4 (A))

Next, impurity doping was performed by a plasma doping method. As the doping gas, phosphine (PH ₃ ) is used for the N type, and diborane (B ₂ ) is used for the P type.
H ₆ ) was used. The figure shows an N-channel TFT. The accelerating voltage is 80 keV for phosphine and 65 for diborane.
keV. Further, this is laser-annealed to activate the impurity, and the impurity region 25 is activated.
a to 25d were formed. The laser used was a KrF laser (wavelength 248 nm), 250 to 300 mJ / c.
Five shots of a laser beam having an energy density of m ² were irradiated. (FIG. 4 (B))

Finally, a 5000-nm-thick silicon oxide film is deposited as an interlayer insulator 26 in the same manner as a normal TFT fabrication, and contact holes are formed in the silicon oxide film to form wiring / electrodes 27a to 27d in the source region and the drain region. Was formed.
(FIG. 4C) The field effect mobility of the obtained TFT is 60 for the N-channel type.
~120cm ² / Vs, 50~90cm ² in P-channel type
/ Vs. A shift register manufactured using this TFT has a drain voltage of 17 V, 6 MHz,
Operation at 11 MHz at 0 V was confirmed.

Embodiment 2 FIG. 5 shows a case in which an aluminum gate TFT is manufactured in the same manner as in FIG. However, here, amorphous silicon was used as the active layer. As shown in FIG. 5A, a base silicon oxide film 32 is deposited on a substrate 31 and further has a thickness of 2000 to 30.
An amorphous silicon film 33 of 00 ° was deposited. An appropriate amount of P-type or N-type impurities may be mixed in the amorphous silicon film. Then, as shown above, the island-shaped nickel or nickel silicide coating 34 is formed.
A, 34B were formed, and in this state, the amorphous silicon film was crystallized by annealing at 550 ° C. for 4 hours.

Next, the crystalline silicon film thus obtained was patterned as shown in FIG. At this time, since the silicon film in the center of the figure (the middle part between the nickel or nickel silicide coatings 34A and 34B) contains a large amount of nickel, patterning is performed so as to remove this, and the island-like silicon regions 35A, 35B was formed.
Further, a substantially intrinsic amorphous silicon film 3 is formed thereon.
6 was deposited. Thereafter, as shown in FIG. 5C, a film is formed of a material such as silicon nitride or silicon oxide as a gate insulating film 37, a gate electrode 38 is formed of aluminum, and anodic oxidation is performed as in the case of FIG. The impurity is diffused by an ion doping method to form an impurity region 39.
A and 39B are formed. Further, an interlayer insulator 40 is deposited, a contact hole is formed, and the metal electrodes 41A and 41A are formed.
B is formed on the source and the drain to complete the TFT. This TFT is characterized in that the semiconductor film in the source and drain portions is thicker and the resistivity is smaller than the thickness of the active layer. As a result, the resistance of the source and drain regions is reduced, and the characteristics of the TFT are reduced. Is improved. Also, the formation of the contact is easy.

Third Embodiment FIG. 6 shows a CMOS type T
The case where FT fabrication was performed is shown. As shown in FIG. 6A, a base silicon oxide film 52 was deposited on a substrate 51, and an amorphous silicon film 53 having a thickness of 1000 to 1500 ° was further deposited. Then, an island-shaped nickel or nickel silicide film 54 is formed as described above, and annealed at 550 ° C. in this state. In this step, the silicon silicide region 55 grows, and crystallization proceeds. By annealing for 4 hours, the amorphous silicon film changes to crystalline silicon as shown in FIG. Further, the silicon silicide 59A and 59B are driven to the end by the progress of crystallization.

Next, the crystalline silicon film thus obtained was patterned as shown in FIG. 6B to form island-like silicon regions 56. At this time, it should be noted that the nickel concentration is high at both ends of the island region. After forming the island-shaped silicon region, a gate insulating film 57 and gate electrodes 58A and 58B were formed.

Thereafter, as shown in FIG. 5C, an impurity is diffused by an ion doping method to form an N-type impurity region 60A and a P-type impurity region 60B. At this time, for example, phosphorus is used as an N-type impurity (doping gas is phosphine PH ₃ ), the entire surface is doped with an acceleration voltage of 60 to 110 kV, and then the region of the N-channel TFT is covered with a photoresist. And P-type impurities such as boron (doping gas is diborane B ₂ H ₆ )
And doping at an accelerating voltage of 40 to 80 kV.

After the completion of the doping, the source and the drain are activated by irradiating a laser beam in the same manner as in FIG. 4, and further, an interlayer insulator 61 is deposited, contact holes are formed, and metal electrodes 62A and 62B , 62C are formed on the source and the drain to complete the TFT.

[Embodiment 4] In this embodiment, after the crystallization step by heating at 550 ° C. for 4 hours in the process of Embodiment 3, laser light is further irradiated to further improve the crystallinity of the crystalline silicon film. Configuration. FIG. 7 shows a manufacturing process of the CMOS type TFT of this embodiment. First, FIG.
As shown in FIG. 3A, a base silicon oxide film 52 is formed on a substrate 51.
Was deposited to a thickness of 2000 ° by sputtering. Further, an amorphous silicon film 53 having a thickness of 1000 to 1500 ° was deposited by a plasma CVD method. Then, an island-shaped nickel or nickel silicide coating 54 was formed.

Then, at 550.degree.
Time annealing was performed. In this step, the silicon silicide region 55 grows, and crystallization proceeds. Next, the crystalline silicon film thus obtained was patterned as shown in FIG. 7B to form an island-shaped silicon region 56.

Further, a KrF excimer laser beam (wavelength 2
Irradiation was performed at 48 nm and a pulse width of 20 nsec). Irradiation conditions were 250 mJ / cm ² and 2 shots. The irradiation power may be set to 200 to 400 mJ / cm ² in consideration of conditions such as a film thickness and a substrate temperature. Further, as the laser light, a XeCl laser (wavelength 308 n)
m), ArF laser (wavelength 193 nm) and the like can also be used.

Further, it is also possible to irradiate strong light which can obtain the same effect as irradiation with laser light. RTA (rapid thermal annealing) by irradiation of infrared light
Since silicon can selectively absorb infrared light in silicon, effective annealing can be performed. Note that laser light irradiation may be performed before the patterning step. As described above, a silicon film having good crystallinity can be obtained. As a result of performing such processing,
The silicon film 53 crystallized by the thermal annealing becomes a silicon film having better crystallinity. On the other hand, in a region that was not crystallized (not shown), a polycrystalline film was obtained as a result of laser irradiation, and the film was deteriorated, but Raman spectroscopy revealed that the crystallinity was not good. Became. According to transmission electron microscopy, a laser is irradiated without being crystallized, and the crystallized film has an infinite number of small crystals. As for No. 53, a relatively large crystal having a uniform crystal direction was observed.

Thereafter, gate electrodes 58A and 58B containing silicon as a main component were formed. Then, as shown in FIG. 7C, an impurity was diffused by an ion doping method to form an N-type impurity region 60A and a P-type impurity region 60B. At this time, for example, phosphorous (doping gas is phosphine PH ₃ ) is used as the N-type impurity,
Doping is performed on the entire surface at an accelerating voltage of ~ 110 kV, and then a P-type impurity, for example, boron (doping gas is diborane B ₂ H ₆ ) is used to cover the region of the N-channel TFT with a photoresist, and the doping is performed at 40 to 80 kV Doping at an acceleration voltage of

After the doping, the source and the drain are activated by irradiating a laser beam, an interlayer insulator 61 is deposited, a contact hole is formed, and metal electrodes 62A, 62B and 62C are formed on the source and the drain. Thus, the TFT is completed. As shown in this example, by introducing a catalyst element that promotes crystallization, 550 ° C.
By using both the crystallization step at a low temperature and a short time of about 4 hours and the annealing step by laser light irradiation, a crystalline silicon film with good crystallinity can be obtained. By manufacturing a TFT using such a crystalline silicon film, a high-performance TFT can be obtained. That is, in the N-channel TFT obtained in Example 1, the field-effect mobility (mobility) is 40 to 60 c.
m ² / Vs (silicon gate type, see FIG. 3) or 60 to 120 cm ² / Vs (aluminum gate type, see FIG. 4), and the threshold voltage was 3 to 8 V. The mobility of the N-channel TFT is 150 ~
200 cm ² / Vs, threshold voltage is 0.5 to 1.5 V
It is noted that the mobility has been greatly improved and the variation in threshold voltage has been reduced.

Conventionally, such characteristics have been
Only possible by laser crystallization of recon film
However, with conventional laser crystallization, the resulting silicon film
The characteristics vary widely and the crystallization is 400 ° C or less.
350 mJ / cm at above temperature ^TwoOr higher laser energy
Energy irradiation was required, and there was a problem in mass productivity.
In this regard, in this embodiment, both the substrate temperature and the energy density
Since a smaller value is sufficient,
There was no problem. In addition, the variation can be
Can be obtained because it is comparable to the solid-phase growth crystallization method
The TFT also had uniform characteristics.

In the present invention, when the concentration of Ni was low, the crystallization of the silicon film was insufficient, and the characteristics of the TFT were not good. However, in the present embodiment, even if the crystallinity of the silicon film is insufficient, it can be compensated by the subsequent laser irradiation, so that the characteristics of the TFT did not decrease even if the concentration of Ni was low. For this reason,
The nickel concentration in the active layer region of the device can be further reduced, and an extremely preferable configuration can be obtained from the viewpoint of electrical stability and reliability of the device.

Embodiment 5 In this embodiment, a catalyst element for promoting crystallization of amorphous silicon is contained in a solution, and this solution is applied on the amorphous silicon film to introduce the catalyst element into the amorphous silicon film. Configuration. Further, in this embodiment, a method for obtaining a crystalline silicon film with a low concentration of a catalytic element by selectively introducing a catalytic element and performing crystal growth from a region into which the catalytic element has not been introduced from the introduced region. About.

FIG. 8 shows an outline of the manufacturing process of this embodiment.
In FIG. 8, the same reference numerals as those in FIG. 2 indicate the same parts as those in FIG. First, a glass substrate (Corning 7059,
(10 cm square), an underlying silicon oxide film 1B was formed to a thickness of 2000 ° by sputtering, and an amorphous silicon film 1 was formed to a thickness of 1000 ° by plasma CVD. Next, a silicon oxide film 80 serving as a mask is
Was formed to a thickness of Experiments conducted by the inventors have confirmed that there is no problem with the thickness of the silicon oxide film 80 even at 500 °, and it is considered that the film thickness may be further reduced if the film quality is dense.

Then, the silicon oxide film 80 was subjected to a necessary pattern by a usual photolithography patterning process. Then, a thin silicon oxide film 82 was formed on the surface of the amorphous silicon film 1 exposed by irradiation of ultraviolet rays in an oxygen atmosphere. The silicon oxide film 82 is formed by irradiating UV light for 5 minutes in an oxygen atmosphere. The silicon oxide film 82 has a thickness of 20 to
It is considered about 50 °. (FIG. 8A)

This silicon oxide film is for improving the wettability of a solution applied in a later step. In this state, 100 ppm of nickel is added to the acetate solution.
(Weight conversion) 5 ml of the added acetate solution was dropped (10 c
In the case of an m-square substrate). At this time, 5
Spin coating was performed at 0 rpm for 10 seconds to form a uniform water film 83 over the entire substrate surface. Further, after maintaining in this state for 5 minutes, using a spinner 84 at 2,000 rpm, 6
Spin drying was performed for 0 seconds. This holding may be performed while rotating the spinner at 0 to 150 rpm. (FIG. 8A)

Through the above steps, nickel is introduced into the region indicated by reference numeral 85. And 300-50
A heat treatment was performed at a temperature of 0 degrees to generate nickel silicide on the surface of a region indicated by 85. Next, the silicon oxide film 80 serving as a mask is removed, and a heat treatment is performed at 550 ° C. (in a nitrogen atmosphere) for 4 hours.
0 was crystallized. At this time, crystal growth is performed in a lateral direction (a direction parallel to the substrate) from the region 85 into which nickel has been introduced to the region into which nickel has not been introduced. Of course, crystallization is performed also in the region where nickel is directly introduced.

Here, a heat treatment is performed to form a nickel silicide film on the surface of a region indicated by 85, and then the silicon oxide film 80 is removed. In the case where crystallization is performed by heat treatment, a step of forming a nickel silicide film need not be performed. In this case, after the crystallization step, the silicon oxide film 80 is formed.
Should be removed.

FIG. 8B shows an intermediate state in which crystallization proceeds. This indicates a state in which the nickel introduced toward the end advances to the central portion as nickel silicide 3A, and the portion 3 through which nickel has passed is crystalline silicon. As the crystallization proceeds further, the crystallization starting from the region 85 into which two nickels have been introduced as shown in FIG. 8C, the nickel silicide 3A remains in the middle, and the crystallization ends.

Although crystalline silicon can be obtained by the above steps, it is not preferable that nickel diffuses into the semiconductor film from the nickel silicide 3A generated at this time. Therefore, the 3A region was etched with hydrofluoric acid or hydrochloric acid. FIG. 8D shows the state after the etching. The portion having the grain boundary becomes the groove 4A.

In FIG. 8C, a region 86 is a region 85
Is a region where crystallization is performed in the lateral direction. FIG. 9 shows the nickel concentration in the region indicated by 86. FIG. 9 shows the result of measurement of the nickel concentration distribution in the depth direction of the region indicated by 86 of the crystalline silicon film after the crystallization step by SIMS. Further, it has been confirmed that the concentration of nickel in the region 85 into which nickel has been directly introduced shows a value which is higher by one digit or more than the concentration distribution shown in FIG.
Using the crystalline silicon film thus obtained, a TFT was manufactured in the same manner as in Example 1.

Incidentally, it is effective to further improve the crystallinity by irradiating the crystalline silicon film thus obtained with a laser or a strong light equivalent thereto as in the fourth embodiment. In Example 4, since the nickel concentration in the silicon film was relatively high, the laser irradiation caused nickel in the silicon film to precipitate and
Nickel silicide grains of about μm were formed in the silicon film, and the morphology of the film deteriorated. However, in this embodiment, since the nickel concentration can be reduced much more than in Examples 1 and 2, there was no precipitation of nickel silicide, and the film was prevented from being roughened by laser irradiation.

The nickel concentration shown in FIG. 9 can be controlled by controlling the nickel concentration in the solution. In the present embodiment, the nickel concentration in the solution was set to 100 ppm, but it has been found that crystallization is possible even when the nickel concentration is set to 10 ppm. In this case, the nickel concentration in the region 86 of FIG. 8 shown in FIG. 9 can be further reduced by one digit. However, when the nickel concentration in the solution is reduced, there is a problem that the crystal growth distance in the lateral direction is shortened.

The crystalline silicon film crystallized as described above can be used as it is for the active layer of the TFT. In particular, it is extremely useful to form an active layer of a TFT using the region indicated by 86 because of the low concentration of the catalytic element. In this example, an acetate solution was used as the solution containing the catalytic element, but the solution was widely used.
An organic solvent solution or the like can be used. Here, the catalyst element may not be contained as a compound but may be contained simply by being dispersed.

As the solvent containing the catalyst element, a solvent selected from polar solvents such as water, alcohol, acid and ammonia can be used. When nickel is used as a catalyst and this nickel is contained in a polar solvent, nickel is introduced as a nickel compound. As the nickel compound, typically, nickel bromide, nickel acetate,
Nickel oxalate, nickel carbonate, nickel chloride, nickel iodide, nickel nitrate, nickel sulfate, nickel formate, nickel acetylacetonate, nickel 4-cyclohexylbutyrate, nickel oxide, and nickel hydroxide are used.

As the solvent, a non-polar solvent selected from benzene, toluene, xylene, carbon tetrachloride, chloroform and ether can be used.
In this case, nickel is introduced as a nickel compound. As the nickel compound, typically, a compound selected from nickel acetylacetonate and nickel 2-ethylhexanoate can be used.

It is also useful to add a surfactant to the solution containing the catalyst element. This is to increase the adhesion to the surface to be coated and control the adsorption. This surfactant may be applied in advance on the surface to be coated. When nickel alone is used as a catalyst element, it is necessary to dissolve it in an acid to form a solution.

The above is an example in which a solution in which nickel as a catalytic element is completely dissolved is used. However, even if nickel is not completely dissolved, a powder composed of nickel alone or a nickel compound is dispersed in a dispersion medium. A material such as an emulsion which is uniformly dispersed in the emulsion may be used. Alternatively, a solution for forming an oxide film may be used. As such a solution, OCD (Ohka Diffusion) of Tokyo Ohka Kogyo Co., Ltd.
Source) can be used. With the use of this OCD solution, a silicon oxide film can be easily formed by applying it on the surface to be formed and baking it at about 200 ° C. In addition, it is possible to add an impurity because it is free.

The same applies to the case where a material other than nickel is used as the catalyst element. In addition, by using a nonpolar solvent such as a toluene solution of nickel 2-ethylhexanoate as a solution, the solution can be directly applied to the surface of the amorphous silicon film. In this case, it is effective to apply a material such as an adhesive used in applying the resist in advance. However, care must be taken when the amount of coating is too large, since this would hinder the addition of the catalytic element to the amorphous silicon.

The amount of the catalyst element contained in the solution depends on the type of the solution, but the general tendency is that the amount of nickel is 200 ppm to 1 ppm, preferably 50 ppm to 1 ppm (weight conversion) based on the solution. It is desirable. This is a value determined in view of the nickel concentration in the film after crystallization and the resistance to hydrofluoric acid. In this embodiment, the example in which the solution containing the catalyst element is applied to the upper surface of the amorphous silicon film is shown, but the solution containing the catalyst element is applied to the base film before the formation of the amorphous silicon film. May be.

[Embodiment 6] This embodiment relates to a positional relationship between a catalytic element addition region and a crystallization region, a TFT active layer (channel region), and a contact hole when a TFT is manufactured by using the present invention. . Hereinafter, a description will be given of a pixel portion of a machive matrix as an example. FIG. 10 shows a manufacturing process of the TFT of this embodiment. First, as shown in FIG. 10A, a base silicon oxide film 92 was deposited on a substrate 91 to a thickness of 2000 ° by a sputtering method. Further thickness 30
An amorphous silicon film 93 of 0 to 1500 °, for example, 800 ° was deposited by a plasma CVD method. Then, a silicon oxide film 94 having a thickness of 200 to 2000 Å, for example, 300 Å was formed, and holes 96 a and 96 b were formed therein, and this was used as a mask. Then, an extremely thin nickel film or nickel compound film 95 was formed on the entire surface by sputtering or spin coating as in Example 5.

Then, at 550 ° C., 4
Time annealing was performed. By this step, the amorphous silicon film is formed in the portion 97 immediately below the holes 96a and 96b.
a and 97b became silicide, from which crystallization proceeded and silicon regions 98a and 98b grew. The tip portions were regions 99a and 99b having a high nickel concentration. (FIG. 10 (B)) In a state where crystallization has sufficiently proceeded, the crystallization that has proceeded from the holes 96a and 96b collides in the middle thereof, and the crystallization has stopped in this state. A region 99a having a high nickel concentration was left in the portion where the crystallization collided. In this state, optical annealing may be further performed by an excimer laser or the like as in the fourth embodiment. (FIG. 10C) Next, the crystalline silicon film thus obtained is
As shown in (D), the island-shaped silicon region 100 was formed by patterning. In the silicon region 100, a part of the region 97a having a high nickel concentration and 99c are left. Further, the thickness is 700 to 2 by a plasma CVD method.
A silicon oxide film 101 having a thickness of 2,000 °, for example, 1200 ° was formed and used as a gate insulating film. (FIG. 10 (D))

Thereafter, the gate electrode 102 was formed of aluminum using the same means as in the first embodiment. An anodic oxide film 103 having a thickness of 1000 to 5000 ° was formed around the gate electrode. Then, the impurities are diffused by the ion doping method to form the N-type impurity regions 104 and 10.
5 was formed. In this case, as shown in the figure, the position of the gate electrode must be determined so that the regions 97a and 99c having a high nickel concentration are not located in a portion (channel region) immediately below the gate electrode. (FIG. 10 (E)

After the completion of the doping, the source and the drain are activated by irradiating a laser beam, an interlayer insulator 106 is deposited, and a thickness of 500 nm is formed by sputtering.
A pixel electrode 107 was formed by forming a transparent conductor film of about 1500 °, for example, 800 °, and patterning and etching the transparent conductive film. Further, the interlayer insulator 106
Contact holes are formed in the metal electrodes 108 and 109
Was formed on the source and drain of the TFT to complete the TFT. When forming the contact hole, it is desirable to form the contact hole avoiding the regions 97a and 99c where the nickel concentration is high. For this purpose, the contact hole may be designed so as not to overlap with the holes 96a and 96b for adding nickel as much as possible. Such a design is made because, in a region where the concentration of nickel is high, the silicon film is more easily etched by a hydrogen fluoride-based solution than a silicon film having no nickel. Is over-etched and a contact failure is likely to occur. In the figure, the left contact partly overlaps with the region 97a having a high nickel concentration, but it is desirable that at least a part of the electrode is in contact with a region other than the nickel-added region.

[0067]

As described above, the present invention is epoch-making in that it promotes lowering the temperature and shortening the time of crystallization of amorphous silicon.
Since the equipment and the method are very common and excellent in mass productivity, the profits brought to the industry are insignificant.

For example, in the conventional solid-phase growth method, since annealing for at least 24 hours is required,
Assuming that the substrate processing time per substrate is 2 minutes, as many as 15 annealing furnaces were required.
Since the number of annealing furnaces can be reduced to less than 1/6, the number of annealing furnaces can be reduced to 1/6 or less. Improvement in productivity and reduction in capital investment due to this leads to a reduction in substrate processing cost, which in turn leads to a reduction in TFT price and thus a new demand. Thus, the present invention is industrially useful and deserves a patent.

[Brief description of the drawings]

FIG. 1 shows a top view of the steps of an embodiment. (Crystallization and TFT arrangement)

FIG. 2 shows a cross-sectional view of a process of the embodiment. (Step of selective crystallization)

FIG. 3 shows a cross-sectional view of a process of the embodiment. (Example 1
reference)

FIG. 4 shows a cross-sectional view of a process of the embodiment. (Example 1
reference)

FIG. 5 shows a cross-sectional view of the process of the embodiment. (Example 2
reference)

FIG. 6 shows a cross-sectional view of a process in the example. (Example 3
reference)

FIG. 7 shows a cross-sectional view of a step in the example. (Example 4
reference)

FIG. 8 shows a cross-sectional view of the process of the example. (Example 5
reference)

FIG. 9 shows the nickel concentration in the crystalline silicon film.
(See Example 5)

FIG. 10 shows a cross-sectional view of a step in the example. (Example 6
reference)

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Amorphous silicon 2 ... Nickel-shaped nickel film 3 ... Crystal silicon 4 ... Grain boundary 5 ... A region where crystallization has not progressed 6 ... Semiconductor region 7 ... Gate wiring

Continued on the front page (72) Inventor Toru Takayama 398 Hase, Atsugi-shi, Kanagawa Prefecture Inside Semi-Conductor Energy Laboratory Co., Ltd. (72) Inventor Shunpei Yamazaki 398-Hase, Atsugi City, Kanagawa Prefecture Inside Semi-Conductor Energy Laboratory Co., Ltd. (72) Inventor Yasuhiko Takemura 398 Hase, Atsugi-shi, Kanagawa Inside Semiconductor Energy Laboratory Co., Ltd.

Claims (10)

[Claims] After forming a material containing a metal element which promotes crystallization of silicon in contact with an insulating surface, a substantially amorphous silicon film is formed on the insulating surface, and the silicon film is heated. Thereby, the metal element is moved in the silicon film and crystallized, phosphorus is selectively added to the crystallized silicon film, and after the phosphorus is added, the crystallized silicon film is heat-treated. A method of manufacturing a semiconductor device, wherein the metal element is any one of nickel, iron, cobalt, platinum, and palladium. 2. A silicon film in a substantially amorphous state is formed on an insulating surface, a material containing a metal element which promotes crystallization of silicon is formed in contact with a surface of the silicon film, and the silicon film is heated. Then, the metal element is moved in the silicon film and crystallized, phosphorus is selectively added to the crystallized silicon film, and after the phosphorus is added, the crystallized silicon film is heat-treated. A method of manufacturing a semiconductor device, wherein the metal element is any one of nickel, iron, cobalt, platinum, and palladium. 3. A silicon film substantially in an amorphous state is formed on an insulating surface, a material containing a metal element which promotes silicon crystallization is formed in contact with a surface of the silicon film, and the silicon film is heated. Then, the metal element is moved in the silicon film and crystallized, and phosphorus is selectively added to the crystallized silicon film. After phosphorus is added, the crystallized silicon film is laser-annealed. A method of manufacturing a semiconductor device including annealing or flash lamp annealing, wherein the metal element is any one of nickel, iron, cobalt, platinum, and palladium. . 4. The method for manufacturing a semiconductor device according to claim 1, wherein phosphorus is added to the crystallized silicon film using an ion doping method. 5. A method for forming a substantially amorphous silicon film on an insulating surface, forming a material containing a metal element which promotes crystallization of silicon in contact with the surface of the silicon film, and heating the silicon film By moving the metal element in the silicon film and crystallizing the same, the crystallized silicon film is patterned to form a semiconductor region provided with a channel formation region, and a gate insulating film is formed on the semiconductor region. Forming a gate electrode on the gate insulating film, using the gate electrode as a mask, selectively adding phosphorus to the semiconductor region, and heat-treating the phosphorus-added semiconductor region. A method of manufacturing a device, wherein the metal element is any one of nickel, iron, cobalt, platinum, and palladium. Manufacturing method. 6. A silicon film in a substantially amorphous state is formed on an insulating surface, a material containing a metal element which promotes silicon crystallization is formed in contact with a surface of the silicon film, and the silicon film is heated. By moving the metal element in the silicon film and crystallizing the same, the crystallized silicon film is patterned to form a semiconductor region provided with a channel formation region, and a gate insulating film is formed on the semiconductor region. Forming a gate electrode on the gate insulating film; using the gate electrode as a mask, selectively adding phosphorus to the semiconductor region; and performing laser annealing on the phosphorus-added semiconductor region or using a flash lamp. A method for manufacturing a semiconductor device including annealing, wherein the metal element is any one of nickel, iron, cobalt, platinum, and palladium. The method of manufacturing a semiconductor device which is a Kano element. 7. The method for manufacturing a semiconductor device according to claim 5, wherein phosphorus is added to the semiconductor region using an ion doping method. 8. The heating temperature according to claim 1, wherein a heating temperature for crystallizing the silicon film is 450 to 450.
A method for manufacturing a semiconductor device, wherein the temperature is 580 ° C. 9. The semiconductor according to claim 1, wherein the material containing the metal element is formed by using any one of a vacuum deposition method, a sputtering method, and a CVD method. Device manufacturing method. 10. The method according to claim 1, wherein the metal element is contained by using any one of a spin coating method, a dipping method, a doctor blade method, a screen printing method, and a spray pyrolysis method. A method for manufacturing a semiconductor device, comprising forming a material.