JP2001051640A - Clock phase automatic adjusting device in pixel corresponding display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To maintain a best stabilized phase relation between pixel data of input image signals and a sampling clock, by calculating an arithmetic mean value of a 1st and a 2nd delays and deciding it as an optimal delay to be set into a stationary delay circuit when the 1st and 2nd delays are maintained by maintaining means and the 2nd delay id larger than the 1st delay. SOLUTION: When a 1st count value held in a 1st clock phase holding circuit 11 and a 2nd count value held in a 2nd clock phase holding circuit 12 satisfy the relation that the 2nd count value is larger than the 1st count value, an arithmetic mean circuit 13 calculates an arithmetic mean value of the 1st count value and the 2nd count value, and also outputs an automatic phase adjustment ending signal. When the automatic phase adjustment ending signal is outputted, a switch circuit 15 is returned to the side (a) of a contact and the value calculated by the arithmetic mean circuit 13 is sent to a horizontal synchronizing signal delay circuit 16 as an optimal delay setting.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic clock phase adjusting device in a pixel-compatible display device for displaying an image in pixel units, and more particularly to a clock signal and an image signal pixel for converting an input image signal from analog to digital. The present invention relates to an automatic clock phase adjusting device in a pixel correspondence display device which can always maintain a stable phase relationship with the clock signal.

[0002]

2. Description of the Related Art In a liquid crystal display device, which is one type of pixel-compatible display device, an image is displayed by synchronizing one dot of pixel data of an image signal with one pixel of a liquid crystal panel in one horizontal scanning period. Is done. In addition, the line data of one horizontal scanning line (hereinafter, referred to as a line) in an arbitrary number of line data included in one vertical scanning period of the image signal is displayed corresponding to one vertical line on the liquid crystal panel. . This line data is an aggregate of pixel data.

Image data handled internally by a computer is a digital signal, and the image signal is also generated as a digital signal in pixel units. However, since a CRT display conventionally used as a display is an analog device, the image data generated in the computer is converted into an analog image signal in the computer to generate a CRT display.
Output to the display.

On the other hand, since a liquid crystal display is a digital device, it is necessary to A / D convert an image signal sent as an analog signal from a computer. For this reason, it is necessary to reproduce a sampling clock for performing A / D conversion on the display side. Conventionally, a sampling clock for performing A / D conversion based on only the horizontal synchronization signal has been reproduced. However, there is no guarantee that the phase relationship between the horizontal synchronizing signal and the pixel of the analog image signal is always kept in a correct state, so that it is necessary to adjust the phase of the sampling clock.

In order to automatically adjust the phase of a sampling clock, the level value of specific pixel data in a digital image signal sampled by an A / D converter is measured while changing the clock phase, and the level becomes maximum. A system for adjusting the clock phase has already been developed.

With such an adjustment method, it is possible to detect a range in which the phase relationship between the pixel of the image signal and the sampling clock is almost stable, but it is difficult to specify the most stable phase point. This is because within the range in which the phase relationship between the pixel of the image signal and the sampling clock is almost stable, the sampled digital data keeps the same value that is almost stable. It is difficult to specify the amount of deviation. Furthermore, the level value of the reference image data is easily affected by the image content and the frequency characteristics of the analog waveform, that is, overshoot distortion and linking distortion, and is likely to cause erroneous detection.

Also, as a characteristic of a PLL circuit for generating a clock from a horizontal synchronization signal, the clock phase tends to gradually shift from the clock phase immediately after the horizontal synchronization signal as the distance from the horizontal synchronization signal increases. Therefore, the best point of the clock phase actually differs between the left and right ends of the image. Thus, the best clock phase at a particular point in the image may not be the best at other points in the image.

[0008]

SUMMARY OF THE INVENTION The present invention provides an automatic clock phase adjusting device in a pixel-compatible display device capable of accurately detecting a clock phase at which the phase relationship between a pixel of an input image signal and a sampling clock is most stable. The purpose is to:

[0009]

According to the present invention, there is provided an automatic clock phase adjusting device in a pixel-compatible display device, wherein a horizontal synchronizing signal of an input image signal is delayed and outputted from a variable delay circuit and a delay circuit. A clock generation circuit that generates a sampling clock synchronized with the horizontal synchronization signal, an A / D converter that samples an input image signal based on a sampling clock generated from the clock generation circuit, and an image data output from the A / D converter. Detecting means for detecting a horizontal video start position and a horizontal video end position of each horizontal line by comparing the horizontal video start position and the horizontal video end position among the horizontal video start positions detected in one field. A horizontal video start position closest to the horizontal period start position specified by the horizontal synchronization signal; Of the input image signal for each field based on the horizontal image end position farthest from the horizontal period start position specified by the horizontal synchronization signal output from the delay circuit among the horizontal image end positions detected in Calculating means for calculating the number of sampling clocks corresponding to the distance between the video start position and the horizontal video end position; and changing the phase of the sampling clock to 1 by changing the amount of delay set for the delay circuit by a predetermined amount for each field. The delay amount is changed by a predetermined amount for each field, and the set delay amount set in the delay circuit in the field when the number of sampling clocks calculated by the calculating means changes in a decreasing direction is held as a first delay amount. Change in the direction in which the number of sampling clocks calculated by the calculation means increases. Holding means for holding the set delay amount set in the delay circuit in the field at the time as the second delay amount, and calculating the average value of the first delay amount and the second delay amount, and obtaining the obtained average value An optimum delay amount determining means for determining a value as an optimum delay amount to be set in the delay circuit in a steady state is provided.

[0010] The optimum delay amount determining means is configured to determine when the first delay amount and the second delay amount held in the holding means satisfy a relationship that the second delay amount is larger than the first delay amount. Calculating an average value of the first delay amount and the second delay amount,
It is preferable to use one that determines the obtained average value as an optimal delay amount to be set in the delay circuit in a steady state.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration of an automatic clock phase adjusting circuit provided in a liquid crystal display device.

The image signals R, G, and B input from the computer to the liquid crystal display device respectively have level adjusters 1a,
The levels are adjusted by 1b and 1c so as to meet the input conditions of the A / D converters (A / D converters) 2a, 2b and 2c. The level-adjusted R, G, and B signals are A
The data is converted into digital R, G, B data by the / D converters 2a, 2b, 2c.

A sampling clock for the A / D converters 2a, 2b, 2c is generated by a PLL circuit 17. A horizontal synchronizing signal for the input image signal is sent to the PLL circuit 17 via a horizontal synchronizing signal delay circuit 16. The PLL circuit 17 includes a horizontal synchronizing signal delay circuit 1
A sampling clock is generated based on the horizontal synchronizing signal output from 6. The phase of the sampling clock is
The adjustment is made by changing the amount of delay set in the horizontal synchronization signal delay circuit 16.

The digital R, G, B data obtained by the A / D converters 2a, 2b, 2c are sent to a horizontal video start / end detection circuit 3. The horizontal video start / end detection circuit 3 is provided for detecting a horizontal video start position and a horizontal video end position for each horizontal line based on output data of the A / D converters 2a, 2b, 2c. is there.

That is, the horizontal video start / end detection circuit 3
When the input R, G, B data changes from a level lower than a predetermined threshold value (video slice level) to a level higher than the threshold value, a horizontal video signal consisting of a pulse signal for one sampling clock starts. Output a signal. However, after the horizontal image start signal is output by changing the input data from a level lower than the threshold to a level higher than the threshold, the input data maintains the level higher than the threshold. In this case, the horizontal video start signal is not output. After the horizontal image start signal is output, if the input data becomes lower than the threshold value and then exceeds the threshold value again, the horizontal image start signal is output again.

When the input R, G, B data changes from a level higher than a predetermined threshold value to a level lower than the threshold value, the horizontal video start / end detection circuit 3 outputs one sampling clock. And outputs a horizontal video end signal composed of a pulse signal of The horizontal video start signal and the horizontal video end signal output from the horizontal video start / end detection circuit 3 are sent to the maximum hold unit 5.

If a large value is set as the threshold value, low-luminance data cannot be read, and if a small value is set as the threshold value, noise may be read as data. Is set to a low value.

The H counter 4 counts the number of sampling clocks input to the H counter 4. However,
The H counter 4 is reset every time a horizontal synchronization signal is input from the horizontal synchronization signal delay circuit 16. Therefore,
The H counter 4 counts the number of sampling clock outputs from the output timing of the horizontal synchronization signal output from the horizontal synchronization signal delay circuit 16 for each horizontal period. H
The count value of the counter 4 is sent to the maximum hold unit 5.

The maximum hold unit 5 holds the smallest one of the count values of the H counter 4 when the horizontal image start signal is input (hereinafter referred to as the horizontal image start count value) in each field. Also, the maximum hold unit 5
Is the H counter 4 when the horizontal video end signal is input.
Count value (hereinafter referred to as horizontal video end count value)
Of these, the largest one in each field is held.
The maximum hold unit 5 sends the horizontal video start count value and the horizontal video end count value to the subtracter 6 for each field. However, the maximum hold unit 5 is reset every field.

The subtractor 6 calculates the difference between the horizontal video start count value and the horizontal video end count value sent from the maximum hold unit 5 for each field for each vertical period,
The calculation result is output to the absolute value circuit 7. Absolute value circuit 7
Outputs the absolute value of the operation result obtained by the subtractor 6.

At the time of automatic clock phase adjustment, the amount of delay of the horizontal synchronizing signal delay circuit 16 is changed by a predetermined amount for each field to change the difference between the horizontal video start count value and the horizontal video end count value. , The best point of the clock phase is detected.

The principle for detecting the best point of the clock phase will be described with reference to FIG. FIG. 2 (a)
When the clock phase is changed, the relationship between the pixel of the input image signal and the clock phase becomes a data stable state,
This shows a state where data becomes unstable.

The point a is the best point of the clock phase.
The point at which the image data sampled by the D converters 2a, 2b, 2c is the most stable. When the clock phase is gradually shifted from the point a, the data sampled by the A / D converters 2a, 2b, and 2c become unstable, and the data becomes most unstable at the point b.

FIG. 2A shows an example in which a SIN waveform is used as a change curve indicating a stable state of data and a point at a phase of 90 degrees is the best point for easy understanding. This change curve changes depending on the setting of the frequency, the amount of clock jitter, and the video slice level. However, in the change curve indicating the stable state of the data, since the vicinity of the point a, which is the best point, is always a gentle curve, it can be understood that the vertex of the curve, that is, the best point a, is difficult to find.

FIG. 2B shows how the absolute value of the difference between the horizontal video start count value and the horizontal video end count value when the clock phase is changed in the positive direction changes.
As can be seen from FIG. 2B, at point m, the absolute value has decreased from the previous value x + 1 to x. At the point n, the absolute value increases from the previous value x to x + 1. The singular points m and n at which the absolute value changes occur are located at the same distance from the best point a.

As shown in FIG. 2C, the absolute value near the clock phase unstable point b is x + 1 as compared with the absolute value x near the clock phase best point a. Therefore, the best point a of the clock phase can be found by finding the midpoint between the points m and n, which are singular points, within the range where the absolute value is x.

Returning to FIG. 1, the automatic phase adjustment timing generation circuit 14 detects, for example, when the input signal to the liquid crystal display device has been switched, or when an automatic adjustment command is input by the operator. Outputs the automatic adjustment start signal.

A default value is initially set in the clock phase setting counter 10. When an automatic adjustment start signal is input, the clock phase setting counter 10 counts up (the count value is incremented by 1) every vertical retrace period of the input image signal. Is done. The switch circuit 15 is normally switched to the contact a side, but is switched to the contact b side during automatic adjustment.

The count value of the clock phase setting counter 10 is input to the horizontal synchronization signal delay circuit 16 through the switch circuit 15. The horizontal synchronization signal delay circuit 16 delays the horizontal synchronization signal by a delay amount according to the count value of the clock phase setting counter 10. PLL circuit 17
Generates a sampling clock based on the horizontal synchronization signal delayed by the horizontal synchronization signal delay circuit 16.

The first change point detection circuit 8 includes an absolute value circuit 7
The first change point (the point m in FIG. 2A) at which the absolute value output from is smaller than the previous value is detected. The first clock phase hold circuit 11 holds the count value of the clock phase counter 10 set in the horizontal synchronization signal delay circuit 16 in the field where the first transition point is detected by the first transition point detection circuit 8.

The second change point detection circuit 9 includes an absolute value circuit 7
The second change point (the point n in FIG. 2A) at which the absolute value output from is increased from the previous value is detected. The second clock phase hold circuit 12 holds the count value of the clock phase counter 10 set in the horizontal synchronization signal delay circuit 16 in the field where the second change point is detected by the second change point detection circuit 9.

The averaging circuit 13 calculates the count value (first count value) held in the first clock phase hold circuit 11 and the count value (second count value) held in the second clock phase hold circuit 12. Value) and the second
When the relationship that the count value is larger than the first count value is satisfied, an average value of the first count value and the second count value is calculated, and an automatic phase adjustment end signal is output.

The count value (first count value) held by the first clock phase hold circuit 11 and the count value (second count value) held by the second clock phase hold circuit 12 are equal to each other. The reason for terminating the automatic phase adjustment when the relationship that the 2 count value is larger than the first count value is satisfied is as follows.
That is, from the first change point (point m shown in FIG. 2A),
The second change point (point n shown in FIG. 2A) is detected first,
Thereafter, when the first change point is detected, the automatic adjustment is maintained until the next change point is detected.

When the automatic phase adjustment end signal is output, the switch circuit 15 is returned to the contact a, and the averaging circuit 13
Is sent to the horizontal synchronizing signal delay circuit 16 as an optimal delay amount setting value (clock phase setting value). Then, the automatic phase adjustment ends.

The feature of the above automatic phase adjustment circuit is that, instead of using the level value of the input image signal as it is, a unique clock phase is determined based on the number of sampling clocks output from the horizontal video start position to the horizontal video end position. The point is to detect the point.

According to the automatic phase adjusting circuit, the image content and the frequency characteristics of the analog waveform, that is, the image signal which is susceptible to overshoot distortion and ringing distortion, are stable regardless of the data near the white level or the black level of the image signal. As a result, the best clock phase can be detected. In addition, since the data at both the start position and the end position of the horizontal image is used, it is possible to absorb subtle differences in the clock phase between the left and right parts of the image. Clock phase can be detected.

Since the start position and end position of the horizontal image are extracted from the entire screen by the maximum hold unit 5, it is sufficient that the image data exists in any one of the lines of the image. However, it is possible to detect even if there is no signal up to both ends of the effective period of the screen.

[0039]

According to the present invention, the clock phase at which the relationship between the pixel of the input image signal and the clock phase is most stable can be accurately detected. As a result, the most stable phase relationship between the pixel data of the input image signal and the sampling clock is maintained, and a stable image can be displayed on the pixel-compatible panel.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a clock phase automatic adjustment circuit provided in a liquid crystal display device.

FIG. 2 is an explanatory diagram for explaining a principle for detecting a best point of a clock phase.

[Explanation of symbols]

1a, 1b, 1c Level adjuster 2a, 2b, 2c A / D converter (A / D converter) 3 Horizontal image start / end detection circuit 4 H counter 5 Maximum hold unit 6 Subtractor 7 Absolute value circuit 8 First change Point detection circuit 9 Second transition point detection circuit 10 Clock phase setting counter 11 First clock phase hold circuit 12 Second clock phase hold circuit 13 Averaging circuit 14 Automatic phase adjustment timing generation circuit 15 Switch circuit 16 Horizontal synchronization signal Delay circuit 17 PLL circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C006 AA22 AC21 AF72 AF81 BB11 BC12 BC16 BF11 FA04 FA16 5C020 AA01 AA22 AA35 CA13 CA15 5C021 PA18 PA26 PA42 PA54 PA76 PA85 SA02 SA08 SA21 XC01 YC01 5C080 AA10 BB05 CC03 DD09 EE EE EE GG10 JJ02 JJ04 JJ05

Claims (2)

[Claims] A variable delay circuit for delaying and outputting a horizontal synchronization signal of an input image signal; a clock generation circuit for generating a sampling clock synchronized with the horizontal synchronization signal output from the delay circuit; An A / D converter for sampling based on a sampling clock generated from a clock generation circuit, and comparing the image data output from the A / D converter with a predetermined threshold value to determine a horizontal image start position of each horizontal line. And a detecting means for detecting a horizontal video end position, among horizontal video start positions detected in one field, a horizontal video start position closest to a horizontal period start position specified by a horizontal synchronization signal output from the delay circuit; The horizontal synchronization signal output from the delay circuit among the horizontal video end positions detected in one field. To calculate the number of sampling clocks corresponding to the distance between the horizontal video start position and the horizontal video end position of the input image signal for each field based on the horizontal video end position farthest from the horizontal period start position specified by By changing the amount of delay set for the delay circuit by a predetermined amount for each field, the phase of the sampling clock is changed by a predetermined amount for each field, and the number of sampling clocks calculated by the calculating means is changed. The set delay amount set in the delay circuit in the field when the value changes in the decreasing direction is retained as the first delay amount, and the field when the number of sampling clocks calculated by the calculating means changes in the increasing direction. The set delay amount set in the delay circuit is defined as a second delay amount. Holding means for calculating and holding an average value of the first delay amount and the second delay amount, and determining the obtained average value as an optimum delay amount to be set in the delay circuit in a steady state An automatic clock phase adjusting device in a pixel-compatible display device, comprising: an amount determining unit. 2. The optimum delay amount determining means, when the first delay amount and the second delay amount held in the holding means satisfy a relationship that the second delay amount is larger than the first delay amount. 2. The method according to claim 1, wherein an average value of the first delay amount and the second delay amount is calculated, and the obtained average value is determined as an optimal delay amount to be set in the delay circuit in a steady state. An automatic clock phase adjustment device in a pixel correspondence display device.