JP2001044086A - Laminating dielectric separation wafer and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To completely eliminate defects in a dielectric separation silicon island for a lamination dielectric separation wafer, and to improve the electrical characteristics on the surface of the silicon island. SOLUTION: On the surface of a mirror face wafer 10, anisotropy etching is performed for forming a groove 13 for dielectric separation. On the surface, a dielectric separation oxide film 14 is grown. A high-temperature polysilicon layer 16 is grown on the oxide film 14. The high-temperature polysilicon layer 16 is ground and polished. On the ground and polished high-temperature polysilicon layer 16, a low-temperature polysilicon layer 17 is formed and polished. A wafer 20 for a support substrate is laminated to a wafer 10 for an active layer at room temperature, by bringing the mirror faces into contact each other. Heat treatment is conducted. The outer-periphery part of the wafer 10 for the active layer is chamfered, and the wafer 10 is ground and polished. A lamination dielectric separation wafer W is obtained. The lamination dielectric separation wafer W is inserted into a crystal reaction pipe for conducting hydrogen anneal treatment in the atmosphere of a hydrogen gas at 1,200 deg.C for one hour. Oxygen in a dielectric separation silicon island 10A is diffused outwardly, and the oxygen concentration is reduced. Enzyme induction lamination defects in the silicon island 10A disappears completely to eliminate defects, and the electrical characteristics become satisfactory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bonded dielectric separated wafer and a method of manufacturing the same, and more particularly, to a bonded dielectric separated wafer having few small defects in a dielectric isolated silicon island and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a kind of bonded silicon wafer, a bonded dielectric separation wafer is known. A conventional bonded dielectric separation wafer has been manufactured through the steps shown in FIG. FIG. 5 is an explanatory view showing a manufacturing process of a conventional dielectric separation wafer. First, a single-crystal silicon ingot pulled up by the CZ method is subjected to block cutting, slicing, chamfering, polishing, and the like to obtain a silicon wafer 1 having a mirror-finished surface serving as an active layer wafer.
0 is prepared (FIG. 5A). Next, a mask oxide film 11 is formed on the surface of the silicon wafer 10 (FIG. 5).
(B)). The mask oxide film 11 is covered with a resist 12, and a window is formed on the resist 12 by a photolithographic method. A window of a predetermined pattern is formed in oxide film 11 through this window, and a part of the surface of silicon wafer 10 is exposed. Next, the resist 12 is removed, and the silicon wafer 10 is thereafter etched with an etching solution (IPA / KOH / H
Was immersed in _{2 O),} a window inside of the wafer surface is anisotropically etched (FIG. 5 (c)). In this manner, a dielectric isolation groove 13 having a V-shaped cross section is formed on the wafer surface. The term “anisotropic etching” used herein refers to etching in which the etching rate in the depth direction is higher than that in the horizontal direction, and the etching rate has direction dependency, due to the crystal plane orientation of the silicon wafer 10. It is.

Next, the mask oxide film 11 is removed (FIG. 5).
(D)). Then, a dielectric isolation oxide film 14 is formed on the wafer surface by oxidizing heat treatment (FIG. 5E).
As a result, an oxide film 14 is also formed on the surface of the dielectric isolation trench 13. Then, the wafer surface is cleaned. Subsequently, on the surface of the dielectric isolation oxide film 14, about 1200 to 13
The high-temperature polysilicon layer 16 is grown thicker by the high-temperature CVD method at 00 ° C. (FIG. 5F). Then, the outer peripheral portion of the wafer is chamfered and, if necessary, the back surface of the wafer is flattened. Next, the high-temperature polysilicon layer 16 on the wafer surface
Is ground and polished to a thickness of about 10 to 80 μm (FIG. 5).
(G)). Thereafter, if necessary, 55
A low-temperature polysilicon layer 17 having a thickness of 1 to 5 [mu] m is formed by a low-temperature CVD method at 0 to 700 [deg.] C. Then, the surface of the low-temperature polysilicon layer 17 is polished in order to achieve a mirror-finished bonding surface.

On the other hand, a silicon wafer 20 serving as a wafer for a supporting substrate is prepared by the same manufacturing method as the wafer for an active layer (FIG. 5 (h)). This is a mirror-finished wafer surface. Next, this silicon wafer 20
The silicon wafer 10 for the active layer wafer
Are bonded by bringing their mirror surfaces into contact with each other (FIG. 5).
(I)). Then, heat treatment is performed to increase the bonding strength of the bonded wafer. Next, FIG.
As shown in (j), the outer peripheral portion of the active layer wafer is chamfered in the bonded wafer, and the surface of the active layer wafer is further ground and polished. The grinding amount of the wafer for the active layer is such that the dielectric isolation oxide film 14 is exposed to the outside, and the dielectric isolation silicon island 10A partitioned by the dielectric isolation oxide film 14 appears on the surface of the high-temperature polysilicon layer 16. Until it does.

[0005]

The single crystal silicon ingot from which the wafer for the active layer and the wafer for the support substrate are cut out contains oxygen as an impurity in a supersaturated state. This is because the single crystal silicon ingot was pulled by the CZ method. Oxygen contained in the ingot in this supersaturated state plays a useful role such as increasing the mechanical strength of the ingot and serving as a gettering site for capturing impurities. On the other hand, microscopic oxidation-induced stacking faults (OS
F; Oxidation Induced Stacking Fault), COP (Cr
ystal Originated Particles) or BMD (Bulk Micro D
efect). Devices on a silicon wafer are manufactured from the surface layer to a depth of 10 μm or less. In the case of a dielectric isolation wafer, a device is manufactured on a dielectric isolation silicon island (active region) having a thickness of several tens μm to several μm. As a result, the crystal characteristics of the dielectrically isolated silicon island become important. That is, the surface and the surface layer portion of the dielectric isolation silicon island are required to be defect-free. However, as described above, this dielectric-isolated silicon island is also manufactured from an active layer wafer which is a CZ wafer. For this reason, supersaturated oxygen also exists in the dielectric isolation silicon island. This causes minute defects (oxidation-induced stacking faults) to appear in the islands, causing various inconveniences in the device manufacturing process and the like. For example, the oxide film withstand voltage of an oxide film (eg, a gate oxide film of a MOS device) formed on the surface of this island has been reduced.

[0006] Therefore, the inventor of the present invention is able to diffuse supersaturated oxygen in the dielectrically isolated silicon islands outward by performing a hydrogen annealing treatment on the bonded bonded dielectric isolation wafer, thereby reducing the oxygen concentration in this region. The present invention has been completed by paying attention to the fact that the defect is largely reduced and the defect is eliminated.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a bonded dielectric isolated wafer capable of making the dielectric isolated silicon island defect-free and thereby improving the electrical characteristics of the silicon island surface, and a method of manufacturing the same. , Its purpose.

[0008]

According to a first aspect of the present invention, there is provided a wafer for a support substrate, and a wafer for an active layer bonded to a surface of the wafer for the support substrate. A bonded dielectric separation wafer in which a plurality of dielectric isolation silicon islands insulated from each other by a dielectric isolation oxide film are formed on a surface of a polysilicon layer laminated on the surface, wherein the dielectric isolation silicon island is formed. This is a bonded dielectric separation wafer that has been subjected to a hydrogen annealing treatment. As the conditions of the hydrogen annealing treatment, a preferable annealing temperature is 1050 to 1250 ° C., and a preferable annealing time is 1 to 4 hours. For example, heating is performed at 1200 ° C. for one hour in a hydrogen gas atmosphere. These matters also apply to the invention described in claim 2.

According to a second aspect of the present invention, a dielectric isolation groove is formed on the surface of the active layer wafer, and a dielectric isolation oxide film is formed on the surface of the active layer wafer including the surface of the dielectric isolation groove. A polysilicon layer is grown on the surface of the dielectric isolation oxide film by the CVD method, and the surface of the active layer wafer is superimposed on the surface of the support substrate wafer so that they are bonded to each other. Is ground and polished from the back side to reveal a plurality of dielectric isolation silicon islands separated by a dielectric isolation oxide film on the polished surface, and thereafter, the bonded dielectric isolation wafer is subjected to a hydrogen annealing treatment. This is a method for manufacturing a bonded dielectric separation wafer to be applied.

As a method for growing the polysilicon layer, a high-temperature CVD method can be employed. In this method, a source gas containing silicon is introduced into a reaction furnace together with a carrier gas (such as H ₂ gas), and silicon generated by thermal decomposition or reduction of the source gas is deposited on a silicon wafer heated to a high temperature. Is the way. The compound containing silicon is usually SiCl ₂ H ₂ , SiCl ₄ , S
iHCl _{3 and the} like. The reaction furnace used at this time includes a high-frequency induction heating furnace, a lamp heating furnace, and the like.

The growth temperature of polysilicon by the high-temperature CVD method differs depending on the heating method of the furnace. In a general high-frequency induction heating furnace used for this purpose, 1200 to 1290
° C, especially 1300-1280 ° C is preferred. 1200 ° C
If it is less than 1, the silicon wafer is easily broken. If it exceeds 1290 ° C., slip occurs and the wafer is easily broken. The thickness of the polysilicon layer is obtained by multiplying the depth of the anisotropic etching by two to three times and adding the thickness of the polysilicon layer to be left. If the thickness of the polysilicon layer is less than twice the depth of the anisotropic etching, the grooves of the anisotropic etching may not be sufficiently filled. If it exceeds three times, it becomes unnecessarily thick and uneconomical. As the anisotropic etching solution, K
OH (IPA / KOH / H ₂ O), KOH (KOH / H
₂ O), can be used KOH (hydrazine _/ KOH / _H 2 O). Normal conditions can be applied to the anisotropic etching. Also, when forming a window for anisotropic etching in the resist on the wafer surface side, it can be performed under general conditions.

[0012]

According to the present invention, a bonded dielectric separation wafer is manufactured, and thereafter, the bonded dielectric separation wafer is subjected to a hydrogen annealing treatment. As a result, supersaturated oxygen in the dielectric isolation silicon island where the device is manufactured is diffused outward. Therefore, this region is made defect-free, and the electrical characteristics of the silicon island can be improved. For example, the withstand voltage of the oxide film can be increased.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A bonded dielectric separation wafer and a method for manufacturing the same according to an embodiment of the present invention will be described below. Here, the bonded dielectric separation wafer described in the section of the prior art will be described as an example. Therefore, the same parts are denoted by the same reference numerals. FIG. 1 is an enlarged sectional view of a main part of a bonded dielectric isolation wafer according to one embodiment of the present invention. FIG. 2 is a flowchart showing a method for manufacturing a bonded dielectric isolation wafer according to one embodiment of the present invention. First, a silicon wafer 10 having a mirror-finished surface to be an active layer wafer is prepared and prepared (FIG. 2).
(A)). Specifically, the single crystal silicon ingot pulled up by the CZ method is cut into blocks, sliced,
It is manufactured by chamfering, polishing and the like.

Next, after cleaning this silicon wafer 10, the wafer surface is covered with a mask oxide film 11 (FIG. 2).
(B)). Instead of the mask oxide film 11, a nitride film may be grown by a CVD method.

Next, a resist film 12 is deposited on the mask oxide film 11. Then, windows of a predetermined pattern are formed in the resist film 12 by a photolithography process. Subsequently, a window having the same pattern is formed in the mask oxide film 11 through this window, and a part of the surface of the silicon wafer 10 is exposed. Next, the resist film 12 is removed. Then, the wafer surface is cleaned. Further, this silicon wafer 10 is treated with an anisotropic etching solution (IPA / KOH / H ₂ O).
For a predetermined time. As a result, recesses (depressions) in a predetermined pattern are formed on the surface of the silicon wafer. That is, anisotropic etching is performed on the wafer surface to form a dielectric isolation groove (recess) 13 having a V-shaped cross section (FIG. 2C).

Next, the mask oxide film 11 is removed (FIG. 2).
(D)). Thereafter, if necessary, a dopant is implanted into silicon, and then a dielectric isolation oxide film 14 is formed on the wafer surface by oxidizing heat treatment (FIG. 2E).
As a result, a dielectric isolation oxide film 14 is also formed on the dielectric isolation trench 13. Next, the wafer surface is cleaned.

Subsequently, a high-temperature polysilicon layer 16 is formed on the dielectric isolation oxide film 14 by a high-temperature CVD method at about 1200 ° C.
Is grown to a thickness of 150 μm (FIG. 2F). Then, the outer peripheral portion of the wafer is chamfered and, if necessary, the back surface of the wafer is flattened. Then, the high-temperature polysilicon layer 16 is ground and ground until its thickness becomes about 30 μm.
Polishing (FIG. 2 (g)). After that, low temperature CV of 600 ° C
A low-temperature polysilicon layer 17 having a thickness of about 3.0 μm is formed on the wafer surface by the method D. Further, the surface of the low-temperature polysilicon layer 17 is polished in order to mirror the bonding surface.

On the other hand, a silicon wafer 20 to be a support substrate wafer having the same thickness and the same diameter as the silicon wafer 10 is prepared by the same manufacturing method as the silicon wafer 10 (FIG. 2 (h)). A silicon oxide film 21 as an insulating film is formed on the surface of the supporting substrate wafer 20 by wet O ₂ oxidation to a thickness of 1 μm. Next, the silicon wafer 10 for the active layer is bonded to the silicon wafer 20 at room temperature with its mirror surfaces in contact with each other (FIG. 2 (i)). Thereafter, a predetermined heat treatment for increasing the bonding strength of the bonded wafer is performed. Then, as shown in FIG. 2 (j), the outer peripheral portion of the silicon wafer 10 for the active layer is chamfered, and if necessary, the oxide film 21 of the silicon wafer 20 for the support substrate is removed by HF cleaning. The wafer 10 is ground and polished.
The amount of grinding / polishing at this time depends on the dielectric isolation oxide film 14.
Are exposed to the outside, the dielectric isolation silicon islands 10A defined by the dielectric isolation oxide film 14 appear on the surface of the high-temperature polysilicon layer 16, and the adjacent silicon islands 10A are completely separated from each other. Thus, the bonded dielectric separation wafer W is obtained.

After that, the bonded dielectric separation wafer W is subjected to a hydrogen annealing treatment (FIG. 2 (k)). Specifically, the bonded dielectric separation wafer W is inserted into a quartz reaction tube of an annealing furnace. Then, a heat treatment is performed on the bonded dielectric separation wafer W at 1200 ° C. for one hour in a hydrogen gas atmosphere. As described above, when the bonded dielectric separation wafer W is heated to a high temperature in a hydrogen gas atmosphere, the oxygen existing in the dielectric separation silicon island 10A is reduced more than when heat treatment is performed in, for example, a nitrogen gas or oxygen gas atmosphere. Large amounts are diffused out. It is considered that this is because diffusion of oxygen into the gas phase on the surface of the dielectric isolation silicon island 10A increases. By the hydrogen annealing treatment, the oxygen concentration of the dielectric isolation silicon island 10A is greatly reduced. As a result, this dielectric isolation silicon island 10A
Oxygen-induced stacking faults in the (active region) disappear almost completely. Thereby, the inside of this region is made defect-free, and as a result, for example, the oxide film breakdown voltage of the oxide film formed on the surface of the silicon island 10A can be increased.

Here, when the conventional method (without hydrogen annealing) is compared with the present invention (with hydrogen annealing), the gate oxidation formed on the surface of the dielectric isolation silicon island is actually performed. The evaluation results of the oxide withstand voltage of the film are described. FIG. 3 is an explanatory view showing an evaluation test method of an oxide film breakdown voltage of a bonded dielectric isolation wafer. FIG. 4 (a)
FIG. 5 is an explanatory diagram showing a distribution of measurement points of oxide film breakdown voltage in a bonded dielectric isolation wafer according to one embodiment of the present invention. FIG. 4B is an explanatory diagram showing a distribution of measurement points of oxide film breakdown voltage in a bonded dielectric isolation wafer according to the conventional means. First, referring to FIG. 3, a specific test method for evaluating the withstand voltage of an oxide film of a bonded dielectric isolation wafer will be described.

As shown in FIG. 3, in each dielectric isolation silicon island 10A of the bonded dielectric isolation wafer W1, an N ⁺ region 30 doped with phosphorus P at a high concentration is formed along the dielectric isolation oxide film 14. Is provided. The oxygen concentration of the dielectric isolation silicon island 10A is Oi = 1.3.
It is 0 × 10 ¹⁸ / cm ³ . An electrode 31 made of aluminum is formed on the surface portion 30a of the N ⁺ region 30. Further, a gate oxide film 32 having a thickness of 25 nm and a film area of 20 mm ² is formed at a position separated from the electrode 31 by a predetermined distance. On this gate oxide film 32,
An electrode 33 made of polysilicon is formed. The electrode 33 has a thickness of 500 nm and is doped with phosphorus at a predetermined concentration. These electrodes 31 and 33 have a DC power supply 3
4, measuring terminals of an oxide film breakdown voltage measuring device having an ammeter 35 and a voltmeter 36 are connected to each other.

In measuring the oxide film breakdown voltage of the gate oxide film 32, a DC applied voltage of 10 MV / cm is applied for 10 seconds, and then the voltage is applied again only once.
At this time, the amount of current flowing between the electrodes 31 and 33 is measured, and
When the current density exceeded 100 μA / cm ² , it was considered that dielectric breakdown of the gate oxide film 32 had occurred. Note that a total of 181 measurement points were arranged on the silicon wafer 10. Then, the state of dielectric breakdown of the gate oxide film 32 at each point was examined. FIG. 4 shows the results. FIG.
As apparent from (a), in the case of the bonded dielectric separation wafer W according to the present invention, dielectric breakdown did not occur at all of the 181 measurement points. On the contrary,
In the case of the bonded dielectric separation wafer of the conventional method shown in FIG. 4B, dielectric breakdown occurred at 25 points out of 181 points. In FIG. 4A and FIG. 4B, the white area indicates no dielectric breakdown, and the black area indicates the dielectric breakdown. As described above, it has been found that if a hydrogen annealing treatment is performed after the bonded dielectric separation wafer W is manufactured, the oxide film breakdown voltage of the gate oxide film 32 increases. That is, the electrical characteristics of the silicon island 10A are increasing.

[0023]

According to the present invention, since the bonded dielectric isolation wafer is subjected to the hydrogen annealing treatment, the dielectric isolation silicon island on which the device is manufactured can be made defect-free. As a result, the electrical characteristics of the silicon island, for example, its oxide film breakdown voltage characteristics can be improved.

[Brief description of the drawings]

FIG. 1 is an enlarged sectional view of a main part of a bonded dielectric separation wafer according to one embodiment of the present invention.

FIG. 2 is a flowchart showing a method for manufacturing a bonded dielectric isolation wafer according to one embodiment of the present invention.

FIG. 3 is an explanatory view showing an evaluation test method of an oxide film breakdown voltage of a bonded dielectric isolation wafer according to one embodiment of the present invention.

FIG. 4A is an explanatory view showing a distribution state of measurement points of an oxide film breakdown voltage in a bonded dielectric isolation wafer according to one embodiment of the present invention. (B) is an explanatory view showing a distribution state of measurement points of the oxide film breakdown voltage in the bonded dielectric isolation wafer according to the conventional means.

FIG. 5 is an explanatory view showing a manufacturing process of a conventional dielectric separation wafer.

[Explanation of symbols]

 Reference Signs List 10 silicon wafer (active layer wafer), 10A dielectric isolation silicon island, 12 silicon wafer (support substrate wafer), 13 dielectric isolation groove, 14 dielectric isolation oxide film, 16 polysilicon layer, W bonded dielectric isolation Wafer.

Claims (2)

[Claims] 1. A wafer for a support substrate, and a wafer for an active layer bonded to a surface of the wafer for the support substrate, wherein a surface of a polysilicon layer laminated on the surface of the wafer for the active layer has a dielectric A bonded dielectric separation wafer formed with a plurality of dielectrically separated silicon islands insulated from each other by a body separation oxide film, the bonded dielectric being subjected to a hydrogen annealing treatment after the formation of the dielectrically separated silicon islands. Body separation wafer. 2. A dielectric isolation groove is formed on the surface of the active layer wafer, and a dielectric isolation oxide film is formed on the surface of the active layer wafer including the surface of the dielectric isolation groove. A polysilicon layer is grown on the surface by the CVD method, and the surface of the active layer wafer is superimposed on the surface of the support substrate wafer so that they are bonded to each other.
Polishing to reveal a plurality of dielectric isolation silicon islands separated by a dielectric isolation oxide film on the polished surface, and thereafter performing hydrogen annealing on the bonded dielectric isolation wafer. Production method.