JP4420986B2 - Shallow trench isolated semiconductor substrate and method of manufacturing the same - Google Patents

Shallow trench isolated semiconductor substrate and method of manufacturing the same Download PDF

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JP4420986B2
JP4420986B2 JP30959096A JP30959096A JP4420986B2 JP 4420986 B2 JP4420986 B2 JP 4420986B2 JP 30959096 A JP30959096 A JP 30959096A JP 30959096 A JP30959096 A JP 30959096A JP 4420986 B2 JP4420986 B2 JP 4420986B2
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oxide film
semiconductor substrate
groove
method
step
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JPH09205140A (en
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浩幸 上條
淳史 八木下
恒博 北
憲彦 土屋
嘉明 松下
華織 梅澤
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株式会社東芝
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[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a substrate for a semiconductor integrated circuit such as an LSI and a method for manufacturing the same, and more particularly to an element isolation technique for a semiconductor integrated circuit.
[0002]
[Prior art]
To form an LSI, an element that electrically separates one element formation region from another element formation region around an element formation region in which an active element such as a transistor or a passive element such as a resistor or a capacitor is formed It is necessary to form an isolation region. In the development of MOS / LSI technology and bipolar LSI technology, element isolation technology for forming this element isolation region has always been one of the most important technical issues, but it will be increasingly important in the future. It is done. One development that marks the era in the history of this element isolation technology can be said to have been the development of LOCOS (LOCal Oxidation of Silicon) technology that can distinguish the element formation region and the element isolation region in a self-aligning manner. As shown in FIG. 15, the LOCOS technology (LOCOS method) uses a nitride film (SiThreeNFourFilm) 88 is used as a mask for selective oxidation, and SiThreeNFourAn oxide film (SiO2) formed on the Si surface where there is no film2Film) 82 is used as an insulating layer in the element isolation region. It is no exaggeration to say that this element isolation technology and polysilicon wiring technology brought about the rise of today's LSI industry. However, since the microfabrication era from submicron to deep submicron has been reached, this LOCOS technology is finally approaching its limits. The biggest problems are the erosion of the element formation region (active region) due to the presence of so-called bird's beaks and the generation of crystal defects due to the generation of local stress during the formation of the field oxide film. In particular, bird's beaks are a hindrance to high integration for VLSI or ULSI, and the thickness of oxide film 82 must be reduced in order to reduce erosion by bird's beaks and miniaturization. However, reducing the thickness of the oxide film 82 causes a problem that the withstand voltage between elements decreases. In order to overcome this, various improvements of the LOCOS method and new separation techniques have been proposed. For example, as an improved element isolation technique based on the LOCOS method, an improved coplanar method, a direct nitride film mask method, or SWAMI (Side WALL Masked Isolation) is known, and a selective epitaxial method, a U-groove method, and the like have also been proposed. In addition to these element isolation techniques, an oxide film embedding method called a BOX (Buried OXide) method as shown in FIG. 16 has attracted attention as an element isolation technique in VLSI and the like of submicron and deep submicron dimensions. This is because the U-groove is formed in the silicon substrate 5 and then SiO.2This is an element isolation technique for depositing an insulating material 77 such as a so as to fill a U groove.
[0003]
Various requirements such as uniformity, flatness, step coverage (step coverage), film quality, and low process temperature are imposed on the insulating film deposition technique used in the BOX method. Of these, step coverage and process temperature reduction are particularly important. High-quality insulating films are required at low temperatures for the manufacture of semiconductor integrated circuits, such as gigascale integrated circuits (GSI), which are becoming increasingly highly integrated. In response to this requirement, monosilane (SiH) that can be formed at a relatively low temperature (300 to 450 ° C.).Four) And N2LTO (Low Temperature Oxide), which is a CVD technique using O and the like, is known, but LTO generally has poor step coverage and poor film quality although it depends on the formation conditions. In particular, an oxide film formed by an atmospheric pressure CVD method or a low pressure CVD method exhibits a tensile stress and has a defect that crack resistance is weak.
[0004]
In view of these requirements, TEOS (tetraethyl orthosilicate: Si (OC2HFive)FourResearch on CVD technology using organic silicon materials such as) is active. For example, TEOS and OThreeAccording to this reaction, the insulating film can be formed at a low temperature of 450 ° C. or lower, and the step coverage is good.
[0005]
[Problems to be solved by the invention]
Among the BOX methods shown in FIG. 16, a relatively shallow groove is advantageous for miniaturization, and is also referred to as a shallow trench isolation (STI) method. However, this STI method is advantageous in terms of miniaturization of the element as compared with the LOCOS method, but an insulating material (for example, silicon of silicon) and a semiconductor substrate such as silicon that becomes an active element region (element forming region). Since the thermal expansion coefficient differs from that of the oxide), stress is generated in the semiconductor substrate during the formation of the element isolation region or during the LSI manufacturing process after the element isolation region is formed, and is indicated by a thick solid line in FIG. There is a problem in that crystal defects such as dislocations 12 are generated. In particular, when the formation of silicon oxide is performed using an organic silicon source as a raw material, the problem of impurities caused by the organic silicon source raw material purification technology has been highlighted. That is, at present, it is difficult to obtain a high-purity organic silicon source.2) Other than impurities (eg H2O, organic matter, etc.) is SiO2Residual or adsorbed inside. Therefore, various problems resulting from the dissociation of these impurities are caused by the subsequent heat process at 800 to 1000 ° C. The water | moisture content as an impurity in an organic silicon source raw material is normally contained 100-20 ppm. For this reason, for example, in a silicon device, a silicon substrate and embedded SiO2The thermal expansion coefficient is different from that of (embedded oxide film), and film shrinkage occurs due to dissociation of moisture in the buried oxide film, resulting in excessive compressive stress being applied to the silicon substrate. Further, the conventional STI structure shown in FIG. 16 has a drawback in that crystal defects are easily introduced into the substrate during the element isolation region formation or in the thermal process accompanying the subsequent element manufacturing process. In other words, the conventional element isolation technique based on the STI method using an organic silicon source has a primary problem that crystal defects such as dislocations 12 are easily generated, propagated and propagated on the surface layer of the substrate, and accompanying these problems. However, these crystal defects easily capture metal impurities, and a large number of crystal defects occur in the element formation region (active region), so that there is a secondary problem that electrical defects such as junction leakage are likely to occur. .
[0006]
In particular, in the actual LSI manufacturing process, in addition to the stress due to the existence of the element isolation region itself, various multilayer films having different properties such as stress due to damage caused by ion implantation, and electrodes, interlayer insulating films, etc. The stress accompanying the formation is generated, and crystal defects are likely to occur. There is also a synergistic effect of crystal defects caused by the STI structure itself and crystal defects caused by the other. Crystal defects generated in the substrate easily capture metal impurities and the like. For this reason, in the conventional STI method, there is a problem that electrical defects such as junction leakage increase and dielectric breakdown of the gate oxide film occur due to the presence of crystal defects in the active layer (element formation region). there were. Therefore, the development of element isolation technology that does not cause crystal defects in the element formation region is an important issue to be solved in future miniaturized LSI manufacturing.
[0007]
That is, in element isolation technologies such as miniaturized GSI, ULSI, and VLSI, conditions such as the absence of bird's beaks, a flat surface, and the absence of crystal defects are required. Although there is no bird's beak problem in the STI method, the suppression of the flatness of the surface and the occurrence of crystal defects are important issues to be solved.
[0008]
In view of the above problems, the present invention is a semiconductor device using an STI method or a buried element isolation method similar to the STI method,2An object of the present invention is to provide a semiconductor substrate for a highly integrated semiconductor in which crystal defects generated in an element formation region due to the stress of the semiconductor are reduced.
[0009]
Another object of the present invention is SiO2The present invention provides a method for manufacturing a semiconductor substrate capable of reducing crystal defects caused by the stress of the semiconductor substrate, suppressing a pn junction leakage current in an element formation region, and simultaneously achieving high integration density.
[0010]
Still another object of the present invention is to provide a method for manufacturing a semiconductor substrate, in which a high-quality oxide film having an etching rate equivalent to that of a thermal oxide film can be embedded in the element isolation region at a low temperature.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, the first feature of the present invention is that a surface of a semiconductor substrate is formed as illustrated in FIGS. 1 (e), 7 (f), 9 (g) and 14 (e). An element isolation semiconductor substrate comprising a plurality of groove portions 6 formed in a portion, a buried oxide film 71 formed inside the groove portion 6, and an element formation region between the groove portions 6 and 6, The buried oxide film 71 is formed by either an organic silicon-based CVD method, a so-called SOG (Spin-on-glass) method, such as a resin glass coating method or an anodic oxidation method, followed by heat treatment at a temperature of 1100 to 1350 ° C. The oxide film is made. Here, the “plurality of grooves” means that a plurality of grooves are observed in a cross section when observed on a predetermined cut surface, and the shape on the plane pattern is not limited. That is, in a fixed case, these groove portions may be continuously formed as one groove portion as a planar pattern. For example, although the corresponding plan view of FIG. 1 is omitted, the plurality of groove portions 6 shown in FIG. 1 (a) are n as shown in the central portion of FIG. 1 (e).+Source region 91, n+It should be understood that it can be understood that the MOS transistor or the like having the drain region 92 is formed as an integral region surrounding the element formation region where the drain region 92 is formed. Alternatively, as shown in FIG. 12, the buried oxide film 71 may be arranged in an island shape around the element formation region and may not be completely surrounded. In any case, when two or more grooves are present so as to sandwich the element formation region when observed in a certain cross section, it corresponds to “a plurality of grooves” in the present invention. Although the object of the present invention can be achieved even if the oxide film is heat-treated at a temperature of 1350 ° C. or higher, it is difficult to configure the apparatus such as a reaction tube or a furnace for heat treatment, and contamination from the furnace to the semiconductor substrate is also caused. It becomes a problem, so it is not realistic considering the current technology. It will be apparent to those skilled in the art that the temperature cannot be higher than the melting point of the oxide film.
[0012]
Preferably, in the first feature, the depth d of the grooves 6 formed on the surface of the semiconductor substrate and the width l of the openings of the grooves 61Aspect ratio d / l defined by the ratio of1Is 10 or less. As shown in FIG. 10, the first feature of the present invention is that the defect density observed in the element formation region is reduced when the aspect ratio is 10 or less, and the stress of the buried oxide film 71 is insufficiently reduced when the aspect ratio is 10 or more. This is because it has been experimentally clarified that the defect density due to the stress is not reduced. Preferably, the groove width l1Is the minimum space width, and the width l of the element formation region2Defined in this predetermined direction in a line-and-space repeating pattern in a predetermined direction with the minimum line width as1And l2Ratio to1/ L2Is 1.5 or less. As shown in FIG.1/ L2If it is 1.5 or more, the stress of the oxide film cannot be reduced even by heat treatment at 1100 ° C. to 1350 ° C., and crystal defects occur. This l1/ L2Is defined with respect to a certain direction, and is a direction orthogonal to the repeating direction of the line and space pattern, that is, a direction orthogonal to the cutting plane XX in FIG. The ratio of the pattern dimensions of the pattern that does not become the minimum line width or the minimum space width may be 1.5 or more. FIG. 12 shows a case where the line and space pattern exists in two directions. In FIG. 12, the ratio l in the XX direction.1x/ L2xIs defined, and the ratio is 1 in the Y-Y direction.1y/ L2yIs defined. In such a case, the ratio should be 1.5 or less in at least one of the directions. For example
l1x/ L2x≦ 1.5 …… (1)
l1y/ L2y> 1.5 (2)
If so, equation (1) may be adopted. In the opposite case, equation (2) may be adopted. Of course the ratio l in both directions1x/ L2x, L1y/ L2yBoth of them may be 1.5 or less. “1 defined in a predetermined direction” of the present invention1And l2As described above, the “ratio to” is defined in any one direction, and the ratio l in the defined direction.1/ L2If it is 1.5 or less, it should be understood that the other directions are not questioned.
[0013]
The second feature of the present invention is the element isolation semiconductor substrate having the shape as illustrated in FIGS. 1E, 7F, 9G, and 14E, which is the same as the first feature. The buried oxide films 25 and 71 are amorphous silicon oxide films each including a ring structure having a five-membered ring or more and a ring structure having a four-membered ring or less in a predetermined ratio.
[0014]
Here, the predetermined ratio corresponds to a three-membered ring, a four-membered ring, or a multi-membered ring structure having five or more members as shown in FIGS. 4 (a) and 4 (b). The ratio of the integrated intensity of each Raman shift to the whole (integrated intensity of all spectra) means a predetermined ratio. That is, as shown in FIGS. 4 (a) and 4B (b), the wave number is 300 to 700 cm.-1It means the ratio of the integrated intensity of each Raman shift when the entire spectral region is. Here, the integrated intensity of each Raman shift is defined within a predetermined spectral range including the corresponding peak.
[0015]
That is, as shown in FIG.
(i) Lamammaft integrated intensity ratio corresponding to five or more rings is substantially 85% or more of the whole,
(ii) the integral intensity ratio of the Raman shift corresponding to a 4-membered ring or a 3-membered ring is substantially 15% or less of the whole,
Amorphous silicon oxide film (SiO2) that satisfies at least one of the two conditions2Therefore, the stress in the buried oxide films 25 and 71 and the stress at the interface between the buried oxide films 25 and 71 and the semiconductor substrates 5, 16, and 23 are alleviated, and dislocations in the element formation region are reduced. Generation | occurrence | production will be suppressed. Here, “substantially 85% or more” means that about 80% or more is allowed as indicated by an error bar in FIG. “Substantially 15% or less” means that about 20% or less is allowed. When both the 3-membered ring and the 4-membered ring are included, the sum of the 3-membered ring and the 4-membered ring may be substantially 15% or less. That is, it should be understood that 85% or more and 15% or less in the present invention means the relationship shown in FIG. Of course, the background component is removed in the calculation of the integral intensity ratio in the second feature of the present invention. According to the structure of the second feature of the present invention, the leakage current of the pn junction formed in the element formation region is reduced, and a high-density integrated circuit having good characteristics can be realized. Note that the etching rate (etching rate) of the oxide film containing substantially 85% or more of the 5-membered ring or more and substantially 15% or less of the 4-membered ring or 3-membered ring of the present invention is NH as shown in FIG.FourThe etching rate by F is 130 nn / min or less, which is substantially equal to the corresponding etching rate of the thermal oxide film. Therefore, as a simple verification of the composition of a five-membered ring or more and a four-membered ring, the etching rate may be examined.
[0016]
The third feature of the present invention is to include at least the following steps as exemplified in FIGS. 1A to 1E or FIGS. 7D to 7F. That is,
(A) a first step of forming a plurality of grooves 6 in a part of the surface of the semiconductor substrates 5 and 16 as shown in FIG. 1 (a) or FIG. 7 (d);
(B) a second step of burying oxide films 7 and 71 in the groove 6 by organic silicon CVD as shown in FIG. 1B, FIG. 7C, or FIG.
(C) at least a third step of heat-treating the oxide film 71 at a substrate temperature of 1100 ° C. to 1350 ° C. As described above, the “plurality of groove portions” is a concept when viewed in a constant cross section. The organic silicon-based CVD method is TEOS (Tetraethylorthosilicate; Si (OC2HFive)Four), TMOS (Tetramethoxysilane; Si (OCHThree)Four), TPOS (Tetrapropoxysilane; Si (OCThreeH7)Four), Or DADBS (Diacetoditertiarybutoxysilane; (CFourH9O)2Si- (OCOCHThree)2) Or the like, which is an organic silicon source.
[0017]
Preferably, the organic silicon-based CVD method in the second step is any one of an atmospheric pressure CVD method, a low pressure CVD method, a plasma CVD method, a photo CVD method, and a liquid phase CVD method. Atmospheric pressure CVD method is O2Was introduced into an ozonizer and discharged to form ozone (OThreeThe so-called ozone-based atmospheric pressure CVD method may be used. Low pressure CVD (LPCVD) is, for example, TEOS-OThreeThis is a CVD method in which the above reaction is performed at a reduced pressure of 6.7 kPa or the like. What is plasma CVD? 13.56MHzOr 150KHzTEOS, O using a plasma discharge of a degree2, He or the like may be used. The photo-CVD method is light mainly using ultraviolet light energy such as excimer laser light, high-pressure mercury lamp, mercury-xenon lamp, etc. by ArF (193 nm), KrF (249 nm), XeCl (308 nm), XeF (350 nm), etc. The reaction may be performed. The liquid phase CVD method is, for example, O excited by RF discharge.2And TMS (Tetramethylsilane; Si (CHThree)Four) At −40 ° C.
[0018]
Preferably, the oxide film formed by organic silicon CVD is H.2Reducing gas such as He, Ne, Ar, Kr, Xe, etc., O2, N2, HCl, CO or CO2Or a mixed gas composed of two or more gases selected from these.
[0019]
Further, the formation of the buried oxide film in the second step is specifically performed by depositing the oxide film 7 thicker than the groove as shown in FIG. 1B, and then, as shown in FIG. Preferably, the method includes planarizing the surface until the surface of 5 is substantially exposed. Here, “the surface of the semiconductor substrate is substantially exposed” does not necessarily need to be etched back until the semiconductor substrate 5 is completely exposed. For example, if necessary in the subsequent steps, 50 nm to 100 nm, or This means that even if an extremely thin oxide film of about 300 nm is etched back so as to remain on the surface of the semiconductor substrate 5 and the surface of the semiconductor substrate is planarized, it is understood that it is “substantially exposed”. Either the planarization process or the heat treatment process may be performed first. Therefore, contrary to the above, as the second step, only the step of forming an oxide film thicker than the depth of the groove by organic silicon CVD is used, and after the heat treatment in the third step, the surface flattening step is performed as the fourth step. You may go.
[0020]
The important point in the third feature of the present invention is the heat treatment temperature (annealing temperature). FIG. 2 shows a result of trial manufacture of an element isolation semiconductor substrate structure by performing heat treatment at intervals of 50 ° C. between 1000 ° C. and 1350 ° C. after the organic silicon CVD method. That is, after forming the element isolation region, an element isolation semiconductor substrate after forming an element such as a MOS transistor in an element formation region (SDG region) having a width of 0.3 μm between the trenches to constitute a MOS integrated circuit, It is the result of surface SEM observation. As shown in FIG. 2, it can be seen that dislocations frequently occur at a low-temperature heat treatment temperature of 1100 ° C. or lower. This is a dislocation similar to the dislocation 12 in the conventional STI substrate indicated by the thick solid line in FIG.
[0021]
The data in FIG. 2 is the result of measuring dislocation density in a 1 mm × 1 mm square region at five points in the surface by making dislocation pits manifest by selective etching and performing SEM observation, and averaging those values. At a heat treatment temperature of 1000 ° C. to 1100 ° C., there are about 10 dislocations 12 / μm similar to the thick solid line in FIG. 16 (prior art).2Although it has occurred, it can be seen that the heat treatment temperature is higher, that is, it is reduced in the temperature range of the present invention. Further, a MOS transistor is formed in the SDG region where the element isolation is performed, and n corresponding to the pn junction structure in the MOS transistor.+The result of measuring the junction leakage characteristics of the -p diode is shown in FIG. It can be seen that the leakage current is reduced in the substrate that has been heat-treated at 1100 ° C. or higher. This result is the cause of leakage current n+This reflects that the dislocation of the −p well junction is suppressed, and shows that the stress control of the buried oxide film according to the present invention is effective for suppressing dislocation and reducing the leakage current. Similar results are apparent when used for element isolation of the bipolar integrated circuit shown in FIG. 8, and the heat treatment in the temperature region (1100 ° C. to 1350 ° C.) of the present invention is more effective than the heat treatment at 1000 ° C. or lower. SiO2It can be seen that the stress is reduced and the junction leakage current is reduced.
[0022]
The fourth feature of the present invention is that
(A) A first semiconductor substrate having first and second main surfaces is prepared, and a direct bonding oxide film 24 is formed on the first main surface of the first semiconductor substrate 23 as shown in FIG. Is formed by an organic silicon-based CVD method, and after the first heat treatment is performed at a substrate temperature of 1100 ° C. to 1350 ° C., the surface is flattened as shown in FIG. A first step of performing a first heat treatment at a substrate temperature of 1100 ° C. to 1350 ° C. after performing
(B) The first semiconductor substrate 23 and the second semiconductor different from the first semiconductor substrate 23 through the direct bonding oxide film 25 whose surface is planarized as shown in FIG. The substrate 26 is directly bonded to form a so-called SOI (Silicon-On-Insulator) substrate, and then the back surface of the first semiconductor substrate 23 is ground, polished and etched as shown in FIG. 9C. The second step of adjusting to the thickness of
(C) Third groove portion 6 is formed in a part of the second main surface located on the side of first semiconductor substrate 23 not facing second semiconductor substrate 26 as shown in FIG. Step (FIG. 9 (d) is reversed from FIG. 9 (c)),
(D) a fourth step of forming a buried oxide film 7 as shown in FIG. 9 (e) in each of the plurality of trenches 6 by an organic silicon CVD method;
(E) a fifth step of performing a second heat treatment on the buried oxide film 7 at a substrate temperature of 1100 ° C. to 1350 ° C .;
And at least. Here, the first semiconductor substrate 23 and the second semiconductor substrate 26 do not have to be the same type of semiconductor substrate, and may be a combination of different types of semiconductors such as Si and SiC. That is, Group IV, III-V, II-VI group semiconductors and amorphous materials other than Si can be selected as the first and second semiconductor substrates. Note that the first heat treatment in the first step may be omitted, and the heat treatment at 1100 ° C. to 1350 ° C. under the same conditions as the first heat treatment may be performed at the time of direct bonding in the second step. Alternatively, the first heat treatment may be omitted, and the first heat treatment may be substituted by the second heat treatment in the fifth step.
[0023]
According to the configuration of the fourth feature of the present invention, the stress of the buried oxide film 71 and the direct bonding oxide film 25 is reduced, and the occurrence of crystal defects such as dislocations in the element formation region is suppressed.
[0024]
The fifth feature of the present invention is:
(A) A first semiconductor substrate having first and second main surfaces is prepared, and a plurality of grooves are formed in a part of the first main surface of the first semiconductor substrate 23 as shown in FIG. A first step of forming
(B) As shown in FIG. 14A, a bonding oxide film 25 is directly formed on the first main surface of the first semiconductor substrate by an organic silicon CVD method, and heat treatment is performed at a substrate temperature of 1100 ° C. to 1350 ° C. After the second step, the second step of planarizing the oxide film 25 on the first main surface of the first semiconductor substrate 23 as shown in FIG. 14B, or the first step as shown in FIG. 14B. A second step of performing a heat treatment at a substrate temperature of 1100 ° C. to 1350 ° C. after planarizing the oxide film 25 on the first main surface of the semiconductor substrate 23;
(C) The first semiconductor substrate 23 and the second semiconductor substrate 26 different from the first semiconductor substrate are directly bonded via the direct bonding oxide film 25 as shown in FIG. Thereafter, the thickness of the first semiconductor substrate 23 is decreased until a part of the direct bonding oxide film 25 is exposed, and, as shown in FIG. 14D, the second main surface of the first semiconductor substrate 23 is formed on the second main surface. A third step of forming an element formation region surrounded by the direct bonding oxide film 25;
And at least. Here, the first semiconductor substrate 23 and the second semiconductor substrate 26 do not have to be the same type of semiconductor substrate, and may be a combination of different types of semiconductors such as Si and SiC. That is, Group IV, III-V, II-VI group semiconductors and amorphous materials other than Si can be selected as the first and second semiconductor substrates.
[0025]
According to the fifth feature of the present invention, since the buried oxide film 25 and the direct bonding oxide film 25 can be simultaneously formed by one organic silicon-based CVD method, the number of processes is reduced as compared with the fourth feature. To do. That is, the direct bonding oxide film 25 exposed on the surface of the first semiconductor substrate 23 also functions as a buried oxide film. In addition, since the heat treatment process is less than the fourth feature, it contributes to the lowering of the process temperature.
[0026]
According to the configuration of the fifth feature of the present invention, the stress of the buried oxide film 25 and the direct bonding oxide film 25 is reduced, and the occurrence of crystal defects such as dislocations in the element formation region is suppressed.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. Although it is common in the representation of semiconductor device drawings, it should be understood that the following drawings are schematic rather than accurate dimensions. In particular, it should be noted that the relative relationship of the thickness of each layer is different from the actual ratio.
[0028]
(First embodiment)
FIG. 1E is a cross-sectional structure of a buried element isolation semiconductor substrate (a shallow trench isolation (STI) semiconductor substrate) for a MOS integrated circuit according to the first embodiment of the present invention. (D) is process sectional drawing which shows the manufacturing method to FIG.1 (e). In the element isolation semiconductor substrate according to the first embodiment of the present invention, a buried oxide film 71 is formed inside a groove formed from the surface of the semiconductor substrate 5 as shown in FIG. N between the element formation regions between the buried oxide film 71 and the buried oxide film 71.+Source region 91, n+A MOS transistor including drain region 92, gate oxide film 8, polysilicon gate electrode 98, source electrode 93, drain electrode 94, and interlayer insulating film 79 is formed.
[0029]
In the MOS integrated circuit formed on the element isolation semiconductor substrate according to the first embodiment of the present invention, the stress of the buried oxide film 71 is relaxed by performing heat treatment as shown below. The dislocation 12 as shown in FIG. 16 described in the prior art is not generated. Therefore, the pn junction leakage current due to dislocation is also reduced.
[0030]
The element isolation semiconductor substrate according to the first embodiment of the present invention can be manufactured by the following processes.
[0031]
(A) First, a silicon oxide film 17 of, eg, 100 nm is formed on the surface of a mirror surface silicon substrate having a plane orientation (100) by a steam oxidation method (wet oxidation method) or the like, and a photoresist (not shown) is formed on the surface of the oxide film 17. And the oxide film 17 is etched by photolithography using the photoresist as a mask. By this etching, a silicon etching mask pattern made of the oxide film 17 is formed, and the other surface of the silicon substrate 5 is exposed. Then, after removing the photoresist used for the oxide film etching, the exposed portion of the silicon substrate 5 is grooved with a width of 0.3 μm and a depth of 1 μm as shown in FIG. Form. The RIE of the silicon substrate 5 is, for example, CFFourAnd H2A high frequency power of 13.56 MHz is 0.22 W / cm at a pressure of 1.3 Pa.2This can be done by applying. Or SF6And O2Or mixed gas with CClFourFor example, RIE may be performed.
[0032]
(B) Next, after cleaning the substrate, as shown in FIG. 1B, an organic silicon source such as TEOS (Si (OC2HFive)FourAn oxide film 7 is formed by a CVD method using Before depositing this oxide film, either thermal oxide film or SiThreeNFourMay be formed thinly. This oxide film 7 is formed on the entire surface of the Si substrate with a thickness equal to or greater than the depth of the groove, for example, 1.1 μm in order to completely fill the groove. As a material for filling the groove, an oxidizing agent such as N is added to the organic silicon source.2O, O2, OThreeThe thing which added etc. may be sufficient. Organic silicon source, SiHFourSilicon hydride such as SiClFourThe trenches can be filled with a silicon oxide film even by CVD using silicon chloride alone or a mixture of two or more of these raw materials, or an oxide may be added to each raw material. .
[0033]
(C) Subsequently, as shown in FIG. 1C, the silicon substrate 5 in portions other than those embedded in the trenches is exposed to the outside by, for example, etching back by the CDE method, and is flattened.
[0034]
(D) The buried oxide film 71 formed by the organic silicon source is made of SiO.2In order to contain a large amount of impurities other than the above, for example, water, heat treatment is performed at 1100 to 1350 ° C. as shown in FIG. As shown in FIG. 1D, a slight curve (concave portion) is generated by the heat treatment. This process is for example N2Among them, heat treatment for about 2 hours is sufficient, but the atmosphere gas for heat treatment is O2, HCl, reducing gas, inert gas, the same result can be obtained. Although the case where the heat treatment is performed after removing and planarizing the oxide film on the substrate other than the element isolation region, the oxide film 7 on the substrate other than the element isolation region is removed after performing the heat treatment first. Thus, the same effect can be obtained even when flattening.
[0035]
(E) Finally, as shown in FIG. 1E, a MOS transistor is formed in the element formation region between the trenches, that is, the SDG region (width 0.3 μm). The formation of the MOS transistor is performed in a self-aligned manner using a polysilicon gate 78.+The drain region 92 may be formed by a standard MOS process, and description thereof is omitted here.
[0036]
The dislocation density in the element formation region after forming a MOS transistor in the element formation region as shown in FIG. 1 (e) is 1 / μm as shown in FIG.2It is as follows. The measurement result of the dislocation density in FIG. 2 is data on the average of 5 points in a 1 mm × 1 mm square region after SEM observation after selective etching of the sample.
[0037]
FIG. 3 shows a leakage current of a pn junction diode having a TEG pattern corresponding to the structure of the MOS transistor. That is, n+N formed between source region 91 and p well 5+FIG. 3 shows the p junction leakage current, which is reduced to 15 pA or less. Since the diode area of the TEG pattern is 350 μm × 240 μm, this is 1.7 × 10-8A / cm2This means that the leakage current density can be reduced to the following. The result of FIG. 3 indicates that the cause of the leakage current is n according to the first embodiment of the present invention.+This shows that the dislocation at the p-junction is suppressed.
[0038]
FIGS. 4A, 4B, and 5 show Raman scattering of the structure of the oxide film according to the first embodiment of the present invention that enables reduction of the dislocation density and reduction of the leakage current. It is the result of using and examining. That is, first, an oxide film is uniformly formed in a plane on a silicon substrate by the above-described method of forming a buried insulating film, and the oxide film (SiO2) Structure was investigated by Raman scattering spectroscopy. SiO2Has a small Raman scattering cross section, and in the measurement, the peak of Raman scattering due to vibration from the Si substrate becomes dominant.2From the spectrum of the Raman scattering shift of the silicon substrate on which the surface is formed, SiO 22SiO having a plurality of peaks as shown in FIG. 4A by subtracting the Raman scattering shift spectrum of the Si substrate on which no film is formed.2A spectrum of Raman scattering is obtained. Further, when this peak is separated by simulation, it can be separated into a 3-membered ring, a 4-membered ring, and a multi-membered ring having 5 or more members as shown in FIG. This method for separating the ring structure is described in C.I. J. et al. Breinker et al. . J. et al. Non-Cryst. Solids 82 (1986) 177 and the like. In FIG. 4A, annealing 1 is a heat treatment for 1 hour at 1000 ° C., and annealing 2 is a heat treatment for 1 hour at 1150 ° C. Also, annealing 1 and annealing 2 are both N2This is a heat treatment in a gas atmosphere.
[0039]
FIG. 5 shows the integrated intensity of the spectrum of each Raman shift for each heat treatment temperature, and the ratio to the total integrated intensity (hereinafter referred to as the integrated intensity ratio) is obtained. The total integrated intensity is wave number 300-700cm-1Is the value obtained by subtracting (excluding) the background value from the Si substrate. It can be seen that from 1100 ° C. at which the occurrence of dislocation is reduced, the integrated intensity ratio of three- and four-membered rings is reduced, and the integrated intensity ratio of multi-membered rings of five or more members is increased. That is, SiO2If the integral strength ratio of a 4-membered ring or less is substantially 15% or less of the whole, or the integral strength ratio of a multi-membered ring of 5 or more members is substantially 85% or more of the entire ring structure, It can be seen that the stress of the embedding material, which is the cause of the occurrence, is relaxed and the dislocation can be suppressed. Considering the error of measurement of Raman scattering, etc., as shown in FIG. 6, it can be said that the effect of the present invention can be obtained if the 4-membered ring or less is about 20% or less and the 5-membered ring or more is about 80% or more.
[0040]
FIG. 6 shows the etching rate (etching rate) of the oxide film according to the first embodiment of the present invention. NH of the oxide film heat-treated at the heat treatment temperature of the present invention, that is, 1100 ° C. to 1350 ° C.FourThe etching rate with the F (ammonium fluoride) solution is 130 nm / min or less, which is substantially equal to the etching rate of the thermal oxide film shown on the left side of FIG. An oxide film deposited by an organic silicon-based CVD method and not heat-treated, that is, an oxide film of so-called “as debo” has an etching rate of about 650 nm / min.FourEtched by F. Therefore, it can be seen that the high-temperature annealing of the present invention reduces the etching rate of the oxide film while reducing the five-membered ring or more to 80%. 5- or more-membered, three- or four-membered SiO measured by oxide film etching rate and Raman scattering2It can be said that the respective content ratios of correspond substantially.
[0041]
In the first embodiment of the present invention, the oxide film 7 is formed by the CVD method using an organic silicon source such as TEOS in the step (b). The oxide film forming method is such an organic silicon type. A method other than CVD may be used. For example, a so-called SOG (Spin-on-glass) method may be used. In the SOG method, resin glass in which polysiloxane or the like is dissolved in a solvent such as acetone or xylene is applied using a spinner or the like, and the solvent is removed by pre-baking at 80 ° C. to 100 ° C.2This is a method of forming a film. SiO by SOG method2The effect similar to the above can be obtained by heat treatment at 1100 to 1200 ° C. after the film is formed. That is, also in the case of the SOG method, the integral intensity ratio of a multi-membered ring of five or more rings determined from the Raman scattering spectrum is substantially 85% or more of the whole, and the integral intensity ratio of a three-membered ring or four-membered ring is substantially equal. By setting it to 15% or less of the total, dislocation is suppressed and leakage current is reduced. The resin glass is described in Japanese Patent Publication No. 58-51422, US Pat. Nos. 3,985,597, 4,004044, and the like. These resin glasses are commercially available, for example, Allied Signal-Accuspin 418/720, Allied Signal-Accuglass T-11 / T-14, Dow-Corning 805, Owens-Illinois650, General Electric SR125 / SR124, etc. may be used. . After prebaking at 80 ° C. to 100 ° C., low temperature annealing at about 600 ° C. may be performed, and then high temperature annealing at 1100 ° C. to 1350 ° C. may be performed.
[0042]
(Second Embodiment)
FIG. 7 (f) is a cross-sectional view showing the structure of an element isolation semiconductor substrate for a bipolar integrated circuit according to the second embodiment of the present invention, and FIGS. 7 (a) to 7 (e) are views of FIG. 7 (f). It is typical sectional drawing which shows the manufacturing method until it reaches a structure. A method for manufacturing an element isolation semiconductor substrate for a bipolar integrated circuit according to the second embodiment of the present invention includes:
(A) First, as shown in FIG. 7 (a), the surface of the p-type silicon substrate 13 is SiO.2A film 14 is formed.
[0043]
(B) Next, this SiO2As shown in FIG. 7B, the film 14 is patterned by using a photolithography method using a photoresist as a mask to expose a part of the surface of the silicon substrate 13 to form a diffusion mask 14. Then, using this diffusion mask 14, Sb (antimony) is thermally diffused to obtain an impurity density of 3 × 10.20cm-3Of n+A buried layer 15 is formed.
[0044]
(C) After the oxide film is removed, as shown in FIG.FourAnd SiH2Cl2PH as a doping gas and silane compounds such asThreeA phosphorus compound such as H2The n layer 16 having a film thickness of 2.5 μm is epitaxially grown on the substrate by decomposition at a high temperature while flowing a carrier gas.
[0045]
(D) Next, an oxide film 17 is formed on the n layer 16 to a thickness of about 0.3 μm, a photoresist pattern is formed on the oxide film 17 by photolithography, and then the oxide film 17 is formed using the photoresist as a mask. A window is opened and an etching mask 17 is formed. Thereafter, the photoresist is removed, and the n-layer 16 is selectively etched using the oxide film 17 as a mask layer to form a groove having a depth of about 3 μm in the n-layer 16 as shown in FIG. Since this selective etching has anisotropy, CClFourOr C2Br2FFourRIE method is used. SF if the groove aspect ratio is large6Low temperature microwave plasma etching with gas plasma is preferred. For example, plasma etching may be performed by cooling the substrate temperature to −80 ° C. to −150 ° C.
[0046]
(E) Further, as in the case of the first embodiment of the present invention, a trench is embedded by CVD using an organic silicon source such as TEOS, TMOS, and TPOS as shown in FIG.
[0047]
(F) Finally, the surface was flattened as shown in FIG.2Heat treatment is performed by holding in an atmosphere for 2 hours. The atmosphere of this heat treatment is N2O other than gas2, HCl, reducing gas, or inert gas. Note that the same effect as described above can be obtained by changing the order, performing heat treatment at 1100 ° C. to 1350 ° C. immediately after CVD, and then performing etch back, that is, planarization. This trench is used as an element isolation region, and n+Collector drawer area 20, p+Base region 21, n+Emitter region 22 is formed to complete the bipolar transistor as shown in FIG. In FIG. 7F, illustration of an emitter metal electrode, a collector metal electrode, an interlayer insulating film, and the like is omitted for the sake of simplicity, but a standard bipolar IC structure is shown. Is naturally provided.
[0048]
FIG. 8 shows the result of investigating the leakage current using the TEG pattern for the element characteristics of the npn bipolar transistor according to the second embodiment of the present invention. p+P between the base region 21 and the n collector region 16+The leakage current of the TEG pattern corresponding to the −n junction is measured and plotted against each heat treatment temperature. The diode area of the TEG pattern is 350 × 240 μm. P in the temperature range of the present invention (1100 ° C. to 1350 ° C.)+-N junction leakage current is 1.7 × 10-8A / cm2It can be seen that the dislocation, which is the cause of leakage current, is suppressed.
[0049]
(Third embodiment)
FIG. 9G is a cross-sectional view of an element isolation semiconductor substrate according to the third embodiment of the present invention, and FIGS. 9A to 9F are schematic diagrams showing a manufacturing method up to FIG. 9G. FIG. In the third embodiment of the present invention, a case where the present invention is applied to a BiCMOS integrated circuit will be described, but it is needless to say that the present invention can also be applied to a MOS integrated circuit, a bipolar integrated circuit, a static induction transistor (SIT) integrated circuit, and the like. A method of manufacturing a semiconductor substrate for a BiCMOS integrated circuit according to the third embodiment of the present invention includes:
(A) First, as shown in FIG. 9A, an n-type silicon substrate (semiconductor) having a first main surface (front surface) and a second main surface (back surface) having a predetermined plane orientation such as (100) plane Substrate) 23 is prepared. The surface of the n-type silicon substrate 23 (first main surface) is formed with a 1 μm-thick SiO 2 film by CVD.2A film 56 is formed. CVD is TEOS, HMDS (Hexamedisiloxane); Si2O (CHThree)6), OMCTS (Octamethylcyclotetrasiloxane); c (OSi (CHThree)2)Four) Or the like may be used.
[0050]
(B) Next, SiO in FIG.2CVD-type n-type silicon substrate 23 is formed at 1100 ° C. to 1200 ° C., N2Hold in an atmosphere for 2 hours and heat-treat. Thereafter, the oxide film is flattened to a thickness of 0.3 μm using a mechanical and chemical polishing (CMP) method or the like while suction-fixing the back surface, and the oxide film 25 for direct bonding (hereinafter referred to as “SDB”). Is formed as shown in FIG.
[0051]
(C) Next, a silicon substrate 26 whose surface is polished to a mirror surface is prepared separately, and the n-type silicon substrate 23 and the silicon substrate 26 are connected to each other through the SDB oxide film 25 as shown in FIG. Bonding and heat treatment at 1100 ° C. for 1 to 2 hours form an SDB substrate. At this time, heat treatment may be performed by applying a voltage. Next, the back surface (second main surface) of the n-type silicon substrate 23 is polished to adjust the thickness so that the thickness of the n-type silicon substrate 23 becomes 1 μm. Note that if the silicon substrate is bonded at 1100 ° C. or higher, substantially the same effect as the heat treatment (b) can be obtained. It is also possible to use heat treatment. It is also possible to perform the heat treatment at the time of bonding to 1200 ° C., or the heat treatment at the time of bonding in two stages of 1100 ° C. and 1200 ° C.
[0052]
(D) Next, the state of FIG. 9C is turned upside down, and the back surface (second main surface) of the n-type silicon substrate 23 is turned up as shown in FIG. 9D. A 300 nm thermal oxide film 17 is formed on the second main surface of the n-type silicon substrate 23 formed by the SDB method, and a part of the thermal oxide film 17 is formed into a predetermined pattern using the photoresist as a mask by photolithography. The photoresist used as an etching mask for the thermal oxide film 17 is removed by etching. Using the thermal oxide film 17 thus obtained as a mask, CClFour, SF69D, a portion of the n-type silicon substrate 23 is etched by a depth of 1 μm until the SDB oxide film 25 is exposed, thereby forming a U-groove 6 as shown in FIG.
[0053]
(E) Next, as shown in FIG. 9 (e), TEOS, TMCTS (1, 3, 5, 7-tetramethylcyclotetrasiloxane; c (OSiHCHThree)FourOr TES (Triethylsilane; SiH (C2HFive)ThreeSiO) using a low pressure CVD method (LPCVD method) using an organic silicon source such as2Film 7 is deposited 1.1-1.5 μm. An ECR plasma CVD method or an ICP-CVD method may be used instead of the LPCVD method. As a material for embedding the U groove 6, an oxidizing agent such as N is added to the organic silicon source.2O, O2, OThreeThe thing which added etc. may be sufficient. Organic silicon source, SiHFourSilicon hydride such as SiClFourThe U-groove 6 can be filled with the silicon oxide film 7 by a CVD method using silicon chloride alone or a mixture of two or more of these raw materials as raw materials. Oxides may be added to the material.
[0054]
(F) Subsequently, CVDSiO is performed by the CDE method or the like.2By etching back the film 7, the surface of the n-type silicon substrate 23 other than the portion buried in the U-groove 6 is exposed to the outside, and is planarized as shown in FIG.
[0055]
(G) The buried oxide film 71 formed by the CVD method using the organic silicon source in the state shown in FIG.2In order to contain a large amount of other impurities such as water, heat treatment is performed at 1100 to 1350 ° C. This heat treatment is for example N2In this case, the atmosphere gas may be about 2 hours.2, HCl, reducing gas, inert gas or CO, CO2But similar results are obtained. After this heat treatment, if a CMOS circuit and a bipolar circuit are formed in the element formation region formed of the n-type silicon substrate 23 surrounded by the buried oxide film 71 using a well-known MOS process and bipolar process, respectively, as shown in FIG. A BiCMOS integrated circuit as shown in FIG. Even if the heat treatment at 1100 ° C. to 1200 ° C. in the step (b) is omitted and the heat treatment at 1100 ° C. to 1350 ° C. in the step (g) is substituted, the object of the present invention can be substantially achieved. In this case, there is an advantage that the process is simplified.
[0056]
As described above, in the case of using an organic silicon source, for example, an insulating material by a CVD method using TEOS as a raw material as the element isolation insulating film, the stress is reduced by performing the heat treatment of the third embodiment of the present invention, It is possible to reduce the occurrence and growth of dislocations during the element isolation region formation or during the subsequent heat treatment in the element manufacturing process. Therefore, according to the third embodiment of the present invention, the value of the leakage current of the pn junction formed in the element formation region is set to 1.7 × 10.-8A / cm2It can be lowered to the following, and high performance of the BiCMOS integrated circuit can be realized.
[0057]
In addition, U groove width l of U groove depth d in the first to third embodiments.1Aspect ratio d / l1Is an example and need not be limited to the aspect ratio described above. As shown in FIG. 10, the aspect ratio d / l1If the oxide film embedded in the U-groove having a thickness of 10 or less is heat-treated under the heat treatment conditions (1100 ° C. to 1350 ° C.) of the present invention, the defect density decreases, so the aspect ratio d / l1May be appropriately selected as long as the value is 10 or less. As shown in FIG. 10, the aspect ratio d / l is outside the range of the heat treatment conditions of the present invention such as 1000 ° C. and 1050 ° C.1It can be seen that the defect density is not reduced even when the value is 10 or less.
[0058]
FIG. 13 shows a separation groove width l in a line and space repeating pattern in a certain direction.1And the width l of the element formation region2Ratio to1/ L2Is the result of investigating the defect density (dislocation pit density) in the element formation region when changing. That is, in the line and space pattern in which the U grooves 6 in the element isolation region are arranged as shown in FIG.1And the width l of the element formation region2The embedded element isolation substrate was manufactured by changing the ratio of the above to 0.003 to 10, and the dislocation pits in the element formation region were selectively etched to be revealed and measured. Fig.11 (a) is XX direction sectional drawing of FIG.11 (b). In this case, FIG. 13 shows a result of comparison in which an oxide film is buried in the U groove by a CVD method using an organic silicon source as a raw material, and heat treatment is performed at 1000, 1050, 1100, 1200, and 1350 ° C. for 2 hours. As shown in FIG.1/ L2However, the number of defects increases at 1.5 or more. Therefore, the present invention provides the width l of the element isolation region.1Is the width l of the element formation region2If it is within this range, it is effective in the above first to third embodiments.1/ L2Any other value may be selected and used. l1/ L2The condition of ≦ 1.5 is defined by a line and space pattern in a certain direction. For example, as shown in FIG. 12, when there is a line-and-space pattern in the XX direction and a line-and-space direction in the Y-Y direction, it is defined in either direction.1x/ L2xOr l1y/ L2yIt is sufficient that at least one of the values is 1.5 or less. The pattern as shown in FIG. 12 is a typical pattern in a MOS / DRAM or the like.
[0059]
(Fourth embodiment)
FIG. 14E is a cross-sectional view of an element isolation semiconductor substrate according to the fourth embodiment of the present invention, and FIGS. 14A to 14D are schematic diagrams showing a manufacturing method up to FIG. 14E. FIG. In the fourth embodiment of the present invention, a case where the present invention is applied to a CMOS integrated circuit will be described. However, the present invention is also applicable to other MOS integrated circuits such as an nMOS (integrated circuit), bipolar integrated circuits, BiCMOS integrated circuits, SIT integrated circuits, and the like. Of course you can. A method for manufacturing a semiconductor substrate for a CMOS integrated circuit according to the fourth embodiment of the present invention includes:
(A) First, as shown in FIG. 14A, an n-type (100) plane silicon substrate 23 having a first main surface (front surface) and a second main surface (back surface) is prepared. A V-groove having a depth of 1.2 to 1.5 μm is formed at a predetermined location on the main surface. The predetermined place means a place that finally becomes an element isolation region. The V-groove is formed by a known method, for example, by forming a thermal oxide film of 150 to 300 nm on the surface (first main surface) of the n-type silicon substrate 23, and by photolithography, a predetermined portion of the thermal oxide film is formed. The n-type silicon substrate 23 may be anisotropically etched using KOH, ethylenediamine pyrocatechol (EDP), or the like using the thermal oxide film as a mask. The V groove is an example, and may be a U groove as in the first to third embodiments of the present invention. CCl for U grooveFour, SiClFour, PClThree, SF6The depth may be 1.2 to 1.5 μm by RIE or ECR ion etching using the like. In either case of U groove or V groove, the width l of the separation groove1And the width l of the element formation region2Ratio of1/ L2Is preferably 1.5 or less. Next, an oxide film having a thickness of about 1.7 to 2 μm is formed by LPCVD using an organic silicon source such as TEOS, DADBS, OMCTS, TMS, and HMD. A thickness of 1.7 to 2 μm refers to the thickness of a flat portion where no groove is formed. Note that coated glass (SOG) may be applied by a spinner or the like instead of the organic silicon CVD method.
[0060]
(B) Next, SiO in FIG.2The CVD-type n-type silicon substrate 23 is 1200 ° C., N2Hold in an atmosphere for 2 hours and heat-treat. Thereafter, the oxide film is flattened to a thickness of 0.3 μm using a CMP method or the like while suction-fixing the back surface (second main surface), and the SDB oxide film 25 is as shown in FIG. To form. At this time, the atmospheric gas is O2, HCl, reducing gas, inert gas or CO, CO2But similar results are obtained.
[0061]
(C) Next, a silicon substrate 26 whose surface is polished to a mirror surface is prepared separately, and the n-type silicon substrate 23 and the silicon substrate 26 are mutually connected via the SDB oxide film 25 as shown in FIG. The SDB substrate is formed by heat treatment at 1100 ° C. to 1150 ° C. for 60 minutes to 2 hours. At this time, heat treatment may be performed by applying a pulse voltage under reduced pressure (vacuum). For example, the pressure may be reduced to 0.1 Pa and a pulse voltage of ± 350 V may be applied at 800 ° C. for about 10 minutes.
[0062]
(D) Next, if the back surface (second main surface) of the n-type silicon substrate 23 is polished so that the thickness of the n-type silicon substrate 23 becomes 1 μm, the oxidation of SDB is performed on the back surface of the n-type silicon substrate 23. A part of the film 25 is exposed. FIG. 14D shows a cross-sectional view of the substrate in this state, and the n-type silicon substrate 23 is positioned on the upper side by reversing the vertical relationship with FIG. 14C. Therefore, by this step, the element formation region 23 surrounded by the buried oxide film 25 is completed on the second main surface of the n-type silicon substrate.
[0063]
(E) Next, a p-well 31 is formed inside the element formation region 23 using a well-known MOS process as shown in FIG.+The source / drain regions 32 and 33 and the element formation region 23 are formed with a p-type portion where p-well is not formed.+If the source / drain regions 34 and 35 are formed, and further the gate oxide film, polysilicon gate electrodes 98 and 98, and metal wiring are formed on the surface thereof, the CMOS integrated circuit according to the fourth embodiment of the present invention is completed. To do.
[0064]
In the fourth embodiment of the present invention, the SDB oxide film and the buried oxide film can be simultaneously formed by one organic silicon-based CVD method (or application of SOG), and the first embodiment shown in FIGS. Compared with the third embodiment, the number of processes is reduced, and the productivity is increased accordingly. In addition, since the number of heat treatment steps is reduced as compared with the third embodiment, a semiconductor device can be manufactured with less heat history, and crystal defects can be reduced and a fine structure can be easily realized.
[0065]
In addition, the organic silicon-based CVD method has excellent step coverage and can form a thick oxide film at a lower temperature and in a shorter time than the formation of an SDB oxide film by thermal oxidation. (OSF) does not occur. Accordingly, there are few crystal defects in the element formation region, and as a result, leakage current in the CMOS circuit is reduced. In addition, since the step coverage is excellent, not only the case shown in FIG. 14A, but also a substrate having various uneven shapes is used to create an SOI substrate without being affected by the flatness. be able to.
[0066]
As described above, the U-groove may be used in the fourth embodiment of the present invention, but it is a matter of course that the aspect ratio in that case is preferably 10 or less. In the case of V-groove, the depth dvAnd the opening width l on the surface side of the V-groovev 1Ratio dv/ Lv 1Is preferably 10 or less.
[0067]
As described above, in the CMOS integrated circuit, when the insulating material by CVD using an organic silicon source such as TEOS as a material is used as the element isolation insulating film, the stress is obtained by performing the heat treatment according to the fourth embodiment of the present invention. Thus, the generation and growth of dislocations during the formation of the element isolation region or during the heat treatment in the subsequent element manufacturing process can be reduced. Therefore, according to the fourth embodiment of the present invention, the value of the leakage current of the pn junction formed in the element formation region is set to 1.7 × 10.-8A / cm2It can be reduced to the following, and high performance of CMOS / LSI can be realized.
[0068]
In the first to fourth embodiments of the present invention, a silicon oxide film (SiO 2) is formed by atmospheric pressure CVD or LPCVD.2In the case where the film is deposited, SiO2This CVD can also be performed by a liquid phase CVD method. In this case O2A silicon oxide film may be deposited by causing the gas to undergo microwave discharge and reacting with TMS to bring the substrate temperature to −40 ° C. below the boiling point of the deposited particles. If heat treatment is performed in the same manner as in the first to fourth embodiments of the present invention after liquid phase CVD, the same effect as in the above embodiment can be obtained. Further, ethylene glycol, N-methylacetamide as a solvent and a small amount of potassium nitrate as an electrolytic solution are added, and an anodic oxidation using a silicon substrate as an anode and platinum as a counter electrode causes SiO into the U groove.2A film may be formed. In this case as well, the same effect can be obtained by performing heat treatment at 1100 ° C. to 1350 ° C. as in the above embodiments. Also, SiO by plasma CVD method2It is also possible to fill the U-groove with a film.
[0069]
【The invention's effect】
As described above in detail, in an MOS integrated circuit, a bipolar integrated circuit, a BiCMOS integrated circuit, or a SIT integrated circuit on a silicon semiconductor substrate, an organic silicon source, for example, an insulating material by a CVD method using TEOS as a raw material is used as an element isolation insulating film. In some cases, the heat treatment of the present invention can reduce the stress, and can reduce the occurrence and growth of dislocations during the formation of the element isolation region or during the subsequent heat treatment in the element manufacturing process. Therefore, according to the present invention, the value of the leakage current of the pn junction formed in the element formation region is set to 1.7 × 10.-8A / cm2The following can be achieved, and high performance of integrated circuits such as MOS LSI and bipolar LSI can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram showing manufacturing steps of a buried element isolation semiconductor substrate for a MOS integrated circuit according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a relationship between a heat treatment temperature of a buried oxide film and a density of crystal defects generated in an element formation region.
FIG. 3 is a diagram showing a relationship between a heat treatment temperature of a buried oxide film and a leakage current of a pn junction formed in an element formation region.
FIG. 4 is a Raman scattering spectrum diagram by an oxide film with and without heat treatment (annealing 1 and annealing 2).
FIG. 5 is a graph showing the dependency of the integrated intensity ratio of each peak of Raman scattering on the heat treatment temperature of an oxide film.
FIG. 6 is a diagram showing a change in etching rate due to heat treatment.
FIG. 7 is a diagram showing a manufacturing process of a buried element isolation semiconductor substrate for a bipolar integrated circuit according to a second embodiment of the present invention.
FIG. 8 is a diagram showing a relationship between a heat treatment temperature of a buried oxide film and a leakage current of a pn junction formed in an element formation region.
FIG. 9 is a diagram showing manufacturing steps of a buried element isolation semiconductor substrate for a BiCMOS integrated circuit according to a third embodiment of the present invention.
FIG. 10 is a diagram illustrating a relationship between an aspect ratio of a groove and a defect density.
FIG. 11 is a diagram showing the relationship between the width of a trench and the width of an element formation layer.
FIG. 12 is a plan view showing a case where a line and space pattern exists in two directions.
FIG. 13 shows l shown in FIG. 11 (or FIG. 12).1/ L2It is a figure which shows the relationship between and defect density.
FIG. 14 is a diagram showing a manufacturing process of the embedded element isolation semiconductor substrate for the CMOS integrated circuit according to the fourth embodiment of the present invention.
FIG. 15 is a diagram showing a structure of an element isolation semiconductor substrate by a typical LOCOS method as a conventional technique.
FIG. 16 is a diagram showing the occurrence of dislocations in the conventional buried element isolation technique.
[Explanation of symbols]
5,13 p-type silicon substrate
6 U groove
7,71,77 buried oxide film
8 Gate oxide film
12 dislocation
14, 17 Oxide film
15 n+Embedded area
16 n epitaxial growth layer
20 n+Collector electrode extraction area
21 p base region
22 n+Emitter area
23,81 Silicon substrate
24, 25 SDB oxide film
26 n-type silicon substrate
78, 79 interlayer insulation film
82 Oxide film
83 Element formation region
88 Nitride film
91 n+Source area
92 n+Drain region
93 Source electrode
94 Drain electrode
98,99 polysilicon gate electrode

Claims (12)

  1. A plurality of grooves forming a shallow trench formed in a part of the surface of the semiconductor substrate;
    An oxide film formed inside the groove, formed by an organic silicon-based CVD method, heat-treated at a temperature of 1100 ° C. to 1350 ° C. after being deposited by the organic silicon-based CVD method, and moisture is dissociated inside the groove A buried oxide film comprising:
    A shallow trench isolation semiconductor substrate comprising: an element formation region formed between the groove portions and having a dislocation density of 1 / μm 2 or less by the heat treatment .
  2. 2. The shallow trench according to claim 1, wherein an aspect ratio d / l 1 defined by a ratio of a depth d of the groove and a dimension of a width l 1 of the opening of the groove is 10 or less. Isolated semiconductor substrate.
  3. In a line-and-space repeating pattern in a predetermined direction in which the width l 1 of the opening of the groove is the minimum space width and the width l 2 of the element formation region is the minimum line width, the pattern is defined in the predetermined direction. shallow trench isolation semiconductor substrate according to claim 1, wherein the l 1 and the ratio l 1 / l 2 and l 2 is 1.5 or less that.
  4.    2. The shallow trench isolation semiconductor substrate according to claim 1, wherein the buried oxide film is an amorphous silicon oxide film including a ring structure having a 5-membered ring or more and a ring structure having a 4-membered ring or less.
  5.    2. The shallow trench isolation semiconductor substrate according to claim 1, wherein an etching rate of the buried oxide film with an ammonium fluoride solution is 130 nm / min or less.
  6. The manufacturing method of the shallow trench isolation semiconductor substrate characterized by including the following processes at least.
    (A) a first step of forming a plurality of grooves forming shallow trenches on a part of the surface of the semiconductor substrate; (b) a second step of burying an oxide film in the grooves by an organic silicon CVD method; After the step, the oxide film is heat-treated at a substrate temperature of 1100 ° C. to 1350 ° C. to dissociate moisture in the oxide film inside the groove.
  7.   7. The shallow according to claim 6, wherein the organic silicon-based CVD method in the second step is any one of an atmospheric pressure CVD method, a low pressure CVD method, a plasma CVD method, a photo CVD method, and a liquid phase CVD method. A method for manufacturing a trench isolation semiconductor substrate.
  8. The heat treatment in the third step is any one of reducing gas such as H 2 , inert gas such as He, Ne, Ar, Kr, and Xe, O 2 , N 2 , HCl, CO, and CO 2 , or these 7. The method of manufacturing a shallow trench isolation semiconductor substrate according to claim 6, wherein the method is performed in a mixed gas composed of two or more kinds of gases selected from the above.
  9. The second step is characterized in that an oxide film is deposited thicker than the groove, and then the surface of the semiconductor substrate is planarized until the surface of the semiconductor substrate is exposed, and the oxide film is embedded in the groove. A method for manufacturing a shallow trench isolation semiconductor substrate according to claim 6.
  10.   7. The second step is a step of depositing an oxide film thicker than the groove, and further includes a fourth step of planarizing the surface of the semiconductor substrate after the third step. The manufacturing method of the shallow trench isolation semiconductor substrate of description.
  11. The shallow ratio according to claim 6, wherein an aspect ratio d / l 1 defined by a ratio of a depth d of the groove and a dimension of a groove width l 1 of the opening of the groove is 10 or less. A method for manufacturing a trench isolation semiconductor substrate.
  12. The width l 1 of the groove and the minimum space width, the repetitive pattern of predetermined direction of the line-and-space width l 2 and the minimum line width of the element forming region, l 1 defined by the predetermined direction 7. The method of manufacturing a shallow trench isolation semiconductor substrate according to claim 6, wherein the ratio l 1 / l 2 of the first and second layers is 1.5 or less.
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