JP2001037207A - Gate drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gate drive circuit which is hardly affected by influence of noise and has high reliability of the operation. SOLUTION: When a specified on-gate signal VGG is applied to a gate G of a voltage type switching element IGBT, application is so controlled that two-stepwise shifting in time is performed by using first delay drive circuits CRCA, TRA and TRAA. When a specified off-gate signal VGG is applied to the gate of the switching element IGBT, application is so controlled that two- stepwise shifting in time is performed by using second delay drive circuits CRCB, TRB and TRBB. As a result, a stable on-gate voltage and a stable off-gate voltage are applied to the gate G of the switching element IGBT, the descending time of a voltage between a collector C and an emitter E of the switching element and Hall time are shortened, and switching loss is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a gate drive circuit for a voltage-driven switching element.

[0002]

2. Description of the Related Art Generally, a three-phase output PW using a voltage-driven switching element such as an IGBT or IEGT, for example,
The M inverter device has a circuit configuration shown in FIG. In this PWM inverter device, Vd is a DC power source, F
C is a DC smoothing capacitor, QU, QV, QW, QX, Q
Y and QZ are voltage-driven switching elements, GCU and GC
V, GCW, GCX, GCY, and GCZ are gate drive circuits that drive each of these elements. CONT is a speed control circuit of the inverter device, and each speed control circuit CONT-U, CONT-V, CON of each of the three phases of UVW.
It is constituted by T-W.

[0003] Then, PW by the speed control circuit CONT is used.
The control operation of the M inverter device is as follows (hereinafter, the U-phase control circuit CONT-U will be described,
The same applies to the V and W phases.) First, the speed command value Vref is compared with the speed detection value Vo to output a deviation er. This deviation er is multiplied by the output unit sine wave Esin of the sine wave circuit VSIN that outputs the deviation er in proportion to the speed Vo, and the calculation result Iref and the current feedback signal I
o is compared with a comparator S1. The output of the comparator S1 is output as a voltage command value Eref via the amplifier AM1 to the comparator S2.
And compared with the output Etr of the triangular wave generator VTR by the comparator S2. The output of the comparator S2 is a waveform shaping circuit S
The signals are converted into signals of 1 and 0 by the HA, input to the U-phase gate drive circuit GCU, and simultaneously input to another gate drive circuit GCX via the inverter MA. The U-phase voltage-type switching elements QU and QX are alternately turned on / off, and the output is supplied to the motor M as a U-phase current IU. The V and W phases are similarly controlled. As a result,
The sine wave currents IU, IV, IW are supplied to the electric motor M, and the speed is controlled.

The gate drive circuits GCU, GCV, GCW, and GC in the PWM inverter device having such a configuration.
Each of X, GCY, and GCZ has the configuration shown in FIG.
FIG. 11 shows a gate drive circuit for an IGBT which is a voltage source switching element. In this gate drive circuit, POW is a high-frequency power supply, POC is a power supply circuit for converting AC of the high-frequency power supply POW to DC, PGR is a logic control circuit, and PDR is a drive circuit. PR is a gate resistance circuit, which is composed of resistors RA and RB. PHC is an input circuit for inputting the gate control signal VI to the logic control circuit PGR.

This gate drive circuit operates according to the sequence shown in FIG. That is, the input circuit PHC outputs the gate control signal VI to the logic control circuit PGR in response to the input signal GU (this is a signal for the U-phase switching element QU, but the operation is the same for other switching elements). I do. The logic control circuit PGR outputs control signals VGA, VGB to the transistors TRA, TRB of the drive circuit PDR, respectively, based on the input signal VI.

Therefore, while the input signal GU and VI are 1, VGA is also 1 so that the transistor T
RA conducts, applying a positive voltage + V to the gate G of the switching element IGBT via the gate resistor RA to turn on the element.

During a period in which input signal GU and VI are 0, transistor TRB of drive circuit PDR conducts and switching element IGBT passes through gate resistance RB.
A negative voltage -V is applied to the gate G of the device to turn off the device.

[0008]

However, such a conventional gate drive circuit has the following problems. As the voltage-driven switching element has a large capacity and a high withstand voltage, the floating capacitance Cc between the terminals shown in FIG.
g, Cge, and Cce increase. As a result, when other elements switch from off to on like the elements GU and GX of both arms of the U-phase shown in FIG. 14, an erroneous pulse of 0 V or more is input to the off-gate voltages Vgu and Vgx via the floating capacitance. In the worst case, the element that was turned off by this erroneous pulse turns on again, causing a short-circuit mode,
There is a problem that the element may be destroyed. In particular, FIG.
In the PWM inverter device as shown in FIG. 0, the influence between the elements of the upper and lower arms appears, and it is most severe in a small current region. In addition, since the gate drive circuit is installed near the element, it is used in an environment that is easily affected by electromagnetic noise and induction noise.

The present invention has been made in view of such a conventional problem, and has as its object to provide a gate drive circuit which is hardly affected by noise and has high operation reliability.

[0010]

According to a first aspect of the present invention, there is provided a gate drive circuit which applies an ON signal of a predetermined first voltage to a gate of a switching element and conducts the signal for a predetermined period, and applies a predetermined second voltage to the gate. What is claimed is: 1. A circuit for applying a voltage off signal to render a non-conductive state for a predetermined period, comprising delay drive means for applying the predetermined first voltage applied to the gate in two steps with time. It is.

In the gate drive circuit according to the first aspect of the present invention, control for applying a predetermined first voltage on signal to the gate of the switching element by applying a time-shifted two-stage control using a delay drive circuit is performed. . Thus, a stable on-gate voltage is applied to the gate of the switching element, the fall time of the voltage between the collector and the emitter of the switching element is reduced, and the on-loss at the time of switching is reduced.

According to a second aspect of the present invention, in the gate drive circuit, an ON signal of a predetermined first voltage is applied to the gate of the switching element to conduct for a predetermined period, and a predetermined second voltage is applied to the gate.
A circuit for applying a voltage off signal to render a non-conductive state for a predetermined period, comprising delay drive means for applying the predetermined second voltage applied to the gate in two steps with a time lag. It is.

In the gate drive circuit according to the second aspect of the present invention, the control of applying a predetermined second voltage off signal to the gate of the switching element by applying a time-shifted two-stage control using a delay drive circuit is performed. . Thus, a stable off-gate voltage is applied to the gate of the switching element, the hole time of the voltage between the collector and the emitter of the switching element is reduced, and the off-loss at the time of switching is reduced.

According to a third aspect of the present invention, in the gate drive circuit, an ON signal of a predetermined first voltage is applied to a gate of the switching element to conduct for a predetermined period, and a predetermined second voltage is applied to the gate.
A first delay drive means for applying a voltage off signal to render the circuit non-conductive for a predetermined period of time, wherein the first delay drive means applies the predetermined first voltage applied to the gate in a time-shifted two-stage manner; And second delay drive means for applying the predetermined second voltage applied to the gate while shifting the time in two stages.

In the gate drive circuit according to a third aspect of the present invention, an ON signal of a predetermined first voltage is applied to the gate of the switching element by a first delay drive circuit by shifting the signal in two steps in time. Control is performed, and a control is performed in which a second delay drive circuit applies the off-signal of a predetermined second voltage to the gate of the switching element at two steps in time.

Thus, a stable on-gate voltage and a stable off-gate voltage are applied to the gate of the switching element, and the fall time and the hole time of the voltage between the collector and the emitter of the switching element are shortened, and the switching loss is reduced.

According to a fourth aspect of the present invention, in the gate drive circuit, an ON signal of a predetermined first voltage is applied to a gate of the switching element to conduct for a predetermined period, and a predetermined second voltage is applied to the gate.
A delay drive means for applying a predetermined voltage to the gate in a time-shifted manner in two stages, wherein the delay drive means applies a voltage-off signal to render the circuit non-conductive for a predetermined period; A capacitor inserted between the positive side of the signal line and the emitter of the switching element.

In the gate drive circuit according to the fourth aspect of the present invention, control for applying a predetermined first voltage ON signal to the gate of the switching element by applying a time-shifted two-stage control using a delay drive circuit is performed. . Then, the second-stage on-gate voltage is applied to the gate while the first-stage on-gate voltage is applied to both the gate and the emitter by the capacitor.

Thus, a more stable on-gate voltage is applied to the gate of the switching element, the fall time of the voltage between the collector and the emitter of the switching element is reduced, and the on-loss at the time of switching is reduced. The capacitor has low impedance and effectively absorbs noise to make it less susceptible to noise.

According to a fifth aspect of the present invention, in the gate drive circuit, an ON signal of a predetermined first voltage is applied to a gate of the switching element to conduct for a predetermined period, and a predetermined second voltage is applied to the gate.
A delay drive means for applying a predetermined voltage to the gate by applying a predetermined second voltage to the gate in a time-shifted manner in two stages; A capacitor is provided between the negative side of the signal line and the emitter of the switching element.

In the gate drive circuit according to the fifth aspect of the present invention, the control of applying a predetermined second voltage off signal to the gate of the switching element by applying a time-shifted two-stage control by a delay drive circuit is performed. . Then, the second-stage off-gate voltage is applied to the gate while the first-stage off-gate voltage is applied to both the gate and the emitter by the capacitor.

Thus, a stable off-gate voltage is applied to the gate of the switching element, the hole time of the voltage between the collector and the emitter of the switching element is shortened, and the off-loss at the time of switching is reduced. Effectively absorbs noise with low impedance, making it less susceptible to noise.

According to a sixth aspect of the present invention, in the gate drive circuit, an ON signal of a predetermined first voltage is applied to a gate of the switching element to conduct for a predetermined period, and a predetermined second voltage is applied to the gate.
A first delay drive means for applying a voltage off signal to render the circuit non-conductive for a predetermined period of time, wherein the first delay drive means applies the predetermined first voltage applied to the gate in a time-shifted two-stage manner; A delay drive means for applying the predetermined second voltage applied to the gate in a time-shifted manner in two stages; and a first drive means inserted between the positive side of the gate control signal line and the emitter of the switching element. And a second capacitor inserted between the negative side of the gate control signal line and the emitter of the switching element.

In the gate drive circuit according to the present invention, when the ON signal of the predetermined first voltage is applied to the gate of the switching element, the ON signal is temporally shifted by two stages by the first delay drive circuit. Control is performed, and the second-stage on-gate voltage is applied to the gate while the first-stage on-gate voltage is applied to both the emitter and the gate by the first capacitor. In order to apply an off signal of a predetermined second voltage to the gate of the switching element, control is performed such that the signal is applied in a time-shifted two-stage manner by a second delay drive circuit, and the first signal is applied by a second capacitor. The second-stage off-gate voltage is applied to the gate while the off-gate voltage at the stage is applied to the emitter together with the gate.

Thus, a more stable on-gate voltage and a more off-gate voltage are applied to the gate of the switching element, and the first and second capacitors effectively absorb noise with low impedance and reduce the influence of noise. Hard to receive.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows the configuration of the first embodiment of the gate drive circuit of the present invention.

The gate drive circuit shown in FIG. 1 corresponds to one of the voltage-type switching elements IGBT of each phase of the UVW in the general PWM inverter shown in FIG. Therefore, in the PWM inverter device shown in FIG.
Gate drive circuits GCU, GCV, GCW, GCX, GCY, GC for X, QV, QY, QW, QZ, respectively
The gate drive circuit shown in FIG. Inputs PV, IV, AG, and VI in the gate drive circuit shown in FIG. 1 are input from a power supply circuit POC and an input circuit PHC similar to those in the conventional example shown in FIG.

In the gate drive circuit shown in FIG.
GR is a logic control circuit similar to the conventional one, PDRA is a drive circuit which characterizes the first embodiment, and RA and RB are gate resistors.

The drive circuit PDRA alternately turns on / off.
A pair of off-controlled transistors TRA and TRB are provided, and a second drive transistor TRAA is provided in parallel with the transistor TRA. The delay circuit DRCA is connected to the second drive transistor TRAA.

This gate drive circuit operates according to the sequence shown in FIG.

<On-gate output> Gate control input signal V
I is input to the logic control circuit PGR as in the conventional example shown in FIGS. The logic control circuit PGR uses the input signal VI to turn on / off the 0 and 1 phases that are opposite to each other.
The off control signals VGA and VGB are applied to the drive circuit P respectively.
Output to the transistors TRA and TRB of the DRA. The control signal VGA is also input to the delay circuit DRCA. The delay circuit DRCA converts the signal VGA into a signal VGAA whose rising timing is delayed by Δt1, and outputs the signal VGA to the second drive transistor TRAA.

Thus, the period t1 when the input signal VI is 1
During the period from t1 to t3, the VGA also becomes 1, whereby the transistor TRA conducts, and the on-gate voltage Vtra is applied to the gate G of the switching element IGBT via the gate resistor RA during the period t1 to t3. After a delay of Δt1, periods t2 to t
During the period 3, the on-gate voltage Vtraa is applied to the gate of the device IGBT. As a result, an on-gate voltage VGG is applied between the gate G and the emitter E of the switching element IGBT.

<Off-gate output> During the period t3 to t4 when the input signal VI is 0, the control signal VGA output from the control circuit PRG becomes 0 and the drive transistors TRA, TR
AA turns off, and conversely, the control signal VGB becomes 1 and the drive transistor TRB turns on. As a result, a negative voltage of -V is applied to the voltage VGG between the gate G and the emitter E, and the switching element IGBT is turned off.

As described above, in the gate drive circuit according to the first embodiment, in the on-gate operation, after applying the first-stage on-gate voltage from the transistor TRA, Δt
By applying the second-stage on-gate voltage from the second drive transistor TRAA after the delay of 1, a stable on-gate voltage can be supplied. Also, dV / dt
(Time change rate of voltage) can be reduced to reduce the level of pulse noise induced at the gate of the switching element on the opposite side, thereby preventing malfunction. Further, the fall time tr of the voltage between the collector C and the emitter E of the switching element IGBT is shortened, and the on-loss Eon of the switching is reduced.

Next, a second embodiment of the gate drive circuit of the present invention will be described with reference to FIG. The gate drive circuit according to the second embodiment differs from the first embodiment shown in FIG. 1 in that a capacitor CHA is further provided between the positive side PV of the DC power supply and the emitter E of the switching element IGBT. It is characterized. Therefore, other configurations are the same as those of the first embodiment shown in FIG.

In the gate drive circuit according to the second embodiment,
In the on-gate output operation according to the above-described first embodiment, a more stable gate voltage VGG can be applied particularly when the second drive transistor TRAA outputs the second-stage on-gate voltage Vraa. In addition, since the capacitor CHA has low impedance, noise can be effectively absorbed, and the effect of the noise can be reduced.

Next, a third embodiment of the gate drive circuit of the present invention will be described with reference to FIG. The third shown in FIG.
As in the first embodiment shown in FIG. 1, the gate drive circuit according to the embodiment of the present invention corresponds to the one for the voltage type switching element IGBT of one phase of each UVW phase in the PWM inverter device generally shown in FIG. Is shown. Therefore, in the PWM inverter device shown in FIG. 10, the voltage-type switching elements QU, QX, QV, QY, QW,
Gate drive circuits GCU, GCV,
The gate drive circuit shown in FIG. 4 is applied to each of GCW, GCX, GCY, and GCZ. Further, inputs PV, IV, AG, V in the gate drive circuit shown in FIG.
I is input from a power supply circuit POC and an input circuit PHC similar to the conventional example shown in FIG.

In the gate drive circuit shown in FIG.
GR is a logic control circuit similar to the conventional one, PDRB is a drive circuit which characterizes the third embodiment, and RA and RB are gate resistors.

The drive circuit PDRB is turned on / off alternately.
A pair of off-controlled transistors TRA and TRB are provided, and a second drive transistor TRBB is provided in parallel with the transistor TRB. The delay circuit DRCB is connected to the second drive transistor TRBB.

This gate drive circuit operates according to the sequence shown in FIG.

<On-Gate Output> The logic control circuit PGR outputs on / off control signals VGA and VGB in which 0 and 1 are in opposite phases to the transistors TRA and TRB of the drive circuit PDRB in response to the input signal VI. During the period t1 to t2 when the input signal VI is 1, the control circuit PRG
The control signal VGA outputted by the control signal becomes 1 and the drive transistor TRA is turned on. Conversely, the control signal VGB becomes 0 and the drive transistors TRB and TRBB are turned off.
As a result, the voltage VGG between the gate G and the emitter E is increased by +
V gate voltage is applied and the switching element IGBT
Turn on.

<Off-gate output> The logic control circuit PGR controls the control signal VG during the period t2 to t4 when the input signal VI is 0.
A is set to 0 and the control signal VGB is set to 1 for output. When the control signal VGA is 0, the drive transistor TRA is turned off.

On the other hand, the control signal VGB is 1, and the drive transistor TRB is turned on during the period t2 to t4. The control signal VGB is also input to the delay circuit DRCB. The signal VGB of the delay circuit DRCB is converted to a signal VGBB whose fall timing is delayed by Δt2, and is output to the second drive transistor TRBB.

As a result, the transistor TRB is turned on during the period t2 to t4, and the off-gate voltage Vtrb is applied to the gate G of the switching element IGBT via the gate resistor RB.
After the delay of Δt2 from the second drive transistor TRBB, the off-gate voltage Vtrbb is directly applied to the gate of the element IGBT without going through the gate resistance during the period t3 to t4. As a result, an off-gate voltage VGG is applied between the gate G and the emitter E of the switching element IGBT.

As described above, in the gate drive circuit according to the third embodiment, in the off-gate operation, after applying the first-stage off-gate voltage from the transistor TRB, Δt
By applying the second-stage off-gate voltage directly from the second drive transistor TRBB without passing through the gate resistor after the delay of 2, a stable off-gate voltage can be supplied, and pulse noise due to the gate-on of the switching element on the opposite side can be supplied. Can be prevented from being induced. Further, the Hall time tf of the voltage between the collector C and the emitter E of the switching element IGBT is reduced, and the switching off loss Eoff is reduced.

Next, a fourth embodiment of the gate drive circuit of the present invention will be described with reference to FIG. The gate drive circuit of the fourth embodiment differs from the third embodiment shown in FIG. 4 in that a capacitor CHB is further provided between the negative side NV of the DC power supply and the emitter E of the switching element IGBT. It is characterized. Therefore, the other configuration is common to the third embodiment shown in FIG.

In the gate drive circuit according to the fourth embodiment,
In the off-gate output operation according to the above-described third embodiment, a more stable gate voltage VGG can be applied particularly when the second drive transistor TRBB outputs the second-stage off-gate voltage Vrbb. In addition, since the capacitor CHB has low impedance, noise can be effectively absorbed and the influence of noise can be reduced.

Next, a fifth embodiment of the gate drive circuit of the present invention will be described with reference to FIG. The gate drive circuit of the fifth embodiment is characterized by a configuration in which the first embodiment shown in FIG. 1 and the third embodiment shown in FIG. 4 are combined. That is, a first delay circuit DR that delays the rising timing of control signal VGA from logic control circuit PRG by Δt1 and outputs it as control signal VGAA with respect to the conventional gate drive circuit shown in FIG.
CA, a second delay circuit DRCB for delaying the fall timing of the control signal VGB by Δt2 and outputting the control signal as a control signal VGBB is provided.
With the pair of drive transistors TRA and TRB, the second
Drive transistors TRAA and TRBB are provided.

As a result, the gate drive circuit according to the fifth embodiment operates according to the sequence shown in FIG.

<On-gate output> As in the first embodiment, the control circuit PGR sets the control signal VGA to 1 during the period t1 to t3 when the input signal VI is 1, and sets the transistor TRA of the drive circuit PDRC to TRA. Turn on. The control signal VGA is also input to the first delay circuit DRCA, where the rising timing is converted to a signal VGAA delayed by Δt1, and the second drive transistor TRAA
, And this is turned on for the period from t2 to t3.

Thus, the period t1 when the input signal VI is 1
During the period from t2 to t3, the on-gate voltage Vtra is applied to the gate G of the switching element IGBT, and after a delay of Δt1 from the second drive transistor TRAA, the period t2
During t3, the on-gate voltage Vtraa is applied to the gate of the device IGBT. As a result, the switching element IGBT
An on-gate voltage VGG is applied between the gate G and the emitter E.

<Off-gate output> As in the third embodiment, the control circuit PGR sets the control signal VGA to 0 during the period t3 to t5 when the input signal VI is 0, and sets the transistor TRB of the drive circuit PDRC. Turn on. The control signal VGB is also input to the second delay circuit DRCB, where the fall signal is converted to a signal VGBB with a fall timing delayed by Δt2 to generate a second drive transistor TRBB.
, And this is turned on for a period from t4 to t5.

Thus, the period t3 when the input signal VI is 0
During the period from t4 to t5, the off-gate voltage Vtrb is applied to the gate G of the switching element IGBT, and after a delay of Δt2 from the second drive transistor TRBB, the period t4 to
During t5, the off-gate voltage Vtrbb is applied to the gate of the device IGBT. As a result, the switching element IGBT
An off-gate voltage VGG is applied between the gate G and the emitter E.

As described above, the gate drive circuit of the fifth embodiment combines the functions and effects of the first embodiment and the third embodiment. After applying the first-stage on-gate voltage and then applying the second-stage on-gate voltage from the second drive transistor TRAA after a delay of Δt1, a stable on-gate voltage can be supplied. Further, it is possible to reduce dV / dt (rate of time change of voltage) to reduce the level of pulse noise induced at the gate of the switching element on the opposite side, thereby preventing malfunction. Further, the fall time tr of the voltage between the collector C and the emitter E of the switching element IGBT is shortened, and the on-loss Eon of switching is reduced.

In the off-gate operation, after the first-stage off-gate voltage is applied from the transistor TRB, ΔΔ
By applying the second-stage off-gate voltage directly from the second drive transistor TRBB without passing through the gate resistor after the delay of t2, a stable off-gate voltage can be supplied, and pulse noise due to the gate-on of the switching element on the opposite side can be supplied. Can be prevented from being induced. Further, the Hall time tf of the voltage between the collector C and the emitter E of the switching element IGBT is reduced, and the switching off loss Eoff is reduced.

Next, a sixth embodiment of the gate drive circuit of the present invention will be described with reference to FIG. The gate drive circuit according to the sixth embodiment has a configuration in which the second embodiment shown in FIG. 3 and the fourth embodiment shown in FIG. 6 are combined. That is, as compared with the fifth embodiment shown in FIG. 7, a capacitor CHA is further provided between the positive side PV of the DC power supply and the emitter E of the switching element IGBT, and the negative side NV of the DC power supply is connected. Switching element IGB
It is characterized in that a capacitor CHB is disposed between the emitter E of T and the emitter E of T. Other configurations are common to the fifth embodiment shown in FIG.

Thus, in the gate drive circuit according to the sixth embodiment, in addition to the functions and effects of the fifth embodiment, as in the second embodiment with respect to the first embodiment, As in the fourth embodiment with respect to the third embodiment, since the capacitors CHA and CHB have low impedance, noise can be effectively absorbed and the influence of noise can be reduced.

In each of the above embodiments, the IGBT is exemplified as the voltage source switching element. However, the present invention is not limited to this. For example, it is effective to apply the invention to the IEGT.

[0059]

As described above, according to the first aspect of the present invention,
A stable on-gate voltage can be applied to the gate of the switching element, the fall time of the voltage between the collector and the emitter of the switching element can be reduced, and the on-loss at the time of switching can be reduced.

According to the second aspect of the present invention, a stable off-gate voltage can be applied to the gate of the switching element, the hole time of the voltage between the collector and the emitter of the switching element can be shortened, and the off-state during switching can be reduced. Loss can be reduced.

According to the third aspect of the present invention, a stable on-gate voltage and a stable off-gate voltage are applied to the gate of the switching element, the fall time of the voltage between the collector and the emitter of the switching element and the hole time are shortened, Loss can be reduced.

According to the fourth aspect of the present invention, a more stable on-gate voltage can be applied to the gate of the switching element, and the fall time of the voltage between the collector and the emitter of the switching element can be shortened. Can be reduced, and in addition, the capacitor can effectively absorb noise with low impedance and be less affected by the noise.

According to the fifth aspect of the present invention, a stable off-gate voltage can be applied to the gate of the switching element, the hole time of the voltage between the collector and the emitter of the switching element can be shortened, and the off-state during switching can be reduced. Loss can be reduced, and in addition, the capacitor can effectively absorb noise with low impedance and be less affected by noise.

According to the invention of claim 6, more stable on-gate voltage and off-gate voltage are applied to the gate of the switching element, and the fall time and the hole time of the voltage between the collector and the emitter of the switching element are shortened. In addition, the switching loss can be reduced, and in addition, the first and second capacitors can effectively absorb noise with low impedance and be less affected by the noise.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram according to a first embodiment of the present invention.

FIG. 2 is an operation sequence diagram of the first embodiment.

FIG. 3 is a circuit block diagram according to a second embodiment of the present invention.

FIG. 4 is a circuit block diagram according to a third embodiment of the present invention.

FIG. 5 is an operation sequence diagram of the third embodiment.

FIG. 6 is a circuit block diagram according to a fourth embodiment of the present invention.

FIG. 7 is a circuit block diagram according to a fifth embodiment of the present invention.

FIG. 8 is an operation sequence diagram of the fifth embodiment.

FIG. 9 is a circuit block diagram according to a sixth embodiment of the present invention.

FIG. 10 is a circuit block diagram of a general PWM inverter device.

FIG. 11 is a block diagram of a conventional gate drive circuit.

FIG. 12 is an operation sequence diagram of a conventional gate drive circuit.

FIG. 13 is an explanatory diagram showing a distribution of stray capacitance of a switching element in a conventional example.

FIG. 14 is an operation sequence diagram showing the principle of a malfunction according to a conventional example.

[Explanation of symbols]

 PV power supply (positive) NV power supply (negative) AG neutral point potential VI Input signal PGR control circuit DRCA, DRCB delay circuit PDRA, PDRB, PDRC drive circuit TRA, TRB transistor TRAA, TRBB second drive transistor RA, RB gate resistance IGBT Switching element CHA, CHB Capacitor

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference)

Claims (6)

[Claims] A first predetermined voltage is applied to a gate of a switching element.
A gate drive circuit that applies an ON signal of voltage to conduct for a predetermined period, and applies an OFF signal of a predetermined second voltage to the gate to turn off only for a predetermined period; The predetermined first voltage is temporally
A gate drive circuit comprising delay drive means for applying a voltage in a stepwise manner. 2. The method according to claim 1, wherein a predetermined first voltage is applied to the gate of the switching element.
A gate drive circuit that applies an ON signal of voltage to conduct for a predetermined period, and applies an OFF signal of a predetermined second voltage to the gate to turn off only for a predetermined period; The predetermined second voltage is temporally
A gate drive circuit comprising delay drive means for applying a voltage in a stepwise manner. 3. The method according to claim 1, wherein a predetermined first voltage is applied to the gate of the switching element.
A gate drive circuit that applies an ON signal of voltage to conduct for a predetermined period, and applies an OFF signal of a predetermined second voltage to the gate to turn off only for a predetermined period; The predetermined first voltage is temporally
First delay drive means for applying the voltage in a stepwise manner, and applying the predetermined second voltage to the gate
2. A gate drive circuit comprising: a second delay drive means for applying a voltage in a stepwise manner. 4. The method according to claim 1, wherein a predetermined first voltage is applied to the gate of the switching element.
A gate drive circuit that applies an ON signal of voltage to conduct for a predetermined period, and applies an OFF signal of a predetermined second voltage to the gate to turn off only for a predetermined period; The predetermined first voltage is temporally
A gate drive circuit comprising: delay drive means for applying a voltage in a stepwise manner; and a capacitor inserted between a positive side of a gate control signal line and an emitter of the switching element. 5. A predetermined first voltage applied to a gate of a switching element.
A gate drive circuit that applies an ON signal of voltage to conduct for a predetermined period, and applies an OFF signal of a predetermined second voltage to the gate to turn off only for a predetermined period; The predetermined second voltage is temporally
A gate drive circuit comprising: delay drive means for applying a voltage in a stepwise manner; and a capacitor inserted between a negative side of a gate control signal line and an emitter of the switching element. 6. A first predetermined voltage is applied to the gate of the switching element.
A gate drive circuit that applies an ON signal of voltage to conduct for a predetermined period, and applies an OFF signal of a predetermined second voltage to the gate to turn off only for a predetermined period; The predetermined first voltage is temporally
First delay drive means for applying the voltage in a stepwise manner, and applying the predetermined second voltage to the gate
Delay drive means for applying the power in a stepwise manner; a first capacitor inserted between the positive side of the gate control signal line and the emitter of the switching element; a negative side of the gate control signal line and the emitter of the switching element. And a second capacitor inserted between the gate drive circuit and the gate drive circuit.