JP3269092B2 - MOS circuit for intermittent conduction - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method in which a current flowing through an inductive load such as a motor, such as an inverter device or a chopper device, is subjected to PW
The present invention relates to an intermittent conduction MOS circuit including MOS transistors suitable for intermittent control using an M control method or the like.

[0002]

2. Description of the Related Art As is well known, when controlling the magnitude of a current supplied to a load, a PWM control method or the like in which a load current value is controlled by a duty ratio while interrupting the current is generally adopted. A bridge circuit using a transistor or the like as a switching element is widely used for the intermittent conduction circuit, but if the load is inductive, a diode is combined in parallel with each switching element for commutation when the load current is cut off. <br/>It's normal. Hereinafter will be described an example of a conventional intermittent energization circuit according with reference to subsequent FIGS.

FIG. 3 shows an example of a circuit using bipolar transistors as switching elements.
A bridge circuit 60 is formed by pn-type bipolar transistors 51 to 54. As is customary, the power supply 1 is connected between one of the opposite connection points on the upper and lower sides in the figure, and the other opposite connection point on the left and right sides in the figure. The inductive loads 2 to be intermittently supplied with electricity are connected between them. In the drawing of the four bridge-connected transistors 51 to 54, the transistor pairs 51 and 53 on the opposite sides cross-shaped and the transistor pairs 52 and 54 on the other opposite sides are, of course, simultaneously simultaneously driven by the signals received at their bases. In addition, on / off control is performed alternately.

FIG. 4 shows the on / off state. FIG. 4A shows the state of the transistor pair 51 and 53, and FIG. 4B shows the state of the transistor pair 52 and 54. Also,
The left half of the figure corresponds to the time when the current I flows in the load 2 in FIG. 3 in the forward direction as shown, and the right half corresponds to the time when the current I flows in the opposite direction opposite to the arrow. In any of the current directions, one of the two transistor pairs is kept in the off state and the other is in a predetermined short period T.
To perform an on-off operation, and control an effective average value of the magnitude of the load current I while controlling a duty ratio which is an on-time in each cycle T at this time.

However, the load current I is interrupted by the on / off operation, and when the load 2 is an inductive motor or the like, an excessive back electromotive force is generated when the current is interrupted. Therefore, as shown in FIG. Commutation diode to 51-54
It is customary to connect 61 in parallel. For example, when the transistor pair 51 and 53 are turned on, the current I flows to the load 2 in the direction shown in the figure, and then turned off, the two commutation diodes 61 corresponding to the other transistor pairs 52 and 54 are simultaneously turned on. Then, the current I flowing through the load 2 is commutated to the power supply 1 for a short time in the same direction as that of the current I to absorb the energy stored in the inductance of the load 2. Since the power source 1 usually includes a capacitor, the energy in the above-described inductance is temporarily stored in the capacitor by this commutation, and then the current I is supplied to the load 2 in the same or opposite direction. In this case, it is effectively used as a current source, that is, regenerated.

The intermittent energizing circuit shown in FIG. 3 composed of bipolar transistors is suitable for an inverter device or a chopper device. However, it is advantageous to reduce the intermittent period T of the load current I in order to reduce disturbances such as noise. In many cases, MOS transistors that can easily operate at a high frequency are used as switching elements. The present invention relates to such an intermittent conduction MOS circuit, and a conventional example thereof will be described below with reference to FIG.

The four MOS transistors 71 to 74 are usually connected to the bridge circuit 80 by using a high-frequency power element having a vertical structure of several tens of kHz. The procedure for connecting the power supply 1 and the load 2 to the bridge circuit 80 is the same as that in FIG. In principle, a commutation diode 81 is connected in parallel to each of the transistors 71 to 74.However, a parasitic diode 75 is attached to the MOS transistor, and if a current flows through this during commutation, the reverse recovery operation is delayed. , A diode 82 whose conduction direction is reversed is connected in series to each of the transistors 71 to 74, and a commutation diode is connected in parallel to this series circuit.
Connect 81. In the MOS circuit of FIG. 5, the intermittent cycle of the load current I is shorter than that of FIG. 3, and high-speed operation is required. In order to reduce this, a Schottky barrier diode having a small forward voltage is usually used as the series diode 82.

The M for intermittent conduction shown in FIG.
In the OS circuit, as in the case of FIG. 3, the pair of transistors 71 and 73 on one opposite side and the pair of transistors 72 and 74 on the other opposite side during bridge connection receive signals at their gates, respectively, as shown in FIG. ) And (b) are simultaneously and alternately controlled in the same manner as shown in (b). The same applies to controlling the load current I by controlling the duty ratio within the intermittent cycle T. When the transistor pairs 71 and 73 are turned on so that the load current I flows in the direction shown in FIG. 5, the corresponding series diode 82 is turned on, and when these transistors are turned off, the series diodes 82 corresponding to the other transistor pairs 72 and 74 are turned off. Commutation diodes
81 conducts and commutates the load current I to the power supply 1,
Within this commutation time, the series diode 82 becomes non-conductive, preventing current from flowing through the parasitic diode 75, thereby speeding up the circuit operation.

[0009]

However, in the conventional circuit shown in FIG. 5, since there is a weir layer voltage of the pn junction in the commutation diode 81, the forward voltage necessarily intervenes during the commutation operation described above. Commutation is likely to be incomplete. Although the forward voltage is about 0.5 V, a circuit loss always occurs when the power supply is intermittently repeated in the short cycle T described above.
As the operating frequency of the circuit increases, the reduction in circuit efficiency becomes a problem.

In order to increase the operation speed of the conventional circuit,
A series diode to prevent the commutation operation speed from being reduced by the parasitic diode 75, whose reverse recovery of the MOS transistors 71 to 74 is slow.
Since the circuit 82 must be connected, the circuit configuration becomes complicated, and a Schottky barrier diode must be used for preventing a decrease in circuit efficiency. Further, since it is necessary to use a high-speed diode also for the commutation diode 81, there is a problem that this is also expensive.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems of the prior art and to provide an intermittent energizing MOS circuit which can improve the commutation operation during intermittent energization to a load with a simple circuit configuration.

[0012]

According to the present invention, an MO
A bridge circuit composed of S-transistors and having a power supply connected between one opposed connection point and a load connected between the other opposed connection points, and a gate control circuit for simultaneously turning on and off a pair of transistors on opposite sides of the bridge. PWM
In a circuit that intermittently controls intermittent energization by a method, the other transistor pair is turned on during the commutation time when one transistor pair is turned off, and the other transistor pair is turned on during the commutation time.
The ON operation of one transistor pair is the same as the ON operation of one transistor pair.
Remote shortened due to Rukoto achieve the foregoing objects. In addition,
Advantageously, the gate control circuit has its operating time constant set to be shorter during the off-control than during the on-control. Further, the off-control for one transistor pair of the bridge circuit is simultaneously performed with the on-control for the other transistor pair. Is desirably configured to start.

[0013]

The present invention focuses on the fact that the MOS transistor has channel conductivity and does not include the weir layer voltage associated with the pn junction in the ON state, and uses the MOS transistor constituting the bridge circuit instead of the conventional commutation diode. Doing so will solve the problem. That is, according to the present invention, the commutation time of the load current when commutation of the load current is required when the transistor pair on one of the four MOS transistors constituting the bridge circuit is turned off in the present invention. The other pair of transistors on the opposite side is turned on by the gate control circuit and used instead of the commutation diode.

Since this commutation side MOS transistor has no weir layer voltage, it can conduct at a lower on-state voltage than the forward voltage of the conventional commutation diode and commutate the load current. Therefore, according to the present invention, the circuit configuration at the time of commutation is reduced as compared with the related art, and the circuit configuration is simplified because the commutation diode can be omitted. Note that the above-mentioned parasitic diode enters the forward direction in parallel with the on-resistance of the MOS transistor during the commutation operation, but the current naturally flows mainly toward the lower on-resistance, and the parasitic diode has very little current. Since only a part of the current flows, the commutation operation is not actually affected by the reverse recovery time, so that the circuit configuration can be further simplified by omitting the conventional series diode.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of an intermittent current supply MOS circuit according to the present invention and the state of ON / OFF operation of a MOS transistor, and FIG. 2 shows a configuration example and operation waveforms of a main part of a gate control circuit.

As shown in FIG. 1A, the intermittent conduction MOS circuit of the present invention comprises a bridge circuit 20 comprising four MOS transistors 11 to 14 and a gate control circuit 30,
As is customary, in the diagram of the bridge circuit 20, a DC power source 1 as a rectifier is provided between the upper and lower opposing connection points, and an inductive load such as a motor is connected between the other left and right opposing connection points in the diagram. 2 are respectively connected.

The bridge circuit 20 shown in FIG. 1A is a single-phase bridge. For example, when the load 2 is a DC motor, it is used for variable speed and reversible drive. The circuit 20 is a three-phase bridge, and the load 2 in the figure is used as an inverter circuit for variable-speed and reversible drive using each phase coil of the motor. The load driving MOS transistors 11 to 14 are usually vertical high-frequency MOS transistors which are individual elements having a withstand voltage of several tens of volts, a current rating of several tens of kHz, and a usable frequency of several tens of kHz. In the example shown in the figure, the bridge circuit 20 is composed of all n-channel MOS transistors 11 to 14, but the MOS transistors 11 and 12 on the positive voltage point side of the power supply 1 are arranged.
In some cases, a P-channel type is used.

In the example shown in the figure, since the MOS transistors 11 to 14 are all n-channel transistors, the transistor pairs 11 and 13 on one side of the bridge and the transistor pairs 12 and 14 on the other side are connected to a common gate, respectively. Gate control signals v1 and v2 supplied from the gate control circuit 30 are received by a common gate, respectively, and are turned on / off as shown in FIGS. 1 (b) and (c). In the figure, a gate control circuit 30 indicated by a block includes a clock pulse CP for designating the ON / OFF cycle T and a designation signal which is designating data such as a duty ratio in each cycle.
It includes a PWM control circuit for receiving SD and a gate drive circuit for generating gate control signals v1 and v2 based on the output as shown in FIG. 2 (a).

FIGS. 1B and 1C show such a gate control signal v1.
4 shows the on / off state of one transistor pair 11, 13 and the other transistor pair 12, 14 receiving the load current v2. The left half of the transistor pair 11, 13 receives the load current I of FIG. As shown, the flow in the forward direction corresponds to the case where the right half flows in the opposite direction to that in the figure. In the former case, one of the transistor pairs 11 and 13 receives the gate control signal v1 and turns on and off as shown in FIG. 1 (b). Of course, the duty ratio, which is the ratio of the ON / OFF cycle T to the ON time, is specified by the gate control signal v1. For example,
Period T is when MOS transistor is operated at 20 kHz
In 50 μs, the duty factor is the same as in the case of the present invention, but is desirably specified within a range of, for example, 0 to 50%.

In the present invention, the above-mentioned one transistor pair
In order to commutate the load current I during the off operation of 11, 13,
As shown in FIG. 1B, the other transistor pair 12, 14 is turned on within the time specified by the gate control signal v2. Although the time required for the commutation of the load current I varies depending on the circuit constant such as the inductance of the load 2, the period T is originally set to be considerably longer than the commutation time tf. 12, 14
Is set to be the same as the commutation time tf, which is usually advantageous for enhancing the commutation effect. Further, in this embodiment, the load 2
Of the transistor pairs 11 and 13 on the intermittent current supply side, and at the same time, start the ON control on the transistor pairs 12 and 14 on the commutation side. Such timing of commutation start is desirable for promoting commutation, and is advantageous in that the configuration of the gate control circuit 30 can be simplified.

By the on operation of the pair of transistors 12 and 14, the load current I which has been flowing in the direction shown in FIG. 1A into the load 2 shown in FIG. The electric power is returned to the power source 1 until the stored energy in the inductance of the load 2 disappears. As a result, the energy stored in the inductive load 2 is temporarily stored in a capacitor or the like in the power supply 1 and then regenerated when the current I is supplied to the load 2 as described above with reference to FIG.

At the time of such commutation, the channel conductivity MO
S-transistors 12 and 14 conduct at an on-voltage lower than the forward voltage of a conventional commutation diode, and commutate load current I without being restricted by the weir layer voltage. For example,
When a single-phase load 2 is driven by using an intermittent conduction MOS circuit supplied from a 12 V power supply 1 as an inverter, the conventional circuit of FIG. 5 has a forward voltage of 0.5 V per commutation diode 81. 1 causes a voltage loss of 1 V during commutation. In the case of FIG.
Since the on-resistance is about 20 mΩ when using a withstand voltage of 60 V, if the current during commutation is 10 A, 0.2
V, a voltage loss of 0.4 V is sufficient for two units, and the circuit loss can be reduced to about half or less of the conventional case.

During this commutation operation, the transistor 12 and
In 14, the parasitic diode 15 enters the forward direction in parallel with its on-resistance, but the current at the time of commutation flows only toward the low on-resistance with no weir layer voltage, and only a small part flows through the parasitic diode 15. Therefore, there is almost no possibility that the commutation operation is affected by the reverse recovery time of the parasitic diode 15.

The operation corresponding to the left half of FIGS. 1 (b) and 1 (c) has been described above. Of course, in the right half, only the on / off states of the transistor pairs 11, 13 and the transistor pairs 12, 14 are reversed. And the operation is exactly the same, so the description is omitted.
As can be seen by comparing FIG. 1 (a) with the conventional FIG. 5,
In the circuit of the present invention, the commutation diode 81 and the series diode 82, which are conventionally required, can be omitted, so that the configuration is greatly simplified.

Next, a configuration example and operation of the gate drive circuit in the gate control circuit 30 will be described with reference to FIG. Fig. 2 (a)
Denotes a MOS transistor denoted by reference numeral 10 and its gate driving portion in the gate control circuit 30. As is well known, M
Since the OS transistor 10 has a variable gate capacitance depending on the gate voltage v and repeats on / off operations including commutation within a short period T in the present invention, a waveform advantageous for commutation in accordance with the voltage dependence of the capacitance. Is preferably applied to the gate voltage v. In the gate drive circuit of FIG. 2, the time constant of the off control is set shorter than that of the on control.

The gate drive circuit shown in FIG.
, A series circuit of a resistor 32 and a diode 33 are connected in parallel, and the diode 33 is inserted in a direction in which the gate is non-conductive when charging the gate to a positive voltage and is conductive when discharging. FIG. 2B shows a gate voltage v when a positive voltage Vg is applied to the gate drive circuit to control the gate capacitance when the n-channel MOS transistor 10 is turned on. Immediately after the time t0 when the voltage Vg is applied, the charging is rapidly progressed because the capacitance is small, and the gate voltage v reaches the voltage Vt at a short time t1, but is substantially constant until the time t2 when the capacitance increases. Thereafter, it gradually rises with a time constant determined by the resistance 31 and the large capacitance, and at time t3, the MOS transistor
10 reaches the voltage Vg at which it is completely turned on.

FIG. 2C shows the waveform of the gate voltage v when the voltage Vg to the gate drive circuit is eliminated and the capacitance is discharged when the MOS transistor 10 is turned off. The capacitance immediately after the time t0 when the voltage Vg is cut is large, but since the diode 33 conducts, it is rapidly discharged with a time constant determined by the parallel resistance of the diode 31 and the resistors 31 and 32, and the gate voltage v becomes a time after a relatively short time. The voltage drops to the voltage Vt at t1, and the capacitance decreases at time t2 after maintaining the constant value for a while. Therefore, the voltage drops to 0 at time t3, which is a very short time, and the MOS transistor 10 is completely turned off. 2 (b) and 2 (c)
The period from time t1 to time t2 when the waveform of the gate voltage v is substantially constant is the time when the MOS transistor 10 transitions from off to on or vice versa.

In the gate drive circuit constructed as shown in FIG. 2 (a), the combined resistance of the resistors 31 and 32 is set so that no excessive back electromotive force is generated in the load 2 during the OFF control. For example, the resistance 32 is set to about one-third of the resistance 31 and the OFF operation time from t0 to t3 in FIG. 2C is about 1 μs of t0 to t3 in FIG. One half of the ON operation time or slightly less than this is shown in FIG.
This is advantageous in speeding up the operation of the circuit in commutation. That is, the off operation of the pair of MOS transistors 11 and 13 in FIG. 1 can be accelerated to promote commutation to the pair of MOS transistors 12 and 14.

In order to only speed up the commutation operation, the rising of the gate control signal v2 for the pair of transistors 12 and 14 on the commutation side may be shortened. If the on-resistance of the pair of transistors 12 and 14 on the commutation side becomes too low too quickly before the off-resistance of the power supply 1 has yet risen sufficiently, the power supply 1 will be in a state close to being short-circuited and large short-circuit prevention may occur. In order to prevent this, the rise of the gate control signal v2 to the commutation side is controlled by the gate control signal to the off operation side.
It is advantageous to delay the falling of v1 to an extent in accordance with the circuit conditions. In the embodiment of FIG. 2, the operation speed of the circuit of FIG. 1 can be improved while the commutation operation is rationally accelerated.

[0030]

As can be seen from the above description, according to the present invention, a power supply is connected between one opposing connection point and an inductive load to be intermittently connected between the other opposing connection points.
A bridge circuit composed of S transistors and a gate control circuit for simultaneously turning on and off the MOS transistor pairs on the opposite sides of the bridge at the same time in a PWM control method.
A circuit for controlling intermittent energization is configured so that the other MOS transistor pair is turned on by the gate control circuit within the commutation time of the load current during the off operation of one MOS transistor pair, and the other MOS transistor pair is turned on during the commutation time. ON of MOS transistor pair
Operation is shorter than ON operation of one MOS transistor pair
By Ku, it is possible to obtain the following effects.

(A) By using the MOS transistor in the bridge circuit instead of the conventional commutation diode, the load current is commutated at an on-voltage lower than the forward voltage of the commutation diode, and the commutation operation is performed. Circuit loss can be reduced. (b) The circuit configuration can be simplified by utilizing the MOS transistor of the bridge circuit instead of the commutation diode, and the power loss at the time of reverse recovery of the commutation diode can be eliminated. (c) Since the parasitic diode of the MOS transistor is almost short-circuited with a low on-resistance during the commutation operation, the current flowing through the parasitic diode can be reduced, and the reverse recovery time of the parasitic diode can eliminate the adverse effect on the commutation operation. The circuit configuration can be further simplified by eliminating the conventional series diode. (d) By promoting the commutation operation of the circuit by using the low on-resistance of the MOS transistor, the operation speed of the intermittent conduction circuit can be increased to operate at a higher frequency,
For example, when used as an inverter that supplies power to a motor, an intermittent current with a more accurate sine waveform can be supplied to the motor than before.

As described above, the present invention is applied to an intermittent conduction MOS circuit of an inverter device or a chopper device, thereby reducing unnecessary power loss in a circuit due to commutation, simplifying a circuit configuration, and streamlining the device. Further, the present invention has the effect of improving the performance of the device, and the implementation of the present invention can contribute to the further development of these device technologies.

[Brief description of the drawings]

FIGS. 1A and 1B show an embodiment of an intermittent conduction MOS circuit according to the present invention. FIG. 1A is a circuit diagram thereof, and FIGS.
FIG. 3 is an on / off waveform diagram of a transistor.

FIG. 2 shows a configuration example of a gate drive unit in a gate control circuit according to the present invention. FIG. 2 (a) is a circuit diagram thereof, and FIG.
(c) is a waveform diagram of the gate voltage at the time of ON control and at the time of OFF control for the MOS transistor, respectively.

FIG. 3 is a circuit diagram of a conventional intermittent conduction circuit using a bipolar transistor.

FIG. 4 is an ON / OFF waveform diagram of a transistor of a conventional intermittent conduction circuit corresponding to FIGS. 3 and 5;

FIG. 5 is a circuit diagram of a conventional intermittent conduction MOS circuit using a MOS transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Power supply 2 Inductive load 11 MOS transistor which comprises a bridge circuit 12 MOS transistor which comprises a bridge circuit 13 MOS transistor which comprises a bridge circuit 14 MOS transistor which comprises a bridge circuit 15 Parasitic diode of MOS transistor 20 Bridge circuit 30 Gate Control circuit I Load current T Intermittent cycle of conduction tf Commutation time

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H02M 7/5387 H02M 7/537

Claims (3)

(57) [Claims] 1. A bridge circuit comprising a MOS transistor and a power supply connected between one of the opposite connection points and an inductive load to be intermittently connected between the other opposite connection points, and a pair of opposite sides of the bridge. comprising simultaneously a gate control circuit turning on and off the MOS transistors, the intermittent energization
In a circuit intermittently controlled by the PWM control method, the other MOS transistor pair is controlled to be turned on by a gate control circuit within a commutation time of a load current when one of the MOS transistor pairs is turned off , and Other in time
The ON operation of one MOS transistor pair is
An intermittent energizing MOS circuit, which is shorter than the ON operation of a transistor pair . 2. A circuit according to claim 1, wherein a time constant at the time of off control of the gate control circuit is set shorter than a time constant at the time of on control of the gate control circuit.
S circuit. 3. The circuit according to claim 1, wherein
An intermittent conduction MOS circuit, wherein the on control of one MOS transistor pair is started simultaneously with the off control of another MOS transistor pair.