JP2001035967A - High-frequency semiconductor device - Google Patents

High-frequency semiconductor device

Info

Publication number
JP2001035967A
JP2001035967A JP20818899A JP20818899A JP2001035967A JP 2001035967 A JP2001035967 A JP 2001035967A JP 20818899 A JP20818899 A JP 20818899A JP 20818899 A JP20818899 A JP 20818899A JP 2001035967 A JP2001035967 A JP 2001035967A
Authority
JP
Japan
Prior art keywords
mounting
dielectric layer
wiring board
frequency semiconductor
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20818899A
Other languages
Japanese (ja)
Other versions
JP3987659B2 (en
Inventor
Maroaki Maetani
麿明 前谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP20818899A priority Critical patent/JP3987659B2/en
Publication of JP2001035967A publication Critical patent/JP2001035967A/en
Application granted granted Critical
Publication of JP3987659B2 publication Critical patent/JP3987659B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Landscapes

  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, which can suppress the ripple of the impedance of wiring after mounting of a high frequency semiconductor element, and also can remove the reflection of a high frequency signal due to change in line width and further enables a defective element after its mounting to be replaced easily, having a mounting structure improved in both the aspect of high frequency property and the aspect of manufacture process. SOLUTION: This high-frequency semiconductor device possesses a wiring board 21, which has a recess 22a at the topside of a dielectric substrate 22 and in which a line conductor 24 is made around the opening and earth conductors 23 and 23a are made at the lowerside and at the bottom of the recess 22a, a wiring board 25 for mounting which is attached to cover the opening of the recess 22a and whose connecting electrode 28a is abutted and connected to the line conductor 24, and a high-frequency semiconductor element 31 which is connected to a mounted electrode 30a. In this case, the wiring board 25 for mounting comprises a main dielectric layer 26, which is larger than the dimension of the opening of the recess 22a and moreover whose relative dielectric constant is larger than that of dielectric substrate 22, a sub dielectric layer 27 whose relative dielectric constant is smaller than that of the main dielectric layer 26, a line conductor 28 for mounting which is made between the main dielectric layer 26 and the sub dielectric layer 27 from a connecting electrode 28a, and a through-conductor 30 which connects the line conductor 28 for mounting to the mounted electrode 30a.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はマイクロ波もしくは
ミリ波を用いた通信機器もしくはセンサ等に使用される
高周波半導体装置に関し、特に高周波半導体素子の実装
構造を改善した高周波半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency semiconductor device used for communication equipment or sensors using microwaves or millimeter waves, and more particularly to a high-frequency semiconductor device having an improved mounting structure of a high-frequency semiconductor element.

【0002】[0002]

【従来の技術】従来、マイクロ波もしくはミリ波帯にお
いて動作する高周波半導体素子を主な回路素子とする高
周波電子回路モジュールにおいては、高周波半導体素子
が誘電体基板を用いた高周波半導体実装基板に実装さ
れ、さらに金属シャーシ内にこの高周波半導体実装基板
を他の回路基板等とともに収納する形態であった。
2. Description of the Related Art Conventionally, in a high-frequency electronic circuit module mainly including a high-frequency semiconductor element operating in a microwave or millimeter-wave band, the high-frequency semiconductor element is mounted on a high-frequency semiconductor mounting board using a dielectric substrate. Further, the high-frequency semiconductor mounting board is housed in a metal chassis together with other circuit boards and the like.

【0003】このような高周波半導体実装基板に高周波
半導体素子を実装して高周波半導体装置を構成する従来
の形態としては、例えば図8に要部断面図で示すよう
に、下面に接地導体3が、上面に凹部2aおよび凹部2
a開口周辺にかけて線路導体4が形成された誘電体基板
2から成る配線基板1に、凹部2aに実装用配線基板5
を収容するように搭載するとともに、この実装用配線基
板5上に高周波半導体素子7を導体バンプ10によりフリ
ップチップ実装して高周波半導体素子7の下面等に形成
された配線導体9と実装用配線基板5上の実装用線路導
体6とを電気的に接続するとともに、高周波半導体素子
7の裏面に形成された接地導体8とこの高周波半導体素
子7が搭載実装される配線基板1もしくは実装用配線基
板5に形成された接地接続用電極としてのダイマウント
用ランドパターン(図示せず)とを金スズ等のろう材
(図示せず)により接合し、さらに実装用配線基板5の
実装用線路導体6と外部電気回路としての配線基板1の
凹部2a開口周辺に形成された線路導体4とを金ワイヤ
11等を用いたワイヤボンディングによって電気的に接続
するというものが主であった。
A conventional high-frequency semiconductor device in which a high-frequency semiconductor device is mounted on such a high-frequency semiconductor mounting substrate is, for example, a ground conductor 3 on a lower surface as shown in a sectional view of a main part in FIG. The concave portion 2a and the concave portion 2
a wiring board 1 composed of a dielectric substrate 2 having a line conductor 4 formed around the periphery of the opening a;
And a wiring conductor 9 formed on the lower surface of the high-frequency semiconductor element 7 by flip-chip mounting the high-frequency semiconductor element 7 on the mounting wiring board 5 with the conductive bumps 10 and the mounting wiring board. 5 and a grounding conductor 8 formed on the rear surface of the high-frequency semiconductor element 7 and the wiring board 1 or the mounting wiring board 5 on which the high-frequency semiconductor element 7 is mounted. And a die mounting land pattern (not shown) as an electrode for ground connection formed by a brazing material (not shown) such as gold tin or the like. A line conductor 4 formed around the opening of the concave portion 2a of the wiring board 1 as an external electric circuit is connected to a gold wire.
Mainly, they are electrically connected by wire bonding using 11 or the like.

【0004】なお、図8において、12は実装用配線基板
5の下面を配線基板1の下面の接地導体3に凹部2aの
底面を介して電気的に接続するための接地用貫通導体、
13はこの高周波半導体装置に用いられたメタルシールド
である。
In FIG. 8, reference numeral 12 denotes a through conductor for grounding for electrically connecting the lower surface of the mounting wiring board 5 to the ground conductor 3 on the lower surface of the wiring board 1 via the bottom surface of the concave portion 2a.
Reference numeral 13 denotes a metal shield used in the high-frequency semiconductor device.

【0005】しかしながら、高周波半導体素子7の動作
周波数が高くなるにつれて接続用のボンディングワイヤ
11による寄生特性の影響が顕著になるために、近年は実
装用配線基板5の実装用線路導体6と配線基板1の線路
導体4とについても導体バンプを用いて電気的かつ機械
的に接続を行なうフリップチップ実装を採用し、このよ
うな寄生特性を抑制することが提唱されている。
However, as the operating frequency of the high-frequency semiconductor element 7 increases, the bonding wire for connection
In recent years, since the influence of the parasitic characteristics due to 11 becomes remarkable, in recent years, the mounting line conductor 6 of the mounting wiring board 5 and the line conductor 4 of the wiring board 1 are also electrically and mechanically connected using the conductor bumps. It has been proposed to adopt flip-chip mounting to suppress such parasitic characteristics.

【0006】通常、このようなフリップチップ実装は、
高周波半導体素子およびこれが搭載される高周波半導体
実装基板におけるそれぞれの入出力用の電極が形成され
た各主面を対向させ、高周波半導体素子上の電極とこの
電極に対応する実装基板上の電極とを導体バンプにより
電気的に接続する構造を有している。
[0006] Usually, such flip chip mounting is
The main surfaces on which the input / output electrodes of the high-frequency semiconductor element and the high-frequency semiconductor mounting board on which the high-frequency semiconductor element is mounted are opposed to each other, and the electrode on the high-frequency semiconductor element and the electrode on the mounting board corresponding to this electrode are connected. It has a structure to be electrically connected by conductor bumps.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、高周波
半導体素子はその表面における配線構造にマイクロスト
リップ線路等の線路導体を用いたプレーナ型伝送線路を
採用しており、そのインピーダンス設計は半導体素子単
体において最適化されているが、フリップチップ実装を
行なった際には、半導体素子表面の配線部下方に比較的
高い比誘電率を有する実装基板の誘電体が配置されるこ
とになるために、配線のインピーダンスが設計値と異な
る値になり、所望の回路動作が保証されなくなってしま
うという問題点があった。
However, the high-frequency semiconductor element employs a planar transmission line using a line conductor such as a microstrip line for the wiring structure on its surface, and its impedance design is optimal for a single semiconductor element. However, when flip-chip mounting is performed, the dielectric of the mounting substrate having a relatively high relative dielectric constant is arranged below the wiring portion on the surface of the semiconductor element, so that the impedance of the wiring is reduced. Has a value different from the design value, and a desired circuit operation cannot be guaranteed.

【0008】また、半導体素子と実装基板とが重なり合
う領域においては、線路導体の上下に半導体素子の誘電
体と実装基板の誘電体とが配される構造となるために、
インピーダンスを整合させるためには線路導体の線路幅
を狭くする必要があるが、このような線路幅の変化は高
周波信号の反射を引き起こす不連続点に相当するため、
特に高周波帯域においては信号伝送特性を劣化させる要
因となるという問題点があった。
In a region where the semiconductor element and the mounting board overlap each other, the dielectric of the semiconductor element and the dielectric of the mounting board are arranged above and below the line conductor.
In order to match the impedance, it is necessary to reduce the line width of the line conductor, but such a change in the line width corresponds to a discontinuous point that causes reflection of a high-frequency signal.
Particularly in the high frequency band, there is a problem that the signal transmission characteristics are deteriorated.

【0009】また、フリップチップ実装は元来高速ディ
ジタル回路素子の実装において実装面積の縮小化と不良
素子の交換性を向上させる技術として発展してきたが、
高周波半導体素子に対してベアチップによるフリップチ
ップ実装を行なった際には、機械的強度等の観点から不
良素子の実装後の交換が難しいため、マルチチップモジ
ュールを組み立てた際の良品率を高めることが困難であ
るという問題点もあった。
Flip-chip mounting has originally developed as a technique for reducing the mounting area and improving the exchangeability of defective elements in mounting high-speed digital circuit elements.
When performing flip-chip mounting of high-frequency semiconductor elements with bare chips, it is difficult to replace defective elements after mounting from the viewpoint of mechanical strength, etc., so it is possible to increase the rate of non-defective products when assembling multi-chip modules. There was also a problem that it was difficult.

【0010】本発明はかかる従来技術の問題点に鑑みて
案出されたものであり、その目的は、高周波半導体素子
の実装後における配線のインピーダンスの変動を抑える
とともに、線路幅の変化による高周波信号の反射をなく
すことができ、さらに実装後の不良素子の交換を容易に
行なうことができる、高周波特性面でも製造工程面でも
改善された実装構造を有する高周波半導体装置を提供す
ることにある。
The present invention has been devised in view of the above-mentioned problems of the prior art, and has as its object to suppress a change in the impedance of a wiring after mounting a high-frequency semiconductor element and to realize a high-frequency signal due to a change in a line width. An object of the present invention is to provide a high-frequency semiconductor device having an improved mounting structure in terms of high-frequency characteristics and manufacturing process, which can eliminate the reflection of light and can easily replace defective elements after mounting.

【0011】[0011]

【課題を解決するための手段】本発明の高周波半導体装
置は、誘電体基板の上面に高周波半導体素子を収容する
凹部を有し、この凹部の開口周辺に線路導体が形成され
るとともに、下面および前記凹部底面に接地導体が形成
された配線基板と、この配線基板上に前記凹部の開口を
覆うように取着され、下面周辺部に形成された接続電極
が前記線路導体に当接接続された実装用配線基板と、こ
の実装用配線基板の下面に形成された実装電極に導体バ
ンプを介して電気的に接続された高周波半導体素子とを
具備する高周波半導体装置であって、前記実装用配線基
板は、前記凹部の開口寸法より大きく、かつ前記誘電体
基板より比誘電率が大きい主誘電体層と、その下面に積
層された前記開口寸法より小さく、かつ前記主誘電体層
より比誘電率が小さい副誘電体層と、前記主誘電体層の
下面周辺部に形成された前記接続電極から前記主誘電体
層および前記副誘電体層間にかけて形成された実装用線
路導体と、この実装用線路導体を前記副誘電体層の下面
に形成された前記実装電極に電気的に接続する貫通導体
とから成ることを特徴とするものである。
The high-frequency semiconductor device of the present invention has a concave portion for accommodating a high-frequency semiconductor element on an upper surface of a dielectric substrate. A wiring board having a ground conductor formed on the bottom surface of the recess, and a wiring electrode mounted on the wiring board so as to cover an opening of the recess, and a connection electrode formed on a peripheral portion of the lower surface is in contact with the line conductor; A high-frequency semiconductor device comprising: a mounting wiring board; and a high-frequency semiconductor element electrically connected to a mounting electrode formed on a lower surface of the mounting wiring board via a conductive bump, wherein the mounting wiring board is provided. Is larger than the opening size of the concave portion, and a main dielectric layer having a larger relative dielectric constant than the dielectric substrate, and smaller than the opening size laminated on the lower surface thereof, and has a relative dielectric constant larger than the main dielectric layer. small A sub-dielectric layer, a mounting line conductor formed from the connection electrode formed around the lower surface of the main dielectric layer to the main dielectric layer and the sub-dielectric layer, and a mounting line conductor And a through conductor electrically connected to the mounting electrode formed on the lower surface of the sub-dielectric layer.

【0012】本発明の高周波半導体装置によれば、開口
周辺に線路導体が形成され、底面に接地導体が形成され
た、高周波半導体素子を収容する凹部を有する配線基板
に、実装用配線基板にフリップチップ実装された高周波
半導体素子を、実装用配線基板の実装用線路導体を介し
て配線基板の線路導体に電気的に接続するとともに凹部
に収容するようにして実装しており、この実装用配線基
板が凹部の開口に取着される比誘電率が大きい主誘電体
層とその高周波半導体素子側に積層された比誘電率が小
さい副誘電体層とから成ることから、高周波半導体素子
の内部および/または表面に形成された配線部の上方に
は従来の実装基板に比べて低い比誘電率を有する誘電体
を配置できるために、フリップチップ実装を行なった際
の高周波半導体素子における配線本来のインピーダンス
設計からのインピーダンスのずれ量を低く抑えることが
でき、従来のように、高周波半導体素子の配線部の下方
に比較的高い比誘電率を有する誘電体が配置されること
になるために配線のインピーダンスが設計値と異なる値
になり所望の回路動作が保証されない場合と比較して、
高周波半導体素子の特性について本来の設計値を保証す
ることができるものとなる。
According to the high-frequency semiconductor device of the present invention, a wiring substrate having a recess for accommodating a high-frequency semiconductor element, having a line conductor formed around an opening and a ground conductor formed on a bottom surface, is flipped to a wiring substrate for mounting. The chip-mounted high-frequency semiconductor element is electrically connected to the line conductor of the wiring board via the mounting line conductor of the mounting wiring board, and is mounted so as to be accommodated in the concave portion. Is composed of a main dielectric layer having a large relative dielectric constant attached to the opening of the concave portion and a sub-dielectric layer having a small relative dielectric constant laminated on the high-frequency semiconductor element side thereof. Alternatively, since a dielectric having a lower dielectric constant than that of a conventional mounting substrate can be arranged above the wiring portion formed on the surface, a high-frequency semiconductor element when flip-chip mounting is performed. , The amount of deviation of the impedance from the original impedance design of the wiring can be suppressed, and a dielectric having a relatively high relative dielectric constant is arranged below the wiring portion of the high-frequency semiconductor element as in the related art. Therefore, compared to the case where the impedance of the wiring becomes different from the design value and the desired circuit operation is not guaranteed,
The original design value of the characteristics of the high-frequency semiconductor element can be guaranteed.

【0013】また、実装用配線基板における内層配線の
線路導体の線路幅は、主誘電体層および副誘電体層の層
厚みならびに副誘電体層の表面から配線基板に形成され
た凹部底面の接地導体までの距離を用いることにより、
インピーダンス設計における自由度が増すこととなる。
その結果、線路導体の線路幅の変化量を極めて小さく抑
えることが可能となり、高周波信号の反射を引き起こす
ような不連続点に相当する部分をなくすことができ、信
号伝送特性を劣化させることがなくなるので、高周波信
号に対する良好な伝送特性を有する高周波半導体装置と
なる。
The line width of the line conductor of the inner layer wiring in the mounting wiring board is determined by the thickness of the main dielectric layer and the sub-dielectric layer and the grounding of the bottom surface of the concave portion formed on the wiring board from the surface of the sub-dielectric layer. By using the distance to the conductor,
This increases the degree of freedom in impedance design.
As a result, the amount of change in the line width of the line conductor can be kept extremely small, and a portion corresponding to a discontinuous point that causes reflection of a high-frequency signal can be eliminated, so that signal transmission characteristics do not deteriorate. Therefore, a high-frequency semiconductor device having good transmission characteristics for high-frequency signals is obtained.

【0014】さらに、高周波半導体素子を機械的強度の
高い実装用配線基板に実装した上でこの実装用配線基板
を配線基板に実装することから、実装後に不良素子が発
生した場合にもこの実装用配線基板を交換すればよいた
め、従来のようなベアチップ実装により実装後の不良素
子の交換が困難な実装構造のものと比較して、マルチチ
ップモジュールを構成した場合に全体の良品率を向上さ
せることが容易に達成できるものとなる。
Further, since the high-frequency semiconductor element is mounted on the mounting wiring board having high mechanical strength and the mounting wiring board is mounted on the wiring board, even if a defective element occurs after mounting, the mounting is performed. Since the wiring board only needs to be replaced, the overall non-defective rate is improved when a multi-chip module is configured, compared to a conventional mounting structure in which it is difficult to replace defective elements after mounting by bare chip mounting. Can be easily achieved.

【0015】[0015]

【発明の実施の形態】以下、図面に基づいて本発明の高
周波半導体装置について説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A high-frequency semiconductor device according to the present invention will be described below with reference to the drawings.

【0016】図1は本発明の高周波半導体装置の実施の
形態の一例を示す断面図、図2はその要部拡大断面図で
ある。また、図3は図2のA−A’線における要部断面
図、図4は図2のB−B’線における要部断面図、図5
は図2のC−C’線における要部断面図である。
FIG. 1 is a sectional view showing an example of an embodiment of a high-frequency semiconductor device according to the present invention, and FIG. 2 is an enlarged sectional view of a main part thereof. 3 is a cross-sectional view of a main part taken along line AA 'in FIG. 2, FIG. 4 is a cross-sectional view of a main part taken along line BB' in FIG.
FIG. 3 is a sectional view of a principal part taken along line CC ′ of FIG. 2.

【0017】これらの図において、21は配線基板であ
り、誘電体基板22の上面に高周波半導体素子を収容する
凹部22aを有し、この凹部22aの開口周辺に線路導体24
が形成されるとともに、下面および凹部22a底面に接地
導体23および23aが形成されている。
In these figures, reference numeral 21 denotes a wiring board, which has a concave portion 22a for accommodating a high-frequency semiconductor element on an upper surface of a dielectric substrate 22, and a line conductor 24 around an opening of the concave portion 22a.
Are formed, and ground conductors 23 and 23a are formed on the lower surface and the bottom surface of the concave portion 22a.

【0018】25は実装用配線基板であり、配線基板21の
凹部22aの開口寸法より大きく、かつ誘電体基板22より
比誘電率が大きい主誘電体層26と、その下面に積層され
た凹部22aの開口寸法より小さく、かつ主誘電体層26よ
り比誘電率が小さい副誘電体層27と、主誘電体層26の下
面周辺部に形成された接続電極28aから主誘電体層26お
よび副誘電体層27間にかけて形成された実装用線路導体
28と、この実装用線路導体28を副誘電体層27の下面に形
成された実装電極30aに電気的に接続する貫通導体30と
から成り、配線基板21上に凹部22aの開口を覆うように
取着され、主誘電体層26の下面周辺部に形成された接続
電極28aが線路導体24に当接接続されている。
Reference numeral 25 denotes a mounting wiring board, which is a main dielectric layer 26 having a larger relative opening than the opening size of the concave portion 22a of the wiring substrate 21 and a relative dielectric constant larger than that of the dielectric substrate 22, and a concave portion 22a laminated on the lower surface thereof. And a sub-dielectric layer 27 having a smaller relative dielectric constant than the main dielectric layer 26 and a connection electrode 28a formed around the lower surface of the main dielectric layer 26. Mounting line conductor formed between body layers 27
28, and a through conductor 30 for electrically connecting the mounting line conductor 28 to a mounting electrode 30a formed on the lower surface of the sub-dielectric layer 27, so as to cover the opening of the concave portion 22a on the wiring board 21. A connection electrode 28 a attached and formed around the lower surface of the main dielectric layer 26 is connected to the line conductor 24.

【0019】31は高周波半導体素子であり、実装用配線
基板25の副誘電体層27の下面に形成された実装電極30a
に導体バンプ34を介して端子電極(図示せず)が電気的
に接続されている。32は高周波半導体素子31の上面に形
成された配線部としての配線導体、33は高周波半導体素
子31の下面に形成された素子接地導体である。
Reference numeral 31 denotes a high-frequency semiconductor element, which is a mounting electrode 30a formed on the lower surface of the sub-dielectric layer 27 of the mounting wiring board 25.
A terminal electrode (not shown) is electrically connected to the terminal via a conductive bump. Reference numeral 32 denotes a wiring conductor serving as a wiring portion formed on the upper surface of the high-frequency semiconductor element 31, and reference numeral 33 denotes an element ground conductor formed on the lower surface of the high-frequency semiconductor element 31.

【0020】なお、29は実装用配線基板25の主誘電体層
26と副誘電体層27との間で実装用線路導体28と同一面に
形成された実装用同一面接地導体であり、この実装用同
一面接地導体29と実装用線路導体28とでコプレーナ線路
を構成している。また、この実装用同一面接地導体29は
配線基板21の上面において線路導体24と同一面に形成さ
れた同一面接地導体(図示せず)と電気的に接続される
ことによって、配線基板21から実装用配線基板25にかけ
てコプレーナ線路で接続された高周波回路が構成される
こととなる。
Reference numeral 29 denotes a main dielectric layer of the mounting wiring board 25.
The mounting plane conductor 28 is formed on the same plane as the mounting line conductor 28 between the sub-dielectric layer 26 and the sub-dielectric layer 27.This mounting plane conductor 29 and the mounting line conductor 28 form a coplanar line. Is composed. In addition, the same plane ground conductor 29 for mounting is electrically connected to the same plane ground conductor (not shown) formed on the same plane as the line conductor 24 on the upper surface of the wiring board 21 so that A high-frequency circuit connected to the mounting wiring board 25 by a coplanar line is configured.

【0021】35は配線基板21の下面の接地導体23と凹部
22a底面の接地導体23aとを電気的に接続するための接
地用貫通導体である。36は必要に応じて配線基板21に搭
載実装された実装用配線基板25を覆うように配線基板21
に取着される蓋体であり、ここではメタルシールドであ
る。37は線路導体24と接続電極28aとを電気的に接続す
るための例えば半田である。そして、38は凹部22a内あ
るいは配線基板21および実装用配線基板25と蓋体36との
間に存在する空気層を示している。
Reference numeral 35 denotes a ground conductor 23 on the lower surface of the wiring board 21 and a concave portion.
This is a through conductor for grounding for electrically connecting to the grounding conductor 23a on the bottom surface 22a. 36 is a wiring board 21 so as to cover the mounting wiring board 25 mounted on the wiring board 21 as necessary.
, Which is a metal shield here. Reference numeral 37 denotes, for example, solder for electrically connecting the line conductor 24 and the connection electrode 28a. Reference numeral 38 denotes an air layer existing in the recess 22a or between the wiring board 21 and the mounting wiring board 25 and the lid 36.

【0022】このような構成により、本発明の高周波半
導体装置は、上面に端子電極を有する高周波半導体素子
31と、この高周波半導体素子31の端子電極に対応してフ
リップチップ実装を行なうための実装電極30aおよび外
部電気回路としての配線基板21との入出力用の接続電極
28aを有する実装用配線基板25と、この接続電極28aに
対応して実装を行なうための線路導体24を有するととも
にフリップチップ実装された高周波半導体素子31および
実装用配線基板25の一部(副誘電体層27の部分)を収納
するための凹部22aを有する配線基板21とから成る実装
構造を有し、実装用配線基板25は比誘電率の異なる主誘
電体層26と副誘電体層27とを積層した多層構造を有して
おり、その基体となる主誘電体層26の露出面(上面)に
は接地導体が形成されておらず、主誘電体層26の比誘電
率が配線基板21を構成する誘電体基板22の比誘電率およ
び副誘電体層27の比誘電率よりも大きく、主誘電体層26
の寸法が配線基板21の誘電体基板22に設けられた凹部22
aの開口寸法よりも大きく、かつ副誘電体層27の寸法が
凹部22aの開口寸法よりも小さく形成されており、高周
波半導体素子31とのフリップチップ実装用の実装電極30
aはこの副誘電体層27の表面(下面)に形成されてお
り、配線基板21との接続電極28aは主誘電体層26の下面
周辺部において副誘電体層27が積層されていない領域に
形成されており、接続電極28a間の配線は主誘電体層26
と副誘電体層27との界面に形成された実装用線路導体28
および副誘電体層27内に形成された貫通導体30から成
り、実装用配線基板25副誘電体層27およびこの副誘電体
層27の下面にフリップチップ実装された高周波半導体素
子31を配線基板21に設けられた凹部22aに収容しつつ配
線基板21と実装用配線基板25との対応する電極同士を接
続する構成を有している。
With such a structure, the high-frequency semiconductor device of the present invention has a high-frequency semiconductor element having a terminal electrode on the upper surface.
A mounting electrode 30a for flip-chip mounting corresponding to the terminal electrode of the high-frequency semiconductor element 31, and a connection electrode for input / output with the wiring board 21 as an external electric circuit
A mounting wiring board 25 having a wiring conductor 28a and a line conductor 24 for mounting corresponding to the connection electrode 28a and a part of the high-frequency semiconductor element 31 and the mounting wiring board 25 which are flip-chip mounted (sub-dielectric And a wiring board 21 having a concave portion 22a for accommodating the body layer 27). The mounting wiring board 25 has a main dielectric layer 26 and a sub-dielectric layer 27 having different relative dielectric constants. And a ground conductor is not formed on the exposed surface (upper surface) of the main dielectric layer 26 serving as the base, and the relative dielectric constant of the main dielectric layer 26 The dielectric constant of the main dielectric layer 26 is larger than the relative dielectric constant of the dielectric substrate 22 and the
The size of the recess 22 provided on the dielectric substrate 22 of the wiring board 21 is
The size of the sub-dielectric layer 27 is larger than the size of the opening of the recess 22a, and the mounting electrode 30 for flip-chip mounting with the high-frequency semiconductor element 31 is formed.
a is formed on the surface (lower surface) of the sub-dielectric layer 27, and the connection electrode 28a with the wiring board 21 is formed in a region around the lower surface of the main dielectric layer 26 where the sub-dielectric layer 27 is not laminated. The wiring between the connection electrodes 28a is formed on the main dielectric layer 26.
Mounting line conductor 28 formed at the interface between
And a through-conductor 30 formed in the sub-dielectric layer 27, and a wiring board 25 for mounting. The sub-dielectric layer 27 and the high-frequency semiconductor element 31 flip-chip mounted on the lower surface of the sub-dielectric layer 27 are mounted on the wiring board 21. The corresponding electrodes of the wiring board 21 and the mounting wiring board 25 are connected to each other while being accommodated in the recess 22a provided in the wiring board 21.

【0023】このような構成の本発明の高周波半導体装
置において、実装用配線基板25を形成する主誘電体層26
および副誘電体層27は、いずれも単一の誘電体材料から
成る単層のものであってもよく、それぞれ複数の誘電体
層を積層して所望の比誘電率やその他の特性となるよう
にした多層構成のものであってもよい。このような主誘
電体層26および副誘電体層27としては、例えば主誘電体
層26には酸化アルミニウム質焼結体や窒化アルミニウム
質焼結体等のセラミックス材料を用い、副誘電体層27に
はポリイミドやポリテトラフルオロエチレン(PTF
E)・ベンゾシクロブテン(BCB)等の誘電体樹脂材
料を用いればよい。
In the high-frequency semiconductor device of the present invention having such a structure, the main dielectric layer 26 forming the mounting wiring board 25 is formed.
Each of the sub-dielectric layers 27 may be a single layer made of a single dielectric material, and may be formed by laminating a plurality of dielectric layers to obtain a desired relative permittivity and other characteristics. A multi-layer structure may be used. As the main dielectric layer 26 and the sub-dielectric layer 27, for example, the main dielectric layer 26 is made of a ceramic material such as an aluminum oxide sintered body or an aluminum nitride sintered body. Polyimide or polytetrafluoroethylene (PTF
E) A dielectric resin material such as benzocyclobutene (BCB) may be used.

【0024】そして、主誘電体層26を誘電体基板22より
比誘電率が大きいものとし、一方、副誘電体層27を主誘
電体層26よりも比誘電率が小さいものとする場合には、
例えばこれらを形成する実用的な誘電体材料から比誘電
率が2前後の小さいもの、4〜6程度のもの、8以上の
大きいものを選択し、これらの誘電体材料を比誘電率の
大きさに応じて適宜組み合わせて使用するようにすれば
よい。その際、誘電体基板22の比誘電率と副誘電体層27
の比誘電率とは、それぞれ主誘電体層26よりも小さいも
のであれば、同等の比誘電率のものを用いても、異なる
比誘電率のものを用いてもよく、高周波半導体装置の仕
様に応じてそれぞれの材料を適宜選択すればよい。
When the main dielectric layer 26 has a higher relative dielectric constant than the dielectric substrate 22 and the sub dielectric layer 27 has a lower relative dielectric constant than the main dielectric layer 26, ,
For example, from the practical dielectric materials for forming these materials, those having a relative dielectric constant of about 2 as small as about 2 to about 4 to 6 and those having a relative dielectric constant as large as 8 or more are selected. May be used in combination as appropriate. At this time, the relative permittivity of the dielectric substrate 22 and the sub-dielectric layer 27
The relative permittivity of the high-frequency semiconductor device may be the same or different as long as it is smaller than the main dielectric layer 26. May be appropriately selected depending on the conditions.

【0025】また、主誘電体層26の寸法を凹部22aの開
口寸法よりも大きくする場合、概ね開口寸法よりもそれ
ぞれ高周波信号の波長の4分の1程度かそれ以下程度で
大きいものとすればよく、副誘電体層27の寸法を凹部22
aの開口寸法よりも小さくする場合、実装の工作精度に
影響がない程度で、なるべく開口寸法に近い大きさとす
ればよい。
When the size of the main dielectric layer 26 is made larger than the opening size of the concave portion 22a, the size of the main dielectric layer 26 is set to be larger than the opening size by about の of the wavelength of the high-frequency signal or less. The size of the sub-dielectric layer 27 is
When the opening size is smaller than the opening size a, the size may be as close as possible to the opening size without affecting the working accuracy of the mounting.

【0026】なお、配線基板21を形成する誘電体基板22
についても、主誘電体層26よりも比誘電率が小さい誘電
体材料であれば実装用配線基板25と同様の材料を用いれ
ばよく、同様に単層としても多層構成としてもよい。
The dielectric substrate 22 forming the wiring substrate 21
As for the dielectric material, a material similar to that of the mounting wiring board 25 may be used as long as it is a dielectric material having a relative dielectric constant smaller than that of the main dielectric layer 26. Similarly, a single layer or a multilayer structure may be used.

【0027】また、配線基板21の誘電体基板22の凹部22
aの底面に形成された接地導体23aは、実装用配線基板
25に形成された線路導体28および高周波半導体素子31の
上面に形成された配線導体32に対して高周波信号に対す
るグランドとして機能するものである。
The concave portion 22 of the dielectric substrate 22 of the wiring substrate 21
The ground conductor 23a formed on the bottom surface of the mounting wiring board
The line conductor 28 formed at 25 and the wiring conductor 32 formed on the upper surface of the high-frequency semiconductor element 31 function as a ground for high-frequency signals.

【0028】この接地導体23aを始めとして接地導体23
・線路導体24・実装用線路導体28・接続電極28a・実装
用同一面接地導体29・貫通導体30・実装電極30a・配線
導体32・素子接地導体33・接地用貫通導体35には、高周
波用の導体として使用される種々の導体材料を使用すれ
ばよく、その形状や寸法等もその仕様に応じて適宜選択
すればよい。
Starting from the ground conductor 23a, the ground conductor 23
・ Line conductor 24 ・ Mounting line conductor 28 ・ Connection electrode 28a ・ Same-surface ground conductor 29 ・ Penetrating conductor 30 ・ Mounting electrode 30a ・ Wiring conductor 32 ・ Element ground conductor 33 ・ Ground through conductor 35 Various conductor materials used as the conductor may be used, and their shapes, dimensions, etc. may be appropriately selected according to their specifications.

【0029】また、導体バンプ34・半田37にも同様に高
周波用の導体バンプおよび実装用の半田として使用され
る種々の材料を使用すればよく、メタルシールド等の蓋
体36にも同様に蓋体として使用される種々の材料・形状
・寸法等を選択して適用すればよい。
Similarly, various materials used as high-frequency conductor bumps and solder for mounting may be used for the conductor bumps 34 and the solders 37, and the cover 36 such as a metal shield may be similarly used for the cover 36. What is necessary is just to select and apply various materials, shapes, dimensions, etc. used as a body.

【0030】次に、本発明の高周波半導体装置について
具体例を示す。
Next, specific examples of the high-frequency semiconductor device of the present invention will be described.

【0031】まず、厚み200 μmのアルミナセラミック
ス(比誘電率9.6 )から成る主誘電体層26上に実装用線
路導体28としての銅配線および厚み100 μmのポリイミ
ド(比誘電率3.4 )から成る副誘電体層27を薄膜形成
し、ポリイミド層表面において高周波半導体素子31の端
子電極に対応する個所に実装電極30aを設け、内層配線
となる実装用線路導体28と貫通導体30により接続させて
実装用配線基板25を作製した。
First, on a main dielectric layer 26 made of alumina ceramics (having a relative dielectric constant of 9.6) having a thickness of 200 μm, copper wiring as a mounting line conductor 28 and a sub-layer made of polyimide having a thickness of 100 μm (having a relative dielectric constant of 3.4) are used. A dielectric layer 27 is formed as a thin film, a mounting electrode 30a is provided at a position corresponding to a terminal electrode of the high-frequency semiconductor element 31 on the surface of the polyimide layer, and is connected by a mounting line conductor 28 serving as an inner layer wiring and a through conductor 30 for mounting. The wiring substrate 25 was manufactured.

【0032】また、厚み150 μm のガラスセラミックス
(比誘電率4.8 )を3層積層し、その内の2層分をくり
抜くことにより、凹部22aすなわちキャビティを有する
構造の誘電体基板22から成る配線基板21を作製した。な
お、この配線基板21においては3層目の表面に配線基板
21の配線としての線路導体24および入出力電極が、また
1層目表面すなわち凹部22a底部に接地導体23aが、そ
れぞれ銅ペーストを印刷して誘電体基板22と同時焼成す
ることにより厚膜として形成されており、接地導体23a
は1層目を貫通する接地用貫通導体35により配線基板21
の下面の接地導体23と電気的に接続されて接地をとる構
造となっている。
Further, three layers of glass ceramics (relative dielectric constant: 4.8) having a thickness of 150 μm are laminated, and two layers are hollowed out, thereby forming a recess 22a, that is, a wiring substrate comprising a dielectric substrate 22 having a cavity. 21 was produced. In the wiring board 21, the surface of the third layer is
A line conductor 24 and an input / output electrode as the wiring 21 and a ground conductor 23a on the surface of the first layer, that is, the bottom of the recess 22a, are each formed as a thick film by printing a copper paste and co-firing with the dielectric substrate 22. Ground conductor 23a
Is a wiring board 21 by a through conductor 35 for grounding penetrating the first layer.
And is electrically connected to the ground conductor 23 on the lower surface of the device.

【0033】また、配線基板21において、3層目の表面
から上方300 μmの位置には、配線基板21全体を被覆す
るメタルシールドとしての鉄−ニッケル−コバルト合金
から成る蓋体36を設けた。
A cover 36 made of an iron-nickel-cobalt alloy as a metal shield covering the entire wiring board 21 is provided at a position 300 μm above the surface of the third layer in the wiring board 21.

【0034】そして、フリップチップ実装の特性評価用
として、厚み100 μmのガリウムひ素基板に線路幅80μ
mのマイクロストリップ線路導体を形成し、入出力電極
部は信号線路の両端から各々70μm間隔のところに80μ
m×80μmの接地用電極を有するコプレーナ線路構造と
なっている高周波半導体素子31としての評価用基板を作
製し、高さ20μmの金から成る導体バンプ34を介して実
装用配線基板25に対してフリップチップ実装を行なっ
た。
For evaluation of the characteristics of flip chip mounting, a line width of 80 μm was formed on a gallium arsenide substrate having a thickness of 100 μm.
m microstrip line conductors, and the input and output electrodes are 80 μm at 70 μm intervals from both ends of the signal line.
A substrate for evaluation as a high-frequency semiconductor element 31 having a coplanar line structure having a ground electrode of mx 80 μm is manufactured, and is mounted on a mounting wiring substrate 25 via a conductive bump 34 made of gold having a height of 20 μm. Flip chip mounting was performed.

【0035】また、実装用配線基板25の副誘電体層27で
あるポリイミド層および高周波半導体素子31としての評
価用基板を凹部22a内に収容しつつ、主誘電体層26であ
るアルミナセラミックス層において露出している接続電
極28aと配線基板21の線路導体24とを半田37により接続
することにより、本発明の高周波半導体装置における実
装構造を実現した。
The polyimide layer as the sub-dielectric layer 27 of the mounting wiring board 25 and the evaluation substrate as the high-frequency semiconductor element 31 are accommodated in the recess 22a while the alumina dielectric layer 26 as the main dielectric layer 26 is formed. The mounting structure in the high-frequency semiconductor device of the present invention was realized by connecting the exposed connection electrode 28a and the line conductor 24 of the wiring board 21 by solder 37.

【0036】また一方、比較例として、厚み200 μmの
アルミナセラミックス基板上に線路幅200 μmのマイク
ロストリップ線路および高周波半導体素子31としての評
価用基板の端子電極に対応する実装電極を有する実装用
配線基板を作製し、同一の条件で評価用基板をフリップ
チップ接続したものを作製した。
On the other hand, as a comparative example, a mounting wiring having a microstrip line having a line width of 200 μm and a mounting electrode corresponding to a terminal electrode of an evaluation substrate as a high-frequency semiconductor element 31 on an alumina ceramic substrate having a thickness of 200 μm. A substrate was prepared, and a substrate for evaluation was flip-chip connected under the same conditions.

【0037】上記のような本発明の高周波半導体装置に
おける実装構造によれば、図3に示したA−A’線断面
においては、配線基板21上の線路導体の接続部とそれに
対応させて実装用配線基板25の主誘電体層26の下面に形
成された接続電極28aが半田37により接合されており、
実装用線路導体28の線路幅は80μm、実装用線路導体28
と接地導体23aとの間隔は130 μmとなる。また図4に
示したB−B’線断面は、実装用配線基板25の主誘電体
層26と副誘電体層27との界面に形成された実装線路構造
であり、実装用線路導体28の線路幅は80μm、実装用線
路導体28と接地導体23aとの間隔は80μmとなる。
According to the mounting structure of the high-frequency semiconductor device of the present invention as described above, in the cross section taken along the line AA 'shown in FIG. The connection electrode 28a formed on the lower surface of the main dielectric layer 26 of the wiring substrate 25 is joined by solder 37,
The line width of the mounting line conductor 28 is 80 μm, and the mounting line conductor 28
The distance between the ground conductor 23a is 130 μm. 4 is a mounting line structure formed at the interface between the main dielectric layer 26 and the sub-dielectric layer 27 of the mounting wiring board 25, and the cross section of the mounting line conductor 28 is shown in FIG. The line width is 80 μm, and the interval between the mounting line conductor 28 and the ground conductor 23a is 80 μm.

【0038】このような本発明の高周波半導体装置にお
けるA−A’線断面構造およびB−B’線断面構造の反
射特性を図6に線図で示す。図6において、横軸は周波
数(単位:GHz)を、縦軸は反射係数S11(単位:d
B)を表しており、実線で示した特性曲線AはA−A’
線断面における反射係数S11の周波数特性を、破線で示
した特性曲線BはB−B’線断面における反射係数S11
の周波数特性を示している。これによれば、いずれの伝
送線路構造も広帯域にわたって低い反射係数を実現でき
ていることが示されている。すなわち、いずれの伝送線
路構造においても、インピーダンス整合を取りつつ高周
波半導体素子31の配線導体32の線路幅と同程度の線路幅
を実現することが可能となっている。これにより、実装
用線路導体28における線路幅の変化を抑えることが可能
となるため、実装構造全体としての伝送においても良好
な伝送特性を実現することが可能となる。
FIG. 6 is a diagram showing the reflection characteristics of the cross-sectional structure along the line AA ′ and the cross-sectional structure along the line BB ′ in the high-frequency semiconductor device of the present invention. In FIG. 6, the horizontal axis represents the frequency (unit: GHz), and the vertical axis represents the reflection coefficient S11 (unit: d).
B), and the characteristic curve A indicated by the solid line is AA ′.
The characteristic curve B indicated by the broken line shows the frequency characteristic of the reflection coefficient S11 in the line section, and the reflection coefficient S11 in the BB 'line section.
2 shows the frequency characteristics of FIG. According to this, it is shown that any of the transmission line structures can realize a low reflection coefficient over a wide band. That is, in any of the transmission line structures, it is possible to realize a line width approximately equal to the line width of the wiring conductor 32 of the high-frequency semiconductor element 31 while maintaining impedance matching. This makes it possible to suppress a change in the line width of the mounting line conductor 28, so that good transmission characteristics can be realized even in the transmission of the entire mounting structure.

【0039】また、図1におけるC−C’線断面構造お
よび高周波半導体素子31の設計値の伝搬特性を図7に線
図で示す。ここでは、図4に示すB−B’線断面と同様
の主誘電体層26および副誘電体層27からなる実装用配線
基板25の下方20μmに高周波半導体素子31としての評価
用基板が配置されている。図7において、横軸は周波数
(単位:GHz)を、縦軸は伝搬定数の虚部、すなわち
位相定数β(単位:rad/m)を表している。実線で
示した特性曲線Cは、評価用基板の直上に評価用基板と
副誘電体層27との間の空気層・副誘電体層27・主誘電体
層26・空気層38が分布しているが、主誘電体層26の下面
に積層した副誘電体層27に比誘電率の比較的低い材料を
選択しているために、図7に示されるように、破線で示
した特性曲線Dで示される高周波半導体素子の特性では
位相特性にほとんど変化は見られなかった。
FIG. 7 is a diagram showing the cross-sectional structure taken along the line CC ′ in FIG. 1 and the propagation characteristics of the design values of the high-frequency semiconductor element 31. Here, an evaluation board as a high-frequency semiconductor element 31 is disposed 20 μm below a mounting wiring board 25 composed of a main dielectric layer 26 and a sub-dielectric layer 27 similar to the cross section taken along line BB ′ shown in FIG. ing. In FIG. 7, the horizontal axis represents the frequency (unit: GHz), and the vertical axis represents the imaginary part of the propagation constant, that is, the phase constant β (unit: rad / m). The characteristic curve C indicated by the solid line is obtained by distributing the air layer, the sub-dielectric layer 27, the main dielectric layer 26, and the air layer 38 between the evaluation substrate and the sub-dielectric layer 27 immediately above the evaluation substrate. However, since a material having a relatively low dielectric constant is selected for the sub-dielectric layer 27 laminated on the lower surface of the main dielectric layer 26, as shown in FIG. In the characteristics of the high-frequency semiconductor element indicated by, almost no change was observed in the phase characteristics.

【0040】また、図1は本発明の高周波半導体装置の
全体図を示す断面図であるが、図2からも明らかなよう
に、高周波半導体素子31は各々実装用配線基板25にフリ
ップチップ実装されているために、ある高周波半導体素
子31が不良であることが実装後に判明した場合において
も、配線基板1および実装用配線基板13の主誘電体層26
には、高周波半導体素子31に比べて機械的強度が強い材
料を選択することができ、その結果、製造における樹脂
の選択の自由度を高めるとともに、実装用配線基板13毎
に交換することが可能となり、半導体装置全体としての
良品率をも向上させることが可能となる。
FIG. 1 is a sectional view showing an overall view of the high-frequency semiconductor device of the present invention. As is clear from FIG. 2, the high-frequency semiconductor elements 31 are mounted on the mounting wiring board 25 by flip-chip mounting. Therefore, even if it is found after the mounting that a certain high-frequency semiconductor element 31 is defective, the main dielectric layer 26 of the wiring board 1 and the mounting wiring board 13 can be used.
In this case, it is possible to select a material that has higher mechanical strength than the high-frequency semiconductor element 31. As a result, it is possible to increase the degree of freedom in selecting a resin in manufacturing, and to replace the resin for each mounting wiring board 13. As a result, it is possible to improve the non-defective rate of the entire semiconductor device.

【0041】なお、以上はあくまで本発明の実施の形態
の例示であって、本発明はこれらに限定されるものでは
なく、本発明の要旨を逸脱しない範囲で種々の変更や改
良を加えることは何ら差し支えない。
It should be noted that the above is only an example of the embodiment of the present invention, and the present invention is not limited to the embodiment. Various changes and improvements may be made without departing from the gist of the present invention. No problem.

【0042】[0042]

【発明の効果】以上のように、本発明の高周波半導体装
置によれば、開口周辺に線路導体が形成され、底面に接
地導体が形成された、高周波半導体素子を収容する凹部
を有する配線基板に、実装用配線基板にフリップチップ
実装された高周波半導体素子を、実装用配線基板の実装
用線路導体を介して配線基板の線路導体に電気的に接続
するとともに凹部に収容するようにして実装しており、
この実装用配線基板が凹部の開口に取着される比誘電率
が大きい主誘電体層とその高周波半導体素子側に積層さ
れた比誘電率が小さい副誘電体層とから成ることから、
高周波半導体素子の内部および/または表面に形成され
た配線部の上方には従来の実装基板に比べて低い比誘電
率を有する誘電体を配置できるために、フリップチップ
実装を行なった際の高周波半導体素子における配線本来
のインピーダンス設計からのインピーダンスのずれ量を
低く抑えることができ、従来のように、高周波半導体素
子の配線部の下方に比較的高い比誘電率を有する誘電体
が配置されることになるために配線のインピーダンスが
設計値と異なる値になり所望の回路動作が保証されない
場合と比較して、高周波半導体素子の特性について本来
の設計値を保証することができるものとなる。
As described above, according to the high-frequency semiconductor device of the present invention, a wiring substrate having a recess for accommodating a high-frequency semiconductor element, having a line conductor formed around an opening and a ground conductor formed on a bottom surface, is provided. A high-frequency semiconductor element flip-chip mounted on the mounting wiring board is electrically connected to the line conductor of the wiring board via the mounting line conductor of the mounting wiring board, and is mounted in the recess. Yes,
Since this mounting wiring board is composed of a main dielectric layer having a large relative dielectric constant attached to the opening of the concave portion and a sub-dielectric layer having a small relative dielectric constant laminated on the high-frequency semiconductor element side,
Since a dielectric having a relative dielectric constant lower than that of a conventional mounting substrate can be arranged above the wiring portion formed inside and / or on the surface of the high-frequency semiconductor element, the high-frequency semiconductor when flip-chip mounting is performed. The amount of impedance deviation from the original impedance design of the wiring in the element can be kept low, and a dielectric having a relatively high relative dielectric constant is arranged below the wiring part of the high-frequency semiconductor element as in the past. As a result, the original design value of the characteristics of the high-frequency semiconductor element can be guaranteed as compared with the case where the impedance of the wiring becomes different from the design value and the desired circuit operation is not guaranteed.

【0043】また、実装用配線基板における内層配線の
線路導体の線路幅は、主誘電体層および副誘電体層の層
厚みならびに副誘電体層の表面から配線基板に形成され
た凹部底面の接地導体までの距離を用いることにより、
インピーダンス設計における自由度が増すこととなる。
その結果、線路導体の線路幅の変化量を極めて小さく抑
えることが可能となり、高周波信号の反射を引き起こす
ような不連続点に相当する部分をなくすことができ、信
号伝送特性を劣化させることがなくなるので、高周波信
号に対する良好な伝送特性を有する高周波半導体装置と
なる。
The line width of the line conductor of the inner wiring in the mounting wiring board is determined by the thickness of the main dielectric layer and the sub-dielectric layer, and the grounding of the bottom surface of the concave portion formed on the wiring board from the surface of the sub-dielectric layer. By using the distance to the conductor,
This increases the degree of freedom in impedance design.
As a result, the amount of change in the line width of the line conductor can be kept extremely small, and a portion corresponding to a discontinuous point that causes reflection of a high-frequency signal can be eliminated, so that signal transmission characteristics do not deteriorate. Therefore, a high-frequency semiconductor device having good transmission characteristics for high-frequency signals is obtained.

【0044】さらに、高周波半導体素子を機械的強度の
高い実装用配線基板に実装した上でこの実装用配線基板
を配線基板に実装することから、実装後に不良素子が発
生した場合にもこの実装用配線基板を交換すればよいた
め、従来のようなベアチップ実装により実装後の不良素
子の交換が困難な実装構造のものと比較して、マルチチ
ップモジュールを構成した場合に全体の良品率を向上さ
せることが容易に達成できるものとなる。
Furthermore, since the high-frequency semiconductor element is mounted on the mounting wiring board having high mechanical strength and the mounting wiring board is mounted on the wiring board, even if a defective element occurs after mounting, the mounting is performed. Since the wiring board only needs to be replaced, the overall non-defective rate is improved when a multi-chip module is configured, compared to a conventional mounting structure in which it is difficult to replace defective elements after mounting by bare chip mounting. Can be easily achieved.

【0045】以上により、本発明によれば、高周波半導
体素子の実装後における配線のインピーダンスの変動を
抑えるとともに、線路幅の変化による高周波信号の反射
をなくすことができ、さらに実装後の不良素子の交換を
容易に行なうことができる、高周波特性面でも製造工程
面でも改善された実装構造を有する高周波半導体装置を
提供することができた。
As described above, according to the present invention, it is possible to suppress the fluctuation of the impedance of the wiring after the mounting of the high-frequency semiconductor element, to eliminate the reflection of the high-frequency signal due to the change of the line width, and to prevent the defective element after the mounting. It is possible to provide a high-frequency semiconductor device that can be easily replaced and has a mounting structure improved in both high-frequency characteristics and manufacturing processes.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の高周波半導体装置の実施の形態の一例
を示す断面図である。
FIG. 1 is a sectional view showing an example of an embodiment of a high-frequency semiconductor device according to the present invention.

【図2】図1の要部拡大断面図である。FIG. 2 is an enlarged sectional view of a main part of FIG.

【図3】図2のA−A’線における要部断面図である。FIG. 3 is a cross-sectional view of a principal part taken along line A-A ′ of FIG. 2;

【図4】図2のB−B’線における要部断面図である。FIG. 4 is a cross-sectional view of a principal part taken along line B-B 'of FIG.

【図5】図2のC−C’線における要部断面図である。FIG. 5 is a cross-sectional view of a principal part taken along line C-C ′ in FIG. 2;

【図6】本発明の高周波半導体装置におけるA−A’線
断面構造およびB−B’線断面構造の反射特性を示す線
図である。
FIG. 6 is a diagram showing reflection characteristics of a cross-sectional structure taken along line AA ′ and a cross-sectional structure taken along line BB ′ in the high-frequency semiconductor device of the present invention.

【図7】本発明の高周波半導体装置におけるC−C’線
断面構造および高周波半導体素子の位相定数の周波数特
性を示す線図である。
FIG. 7 is a diagram showing a cross-sectional structure taken along line CC ′ in the high-frequency semiconductor device of the present invention and a frequency characteristic of a phase constant of the high-frequency semiconductor element.

【図8】従来の高周波半導体装置の例を示す要部拡大断
面図である。
FIG. 8 is an enlarged sectional view of a main part showing an example of a conventional high-frequency semiconductor device.

【符号の説明】[Explanation of symbols]

21・・・・・配線基板 22・・・・・誘電体基板 22a・・・・凹部 23、23a・・接地導体 24・・・・・線路導体 25・・・・・実装用配線基板 26・・・・・主誘電体層 27・・・・・副導体層 28・・・・・実装用線路導体 28a・・・・接続電極 30・・・・・貫通導体 34・・・・・導体バンプ 21 ... Wiring board 22 ... Dielectric board 22a ... Recess 23,23a ... Ground conductor 24 ... Line conductor 25 ... Mounting wiring board 26 ... ···· Main dielectric layer 27 ····· Sub conductor layer 28 ····· Line conductor for mounting 28a ···· Connection electrode 30 ·························· Bump

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 誘電体基板の上面に高周波半導体素子を
収容する凹部を有し、該凹部の開口周辺に線路導体が形
成されるとともに、下面および前記凹部底面に接地導体
が形成された配線基板と、該配線基板上に前記凹部の開
口を覆うように取着され、下面周辺部に形成された接続
電極が前記線路導体に当接接続された実装用配線基板
と、該実装用配線基板の下面に形成された実装電極に導
体バンプを介して電気的に接続された高周波半導体素子
とを具備する高周波半導体装置であって、前記実装用配
線基板は、前記凹部の開口寸法より大きく、かつ前記誘
電体基板より比誘電率が大きい主誘電体層と、その下面
に積層された前記開口寸法より小さく、かつ前記主誘電
体層より比誘電率が小さい副誘電体層と、前記主誘電体
層の下面周辺部に形成された前記接続電極から前記主誘
電体層および前記副誘電体層間にかけて形成された実装
用線路導体と、該実装用線路導体を前記副誘電体層の下
面に形成された前記実装電極に電気的に接続する貫通導
体とから成ることを特徴とする高周波半導体装置。
1. A wiring board having a concave portion for accommodating a high-frequency semiconductor element on an upper surface of a dielectric substrate, a line conductor formed around an opening of the concave portion, and a ground conductor formed on the lower surface and the bottom surface of the concave portion. And a mounting wiring board attached to the wiring board so as to cover the opening of the concave portion, and a connection electrode formed on the lower surface periphery is connected to the line conductor, and a mounting wiring board, A high-frequency semiconductor device comprising: a high-frequency semiconductor element electrically connected to a mounting electrode formed on a lower surface via a conductor bump, wherein the mounting wiring board is larger than an opening dimension of the concave portion, and A main dielectric layer having a larger relative dielectric constant than the dielectric substrate, a sub-dielectric layer smaller than the opening dimension laminated on the lower surface thereof, and having a lower relative dielectric constant than the main dielectric layer; and the main dielectric layer. Formed around the lower surface of A mounting line conductor formed from the connection electrode thus formed to the main dielectric layer and the sub-dielectric layer, and the mounting line conductor electrically connected to the mounting electrode formed on the lower surface of the sub-dielectric layer. And a through conductor connected to the high frequency semiconductor device.
JP20818899A 1999-07-22 1999-07-22 High frequency semiconductor device Expired - Fee Related JP3987659B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20818899A JP3987659B2 (en) 1999-07-22 1999-07-22 High frequency semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20818899A JP3987659B2 (en) 1999-07-22 1999-07-22 High frequency semiconductor device

Publications (2)

Publication Number Publication Date
JP2001035967A true JP2001035967A (en) 2001-02-09
JP3987659B2 JP3987659B2 (en) 2007-10-10

Family

ID=16552131

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20818899A Expired - Fee Related JP3987659B2 (en) 1999-07-22 1999-07-22 High frequency semiconductor device

Country Status (1)

Country Link
JP (1) JP3987659B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002350793A (en) * 2001-05-23 2002-12-04 Mitsubishi Electric Corp Photoelectric conversion semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002350793A (en) * 2001-05-23 2002-12-04 Mitsubishi Electric Corp Photoelectric conversion semiconductor device

Also Published As

Publication number Publication date
JP3987659B2 (en) 2007-10-10

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