JP2001035940A - Mask structure for semiconductor memory and manufacture of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the mask structure of a semiconductor memory for controlling the threshold voltage of only a desired data writing bit without affecting the threshold voltage of an adjacent bit by suppressing the spread of ion to a horizontal direction near a projection range just under a gate oxide film at the time of operating data writing by inter-layer through high energy injection. SOLUTION: A plurality of MOS transistors are arranged on a substrate 1, and ion implantation is selectively operated by using resist masks for the channel parts of the prescribed transistors so that data writing can be attained in this mask structure of a semiconductor memory. In this case, the cross-sectional shape of the opening of a resist mask 6 for operating the data writing is provided with a taper T.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a mask structure of a semiconductor memory device and a method of manufacturing a semiconductor memory device, and more particularly to a mask structure of a semiconductor memory device suitable for a mask ROM and a method of manufacturing a semiconductor memory device.

[0002]

2. Description of the Related Art A conventional technique will be described below. Here, particularly, a description will be given of a process of writing ion implantation data of a large-capacity FLATNOR type mask ROM having fine processing of sub-half micron or less. Note that NAND
The same applies to molds.

FIG. 10 is a cross-sectional view showing a conventional structure in a high-energy ion implantation data writing step using a photoresist mask. FIG. 11 is a cross-sectional view in the manufacturing step.
FIG. 12 is a diagram for explaining a conventional problem when code data is densely distributed.

As shown in FIGS. 10 and 11, in order to write OFF to the middle bit of the FLAT cell (to increase the threshold voltage), a voltage of 0. Boron is implanted to a depth of from 0.5 to 0.1 μm, but as the miniaturization progresses, the influence on the threshold voltage of the left and right adjacent ON bits cannot be ignored.

For example, the polycide gate electrode 3 has a pitch of 0.28 μmL / S (line and space) as a base, and the total film thickness of (interlayer insulating film 4 + polycide gate electrode 3 + gate oxide film 2) is 0.6 μm. When the data aperture is 0.24 μm, boron is set to 250 to 300 keV.
Is implanted at an acceleration voltage of 1.0 to 2.0E14 cm ^−2, but at this time, adjacent boron is diffused in the horizontal direction near a projection range (hereinafter abbreviated as Rp) immediately below the gate oxide film 2. The threshold voltage of the ON bit increases by 0.1 to 0.3 V. In the worst case, the sense amplifier circuit makes an erroneous determination and sets the ON bit to OF.
It is not recognized as an F bit. Therefore, in the conventional technology,
There is a problem that a stable yield of the device cannot be obtained.

To solve this problem, see, for example, Nikkei Microdevices December 1991, p. As described in 104 to 109, the interlayer insulating film 4 is thinned, and
A method of lowering the accelerating voltage, and a method of
Japanese Patent Application Laid-Open No. 5-48045 discloses a method for producing an opening smaller than the minimum resolution dimension by the two-layer resist method.

[0007] However, in the case of fine processing (0.24 μm or less) of sub-half micron or less due to the increase in capacity, even with these methods, the adjacent bits are not formed due to the spread of ions in the horizontal direction near Rp. It has become difficult to suppress fluctuations in the threshold voltage to a level at which the sense amplifier circuit does not judge incorrectly.

Another problem has arisen with miniaturization. That is, the write data pattern varies depending on the customer, but there are always dense and sparse places (not shown) as shown in FIG. In such a state, when the light exposure technique is used, if a sparse pattern is opened according to the mask, as shown in FIG. 12B, in a dense place as shown in FIG. Overexposure occurs due to the proximity effect due to light diffraction, and the resist at the portion separating the opening becomes thin. For this reason, in an extreme case, as shown in FIG.
Further, there is a problem that the fallen mask serves as an implantation mask, and ions are not implanted where it should be implanted.

In the prior art, because of the above problems, it has been difficult to reduce the chip size and increase the capacity by further miniaturization.

[0010]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks of the prior art, and particularly, when performing data writing by high energy injection through an interlayer film, in the vicinity of a projection range immediately below a gate oxide film. Novel semiconductor that can control only the threshold voltage of the desired data write bit accurately without affecting the threshold voltage of the adjacent bit by suppressing the spread of ions in the horizontal direction An object of the present invention is to provide a mask structure of a storage device and a method of manufacturing a semiconductor storage device.

Another object of the present invention is that when a data write mask is a photoresist film, a resist opening becomes considerably larger than a target aperture due to an optical proximity effect in an area where write data is dense, and the gap between the openings is separated. Even when the resist to be thinned, the opening cross section is formed in an inverted triangle or a trapezoidal trapezoid, so that the mask has a shape diverging toward the bottom of the opening, thereby improving the adhesion to the base, and Accordingly, it is an object of the present invention to provide a novel mask structure of a semiconductor memory device and a method of manufacturing the semiconductor memory device in which the fall of a resist pattern is suppressed and the yield is improved.

[0012]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object.

That is, in a first aspect of the mask structure of the semiconductor memory device according to the present invention, a plurality of MOS transistors are arranged on a substrate, and the channel portions of these predetermined transistors are selectively formed using a resist mask. A mask structure of a semiconductor memory device in which data is written by performing ion implantation, wherein a cross-sectional shape of an opening of the resist mask for writing data has a taper. And the second aspect is:
A mask structure of a semiconductor memory device in which a plurality of MOS transistors are arranged on a substrate, and data is written by selectively performing ion implantation using a resist mask in a channel portion of these predetermined transistors, The cross-sectional shape of the opening of the resist mask for writing data is formed larger on the front surface side of the substrate, and formed in an inverted triangular shape not forming an opening on the transistor side, According to a third aspect, there is provided a semiconductor memory device in which a plurality of MOS transistors are arranged on a substrate, and data is written by selectively performing ion implantation using a resist mask in a channel portion of these predetermined transistors. The cross-sectional shape of the opening of the resist mask for writing data, Formed larger on the side, which is characterized in that formed small in transistor side, or,
A fourth aspect is a mask structure of a semiconductor memory device in which a plurality of MOS transistors are arranged on a substrate, and data is written by selectively performing ion implantation using a mask in a channel portion of these predetermined transistors. An opening for writing data is provided in an interlayer insulating film formed on the entire surface so as to cover the transistor, and a cross-sectional shape of the opening is formed large on the front surface side of the substrate. According to a fifth aspect, a plurality of MOs are formed on a substrate.
An S transistor is arranged, and a mask structure of a semiconductor memory device in which data is written by selectively performing ion implantation by using a mask in a channel portion of these predetermined transistors so as to cover the transistor. An opening for writing data is provided in the interlayer insulating film formed on the entire surface, and the cross-sectional shape of the opening is formed large on the front surface side of the substrate, and an inverted triangle not forming an opening on the gate. It is characterized by being formed in a shape.

In a first aspect of the method of manufacturing a semiconductor memory device according to the present invention, a plurality of MOS transistors are arranged on a substrate, and the channel portions of these predetermined transistors are selectively formed by using a resist mask. A method for manufacturing a semiconductor memory device in which data is written by performing ion implantation, wherein a cross-sectional shape of an opening of the resist mask for performing data writing is formed large on a surface side of a substrate, and a transistor side is formed. And a second step of implanting ions through the opening formed in the first step. In the second mode, a plurality of MOS transistors are arranged on a substrate, and a channel portion of each of these transistors is selectively etched using a resist mask. A method for manufacturing a semiconductor memory device in which data is written by performing a mask implantation, wherein a cross-sectional shape of an opening of the resist mask for performing data writing is formed large on a surface side of a substrate, and a transistor side is formed. A first step of reducing the size in the first step, a second step of performing ion implantation through the opening formed in the first step,
The third aspect is characterized in that
In the first step, an opening is formed in the resist mask by etching.
In a fourth aspect, in the first step, the resist mask is processed by an electron beam direct writing method. In a fifth aspect, a plurality of MOS transistors are arranged on a substrate. A method for manufacturing a semiconductor memory device in which data is written by selectively performing ion implantation using a mask on a channel portion of each of these predetermined transistors, wherein the entire surface is formed so as to cover the transistor. In the interlayer insulating film, an opening for writing data is provided, and a cross-sectional shape of the opening is formed to be large on the surface side of the substrate and etched in an inverted triangular shape in which no opening is formed on the gate. A first step; and a second step of performing ion implantation through the opening formed in the first step.
According to a sixth aspect, there is provided a method of manufacturing a semiconductor memory device in which a plurality of MOS transistors are arranged on a substrate, and data is written by selectively performing ion implantation using masks in channel portions of these predetermined transistors. And
An opening for writing data is provided in an interlayer insulating film formed over the entire surface so as to cover the transistor, and the cross-sectional shape of the opening is formed large on the front surface side of the substrate and small on the gate. The method is characterized by including a first step of performing etching so as to form and a second step of performing ion implantation through the opening formed in the first step.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The mask structure of a semiconductor memory device according to the present invention is particularly suitable for an ion implantation data writing step of a large-capacity mask ROM having fine processing of sub-half micron or less. This is because the cross-sectional shape of the mask opening is an inverted triangle or a trapezoid.

Thus, when data writing is performed by high energy injection through the interlayer film, the spread of ions in the horizontal direction near the projection range (hereinafter abbreviated as Rp) immediately below the gate oxide film is suppressed, and adjacent bits are suppressed. The threshold voltage of only the desired data write bit can be stably controlled without affecting the threshold voltage.

Further, when the data write mask is a photoresist film, the resist opening becomes considerably larger than the target due to the optical proximity effect in the area where the write data is dense, and the resist separating the openings becomes thin. Even in such a case, by making the opening cross-sectional shape an inverted triangle or an inverted leg trapezoid, the mask has a shape diverging toward the bottom of the opening, thereby increasing the adhesion with the base,
Resist pattern collapse can be suppressed, and the yield can be improved.

[0018]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention;

(First Embodiment) FIG. 1 is a sectional view showing a structure of a first embodiment of the present invention, FIG. 2 is a sectional view showing a manufacturing process, and FIG. 3 is a dense distribution of code data. FIGS. 5A and 5B are diagrams illustrating the effect of the present invention in the case where a plurality of MOS transistors are arranged on a substrate, and using a resist mask in a channel portion of these predetermined transistors.
A mask structure of a semiconductor memory device in which data is written by selectively performing ion implantation, wherein a cross-sectional shape of an opening 6A of the resist mask 6 for writing data has a taper T. A mask structure of the semiconductor memory device, and an opening 6 of the resist mask 6 for writing the data.
A is formed with a large cross-sectional shape on the surface 11 side of the substrate 1,
Inverted triangle 21 having no opening on transistor 12 side
FIG. 1 shows a mask structure of a semiconductor memory device characterized by being formed in a shape. Further, a plurality of MOS transistors are arranged on a substrate, and a channel portion of these predetermined transistors is selectively formed by using a resist mask. A method for manufacturing a semiconductor memory device in which data is written by performing ion implantation, wherein a cross-sectional shape of an opening 6A of the resist mask 6 for writing data is formed to be large on the surface 11 side of the substrate. A first step of processing the transistor 12 into an inverted triangular shape 21 in which no opening is formed and a second step of performing ion implantation through the opening 6A formed in the first step. Is shown.

Hereinafter, the first specific example will be described in more detail.

Here, the ion implantation data writing step of a large-capacity FLATNOR type mask ROM having a fine processing of sub-half micron or less will be described. However, the present invention can be similarly applied to a NAND type. it can.

The cross section of the opening of the present invention has an inverted triangular cross section obtained by taper etching the first resist film 6 using the second resist film 5 as a mask. p + diffusion layer 7 does not reach adjacent bits,
The structure is such that fluctuation of the threshold voltage is suppressed.

Next, the manufacturing method according to the first embodiment of the present invention will be described.

As shown in FIG. 1, after a gate oxide film 2 is formed on a P-type silicon substrate 1 in a thickness of 0.005 to 0.03 μm, a polycide gate electrode 3 is formed in a thickness of 0.25 to 0.40 μm.
It is formed with an L / S of 0.15 to 0.24 μm. Subsequently, when the interlayer insulating film 4 is formed in a thickness of 0.3 to 0.7 μm,
The base of the mask ROM is completed.

Next, after the first and second resist films 6 and 5 are applied, an opening 5A of 0.15 to 0.24 μm is formed in the second resist film 6 only in the write data portion by the light exposure technique. Form.

Subsequently, the first resist film 6 is taper-etched using the second resist film 5 as a mask, so that the cross-sectional shape of the first resist film 6 becomes an inverted triangle 21.

Thereafter, an acceleration voltage of 100 to 380 keV
With a dose of 1.0 to 3.0E14cm ^-2Inject boron
Then, ap + diffusion layer 7 is formed.

Here, the opening 6A of the first resist film 6
Is an inverted triangle, the boron implantation region shifts toward the interlayer insulating film 4 as the distance from the vertex of the inverted triangle increases. For this reason, even if there is a lateral spread near Rp, it does not reach the P-type silicon substrate 1 of the adjacent bit, so that the influence on the threshold voltage of the adjacent transistor can be suppressed.

Further, if a sparse pattern is opened according to the mask, in a dense place as shown in FIG.
As shown in FIG. 12B, overexposure occurs due to the proximity effect due to light diffraction, and the resist at the portion separating the opening becomes thin. However, the cross-sectional shape of the opening of the mask is an inverted triangle, that is, the bottom of the opening. Therefore, the adhesiveness of the mask to the base can be improved as compared with the prior art, resist pattern collapse can be suppressed, and the yield can be stabilized.

(Second Embodiment) FIG. 4 is a sectional view showing a structure of a second embodiment of the present invention, and FIG. 5 is a sectional view showing a manufacturing method thereof.

The difference between this embodiment and the first embodiment is that an electron beam direct writing method is used for manufacturing a data write mask. Thereby, the process can be simplified as compared with the multilayer resist method of the first specific example.

That is, as shown in FIG. 5B, by gradually narrowing the electron beam from the surface of the first resist film 5 toward the interlayer insulating film 4, the shape of the opening becomes an inverted triangular shape. I do.

(Third Specific Example) The specific example of FIG. 6 is an example in which the shape of the opening is slightly larger than that of the first specific example and is formed in an inverted trapezoidal shape. FIG. FIG.

Therefore, in the mask structure of the semiconductor memory device of this specific example, a plurality of MOS transistors are arranged on a substrate, and ions are selectively implanted in the channel portions of these predetermined transistors by using a resist mask. Thus, in the mask structure of the semiconductor memory device for writing data, the cross-sectional shape of the opening 6B of the resist mask for writing data is formed large on the surface 11 side of the substrate 1 and the transistor 12 side Further, in the method of manufacturing a semiconductor memory device according to this specific example, a plurality of MOS transistors are arranged on a substrate, and a resist mask is formed on a channel portion of these predetermined transistors. And a method for manufacturing a semiconductor memory device in which data is written by selectively performing ion implantation. A first step in which the cross-sectional shape of the opening 6B of the resist mask 6 for writing data is formed larger on the surface 11 side of the substrate and smaller on the transistor 12 side; And a second step of performing ion implantation through the formed opening 6B.

(Fourth Embodiment) FIG. 7 is a sectional view showing a structure of a fourth embodiment of the present invention, and FIG. 8 is a sectional view showing a method for manufacturing the same.

The difference between this embodiment and each of the above embodiments is that ions are implanted using an interlayer insulating film as a mask. Thereby, the process can be simplified as compared with the above-described multilayer resist method. Furthermore, since the ion implantation can be performed with an acceleration voltage enough to penetrate the polycide gate electrode 3, the lateral spread of ions near Rp can be reduced by the first and second ions.
As compared with the specific example, the effect can be further suppressed.

As shown in FIG. 8B, an opening 16A is formed in the first resist film 16 using a conventional light exposure technique, and then the interlayer insulating film 4 is tapered etched by a dry etching technique. Thus, a hole 4B having an inverted trapezoidal cross section can be obtained. After writing data, the hole 4B of the interlayer insulating film 4 may be backfilled with, for example, a BPSG film.

Therefore, the mask structure of the semiconductor device according to this embodiment has a structure in which a plurality of MOS transistors are arranged on a substrate, and ion implantation is selectively performed using a mask in a channel portion of these predetermined transistors. A mask structure of a semiconductor memory device for writing data,
An opening 4 for writing data is formed in an interlayer insulating film 4 formed on the entire surface so as to cover the transistor 12.
B is provided, and the cross-sectional shape of the opening 4B is formed large on the surface 11 side of the substrate 1 and small on the gate 3.

Further, in the mask structure of the semiconductor device of this embodiment, a plurality of MOS transistors are arranged on a substrate,
A method for manufacturing a semiconductor memory device in which data is written by selectively performing ion implantation using a mask in a channel portion of these predetermined transistors, and is formed over the entire surface so as to cover the transistor 12. An opening 4B for writing data is provided in the interlayer insulating film 4, and a cross-sectional shape of the opening 4B is formed large on the surface 11 side of the substrate 1 and is etched small on the gate 3. And a second step of performing ion implantation through the opening 4B formed in the first step.

(Fifth Specific Example) The specific example of FIG. 5 is an example in which the cross section of the opening is formed in an inverted triangular shape.
Is a cross-sectional view showing the structure.

Therefore, in the mask structure of the semiconductor memory device of this embodiment, a plurality of MOS transistors are arranged on a substrate, and ion implantation is selectively performed using a mask in a channel portion of these predetermined transistors. In the mask structure of the semiconductor memory device in which data is written by the method, an opening 4A for writing data is provided in the interlayer insulating film 4 formed on the entire surface so as to cover the transistor 12; The cross-sectional shape of the portion 4A is
It is characterized in that it is formed large on the surface 11 side of the substrate 1 and is formed in an inverted triangular shape in which no opening is formed on the gate 3.

Further, in the method of manufacturing a semiconductor memory device according to this embodiment, a plurality of MOS transistors are arranged on a substrate, and selective ion implantation is performed using a mask in a channel portion of these predetermined transistors. In the method for manufacturing a semiconductor memory device in which data is written by the method described above, an opening 4A for writing data is formed in the interlayer insulating film 4 formed on the entire surface so as to cover the transistor 12.
And the cross-sectional shape of the opening 4A is
A first step of forming a large triangle on the front surface 11 side and etching the gate 3 in an inverted triangular shape without forming an opening, and a second step of performing ion implantation through the opening 4A formed in the first step. And a step of:

[0043]

As described above, the mask structure of the semiconductor memory device and the method of manufacturing the semiconductor memory device according to the present invention are configured as described above. Suppresses the spread of ions in the horizontal direction near the projection range of the target, enabling the control of the threshold voltage of only the desired data write bit without affecting the threshold voltage of the adjacent bit became.

When the data write mask is a photoresist film, the resist opening becomes considerably larger than the target due to the optical proximity effect in the area where the write data is dense, and the resist separating the openings becomes thin. Even in this case, by forming the cross-sectional shape of the opening into an inverted triangle or a trapezoidal trapezoid, a shape in which the mask spreads toward the bottom of the opening can be obtained, thereby improving the adhesion with the base, and thereby, the resist pattern collapse Disappeared, and the yield improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a first specific example of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of a first specific example.

FIG. 3 is a diagram showing an effect of the first specific example.

FIG. 4 is a sectional view showing a structure of a second specific example of the present invention.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a second specific example.

FIG. 6 is a diagram showing a structure of a third specific example.

FIG. 7 is a sectional view showing a structure of a fourth specific example of the present invention.

FIG. 8 is a sectional view showing a manufacturing process of a fourth specific example.

FIG. 9 is a diagram showing a structure of a fifth specific example.

FIG. 10 is a cross-sectional view showing a structure of a conventional technique.

FIG. 11 is a cross-sectional view showing a conventional manufacturing process.

FIG. 12 is a diagram showing a problem of the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 Gate oxide film 3 Gate electrode 4 Interlayer insulating film 4A, 4B Opening 5 Second resist film 6 First resist film 6A, 6B Opening 11 Surface 12 Transistor 21 Inverted triangle T taper

Claims (11)

[Claims] 1. A mask of a semiconductor memory device in which a plurality of MOS transistors are arranged on a substrate, and data is written by selectively performing ion implantation using a resist mask in channel portions of these predetermined transistors. A mask structure for a semiconductor memory device, wherein a cross-sectional shape of an opening of the resist mask for writing data has a taper. 2. A mask for a semiconductor memory device in which a plurality of MOS transistors are arranged on a substrate, and data is written by selectively performing ion implantation using a resist mask in a channel portion of these predetermined transistors. A cross-sectional shape of the opening of the resist mask for writing data, which is formed to be large on the surface side of the substrate and formed in an inverted triangular shape in which no opening is formed on the transistor side. Mask structure of a semiconductor memory device. 3. A mask for a semiconductor memory device in which a plurality of MOS transistors are arranged on a substrate, and data is written by selectively performing ion implantation using a resist mask in a channel portion of these predetermined transistors. A mask structure for a semiconductor memory device, wherein a cross-sectional shape of an opening of the resist mask for writing data is formed larger on a surface side of a substrate and smaller on a transistor side. 4. A mask structure of a semiconductor memory device in which a plurality of MOS transistors are arranged on a substrate and data is written by selectively performing ion implantation using a mask in a channel portion of these predetermined transistors. An opening for writing data is provided in an interlayer insulating film formed on the entire surface so as to cover the transistor, and a cross-sectional shape of the opening is formed large on the front surface side of the substrate. A mask structure of a semiconductor memory device, which is formed small on a gate. 5. A mask structure of a semiconductor memory device in which a plurality of MOS transistors are arranged on a substrate and data is written by selectively performing ion implantation using a mask in a channel portion of these predetermined transistors. An opening for writing data is provided in an interlayer insulating film formed on the entire surface so as to cover the transistor, and a cross-sectional shape of the opening is formed large on the front surface side of the substrate. A mask structure for a semiconductor memory device, wherein the mask structure is formed in an inverted triangular shape in which no opening is formed on a gate. 6. A semiconductor memory device in which a plurality of MOS transistors are arranged on a substrate, and data is written by selectively performing ion implantation using a resist mask in a channel portion of these predetermined transistors. A first step of forming a cross-sectional shape of an opening of the resist mask for writing data into a larger shape on the front surface side of the substrate and processing it into an inverted triangular shape without forming an opening on the transistor side. And a second step of performing ion implantation through the opening formed in the first step. A method of manufacturing a semiconductor memory device, comprising: 7. A semiconductor memory device in which a plurality of MOS transistors are arranged on a substrate, and data is written by selectively performing ion implantation using a resist mask in a channel portion of these predetermined transistors. A method of forming a cross-sectional shape of an opening of the resist mask for writing data on the front surface side of the substrate to be large and making it small on the transistor side; A second step of implanting ions through the formed opening. A method of manufacturing a semiconductor memory device, comprising: 8. The method according to claim 6, wherein in the first step, an opening is formed in the resist mask by etching. 9. The method according to claim 6, wherein, in the first step, the resist mask is processed by an electron beam direct writing method. 10. A method of manufacturing a semiconductor memory device in which a plurality of MOS transistors are arranged on a substrate, and data is written by selectively performing ion implantation using a mask in a channel portion of these predetermined transistors. An opening for writing data is provided in an interlayer insulating film formed on the entire surface so as to cover the transistor, and a cross-sectional shape of the opening is formed large on the front surface side of the substrate. A first step of etching into an inverted triangular shape without forming an opening on the gate; and a second step of performing ion implantation through the opening formed in the first step. A method for manufacturing a semiconductor storage device. 11. A method for manufacturing a semiconductor memory device in which a plurality of MOS transistors are arranged on a substrate, and data is written by selectively performing ion implantation using a mask in a channel portion of these predetermined transistors. An opening for writing data is provided in an interlayer insulating film formed on the entire surface so as to cover the transistor, and a cross-sectional shape of the opening is formed large on the front surface side of the substrate. A first step of etching so as to be formed on the gate to be small, and a second step of performing ion implantation through the opening formed in the first step. Production method.