JPH06268178A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable sure impurity implantation and control of threshold value even if a depth from a surface of an upper layer film to a set region varies by setting ion implantation energy to position a concentration peak of impurities below a set region of a semiconductor substrate whereto impurities of a semiconductor substrate is to be introduced. CONSTITUTION:A gate oxide film 12 and a field oxide film 13 are formed in a p-type silicon substrate 11. After polysilicon is deposited, gate electrodes 14a to 14c, etc., are formed by patterning. Then, arsenic As of n-type impurities is implanted to form an impurity diffusion region 15 by using the gate electrode, etc., as a mask. A first layer insulation film 16 and a second layer insulation film 18 are formed as an upper layer film. Boron B of p-type impurities is implanted using resist 19 applied to the second layer insulation film 18 as a mask. This ion implantation is performed under the conditions that a concentration peak of impurities is located below a region of the silicon substrate 11 whereto impurities are introduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to improving threshold control of a memory cell transistor of a semiconductor memory such as a mask ROM.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor device of this type, a mask ROM capable of programming information data storage by a mask used in an LSI chip manufacturing process can be mentioned. FIG. 4 is a cross-sectional view of a main part of the mask ROM, and particularly shows a state in which ion implantation for threshold control is performed in the channel region of the memory cell transistor. In the method of manufacturing the mask ROM shown in FIG. 4, first, the gate oxide film 2 and the field oxide film 3 are formed on the p-type silicon substrate 1. Then, gate electrodes 4a, 4b, 4c made of polysilicon are formed, and a first interlayer insulating film 6, an Al wiring 7, and a second interlayer insulating film 8 are sequentially formed. Next, the resist 9 is patterned according to a program so that the opening formed in the resist 9 is located above an active region forming a channel of a predetermined transistor. Then, p-type impurities such as boron (B) are ion-implanted with an implantation energy such that a concentration peak is on the surface of the silicon base surface, and the threshold voltage of the transistor is changed to write data. That is, with such a method, the memory cell transistor becomes an enhancement type or a depletion type, and becomes "0" or "1" of information. As for the writing method of such a mask ROM, for example, “Monthly Nikkei Micro Device, 19
It is published in the December 91 issue, pp. 104-109.
The content of the method is that after forming the first layer wiring, data is written by selectively performing ion implantation in the active layer region immediately below the gate of the memory cell transistor and changing the threshold voltage of the transistor. is there. In this way, in order to position the ion implantation step at an intermediate step of the chip manufacturing process, it is necessary to provide a TAT (time until a product is supplied from a semiconductor producer to a user: Turn Aro).
und Time) has the advantage that it does not become long.

[0003]

The above-mentioned conventional method is excellent in that the TAT is shortened, but the controllability of the threshold value of the transistor is affected by the variation in the film thickness of the gate electrode of the transistor and the interlayer insulating layer. There is a problem that becomes worse. That is, as shown in FIG. 4, for example, in the active region near the surface of the silicon substrate 1 immediately below the gate electrode 4a,
The impurity region a is formed at an appropriate position, but at the portion of the gate electrode 4c where the film thickness of the interlayer insulating film is large, the concentration of the implanted impurities has a peak in the impurity region b in the gate electrode 4c, and the silicon substrate below the impurity region a. Impurities may not reach 1. Therefore, there is a problem that some transistors have an uncontrolled threshold value and program information is erroneous. The graph shown in FIG. 2 shows a profile of the impurity concentration with respect to the substrate depth when ions are implanted.
In the above-mentioned conventional method, the ion implantation is performed so that the vicinity of the surface of the silicon substrate immediately below the gate electrode has the peak of the impurity concentration (the range indicated by A in FIG. 2). Therefore, if the depth from the surface of the interlayer insulating film to the vicinity of the surface of the silicon substrate becomes long due to the variation in the film thickness of the interlayer insulating film or the gate electrode, the impurity concentration as shown in FIG. Cannot reach the silicon substrate, and the above-mentioned problems occur.

The problem to be solved by the present invention is TA
The point is what kind of means should be taken to realize a method for manufacturing a semiconductor device in which T is short and the controllability of the threshold voltage of the transistor is high.

[0005]

The invention according to claim 1 of the present application is a set region in which an impurity is to be introduced into a semiconductor substrate by forming an upper layer film and then forming a mask pattern. In a method of manufacturing a semiconductor device including a step of implanting ions into a semiconductor device, the implantation energy of the ion implantation is set so that a concentration peak of an impurity implanted in the semiconductor substrate is located below the set region. , As a solution.

In the invention according to claim 1 of this application, after forming an upper layer film on a semiconductor substrate, a mask pattern is formed and ions are implanted into a set region in the semiconductor substrate to which impurities are to be introduced. In the method for manufacturing a semiconductor device including a step, the ion implantation step is performed with an implantation energy such that an impurity concentration peak is located below the formation region, and an impurity is implanted in an intermediate portion of the set region. The solution is to carry out a plurality of ion implantations, including an ion implantation performed with an implantation energy such that the concentration peak is located.

[0007]

In the invention according to claim 1 of this application, the implantation energy of the ion implantation is set such that the impurity concentration peak is located below the set region of the semiconductor substrate into which the impurities are to be introduced. For this reason, even if the depth from the surface of the upper layer film to the set region of the semiconductor substrate where the impurities are to be introduced is shallow due to variations in the upper layer film, the impurities are surely implanted and the threshold value control can be performed. That is,
On the left side (shallow direction) of the peak portion in the graph of FIG. 2, the gradient of the concentration is gentler than on the right side (deep direction) of the peak portion, and therefore, for example, the concentration is in the range shown by B in FIG. can do. On the other hand, when the depth to the set region of the silicon substrate becomes deep due to the variation of the upper layer film (when the upper layer film is thick), the depth to the impurity concentration peak is set to be deep, and therefore, for example, as shown in FIG.
The density can be set within the range indicated by A in the middle. In this case also, ion implantation with a sufficient concentration is performed.

As described above with reference to FIG. 2, when the range A of the concentration peak portion is aimed at the set region, when the upper layer film is thicker than the set concentration, the concentration is sharply increased with respect to the peak. Change (ΔN _A ), but if the concentration peak is set to be below the setting area, the concentration change (ΔN _B ) on the left side (shallow direction) of the peak in the figure will be in the gentle range B. Therefore, appropriate ion implantation can be performed even if the upper layer film is thick. Therefore, when the present invention is applied to the mask ROM, the threshold voltage of the transistor can be surely controlled after the upper layer film is formed, and the TAT can be shortened.

Further, in the invention according to claim 2 of this application, a plurality of ion implantations having different implantation energies are performed so that the depths of the impurity rich peaks are different. The depth of the concentration peak includes at least two ion implantations having peaks below and in the middle of the set region of the substrate. For this reason, as shown in FIG. 3, the portion connecting the concentration peaks of the respective ion implantations has a gentle gradient concentration change (ΔN _c ), and the margin for the depth variation increases. Therefore, even if the thickness of the upper layer film varies, the impurities can be surely and appropriately introduced into the set region.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the method for manufacturing a semiconductor device according to the present invention will be described below with reference to the embodiments shown in the drawings. This embodiment is an example in which the present invention is applied to a method for manufacturing a mask ROM.

First, in this embodiment, as shown in FIG. 1A, a gate oxide film 12 and a field oxide film 13 are formed on a p-type silicon substrate 11 by a known method. In addition,
The thickness of the gate oxide film 12 was 10 nm. Then, after depositing polysilicon, patterning is performed to form gate electrodes 14a, 14b, 14c and the like according to the design of the memory cell. The thickness of this gate electrode was set to 200 nm. Then, using the gate electrode or the like as a mask, ion implantation is performed using, for example, arsenic (As) as an n-type impurity to form n-type impurity diffusion regions 15 to 15. This embodiment has a structure in which transistors are connected in series.

Next, as shown in FIG. 1B, for example, B
The first interlayer insulating film 16 made of PSG is formed by the CVD method at 40
Deposit to a film thickness setting of 0 nm. After that, a film made of Al is formed on the first interlayer insulating film 16 by, for example, a sputtering method, and then an Al wiring 17 as shown in FIG. 1C is patterned by using a photolithography technique and an etching technique. The thickness of the Al wiring 17 is 500 nm.
Set to.

Then, as shown in FIG. 1D, a second interlayer insulating film 18 is formed on the entire surface with tetraethoxysilane (TEO).
It is formed to a thickness of 400 nm by the CVD method using S). Thus, when the first interlayer insulating film 16 and the second interlayer insulating film 18 are formed as the upper layer film, Al
These film thicknesses vary depending on the location due to the influence of wiring steps and various conditions. Further, the film thickness of the gate electrode also varies.

Therefore, the threshold control step is performed by the method described below.

That is, the resist 1 is formed on the second interlayer insulating film 18.
After coating 9, the photolithography process for opening the resist 19 above the channel region of the transistor whose threshold is to be controlled is performed according to the program. Resist 19 patterned in this way
Is processed into the structure shown in FIG. 1D to serve as an ion implantation mask.

Then, using the resist 19 as a mask, boron (B) which is a p-type impurity is ion-implanted.
This ion implantation is performed under the condition that the peak of the impurity concentration is located below the formation region of the silicon substrate 11 into which the impurities are to be introduced (the region in which the impurities must be introduced to control the threshold value). Specifically, the first and second layers as the upper layer film
Implantation of 330 KeV such that the concentration peak is at a position several nm to several tens nm deeper than the depth obtained by adding a depth dimension of about 10 nm from the surface of the silicon substrate 11 to the thickness dimension of the two layers of the interlayer insulating films 16 and 18. Energy was used. When the ion implantation is performed under such conditions, the concentration is about 3XE1.
Became 4.

By performing ion implantation under such conditions, as shown in FIG. 1D, the channel region of the transistor having the gate electrode 14c with a thick upper layer film can also have an appropriate impurity concentration. In FIG. 1D, a,
b indicates a region into which impurities are introduced. In this way, even if the film thickness of the upper layer film varied, the threshold control of the transistor could be reliably performed.

Further, in this embodiment, there is one type of ion implantation for threshold control, but if two or more types of ion implantations with different implantation energies of impurities of the same conductivity type are carried out, a higher impurity concentration can be obtained. Can be uniform. In this method, the implantation energy is set so that the concentration peak is located below the formation region where impurities should be introduced by one ion implantation, and the implantation energy is set so that the concentration peak is located inside the formation region by another ion implantation. Should be set. Therefore, as shown in FIG. 3, the range C has a substantially uniform density,
Even if there is some variation in depth, an appropriate impurity concentration can be obtained. In the structure shown in the above embodiment, at least ion implantation of 330 KeV and ion implantation of 280 KeV may be performed.

Although the embodiment has been described above, the present invention is not limited to this, and various design changes can be made. Further, the above-described embodiment is a mask ROM according to the present invention.
However, the present invention can be applied to the manufacturing of other semiconductor devices.

[0020]

As is apparent from the above description, according to the inventions described in claims 1 and 2 of the present application, even if the film thickness of the upper layer film on the semiconductor substrate varies, it is appropriate in the substrate. There is an effect that ion implantation can be performed.

In particular, if the present invention is applied to the manufacture of a mask ROM, even if there is a variation in the film thickness of the gate electrode of the transistor or the interlayer insulating film, the variation in the characteristics (threshold voltage) of the programmed transistor is minimized. To the limit, and T
This has the effect of shortening the AT.

[Brief description of drawings]

1A to 1D are process sectional views showing an embodiment of the present invention.

FIG. 2 is a graph showing a relationship between a depth and an impurity concentration in ion implantation into a substrate.

FIG. 3 is a graph showing the relationship between the implantation depth and the impurity concentration when ion implantation with different implantation energies is performed.

FIG. 4 is a sectional view of a conventional example.

[Explanation of symbols]

 11 ... Silicon substrate 14a, 14b, 14c ... Gate electrode 16 ... First interlayer insulating film 18 ... Second interlayer insulating film 19 ... Resist

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device, comprising the steps of forming an upper layer film on a semiconductor substrate, forming a mask pattern, and implanting ions into a set region in the semiconductor substrate where impurities should be introduced. A method for manufacturing a semiconductor device, characterized in that the implantation energy of ion implantation is set so that a concentration peak of an impurity implanted in the semiconductor substrate is located below the set region. 2. A method of manufacturing a semiconductor device, comprising the steps of forming an upper layer film on a semiconductor substrate, forming a mask pattern, and ion-implanting into a set region in the semiconductor substrate where impurities should be introduced. In the ion implantation step, ion implantation is performed with an implantation energy such that an impurity concentration peak is located below the formation region, and ion implantation is performed with an implantation energy such that an impurity concentration peak is located in an intermediate portion of the set region. A method for manufacturing a semiconductor device, which comprises performing a plurality of ion implantations including implantation.