JP2001034455A - Adding device, subtracting device, multiplying device and dividing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the configuration of various arithmetic units performing addition and subtraction of two numbers undergoing bias representation by inverting the most significant bit of 2nd data and outputting n-bit operation results obtained by adding 1 to the sum of the data and 1st data as addition result data. SOLUTION: Addition processing of 1st data e1 and 2nd data e2 which are subjected to bias representation obtained by adding a bias value 127 (=27-1) to 8-bit data represented by 2 complement format is performed, and 8-bit addition result data e3 undergoing bias representation is outputted. This adding device 10 consists of an inverting circuit 12 which inverts and outputs only the most significant bit of the data e2 and an 8-bit adder 14 which adds the data e1 to data outputted by the circuit 12 and inputs the data e1 added to the data. Then, the data e3 undergoing bias representation is obtained by adding 1 to the sum of a value obtained by inverting the most significant bit of the data e2 and the data e1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adder and a subtractor for obtaining a sum or difference of bias-expressed binary values, a multiplication device for obtaining a product or quotient of binary values expressed in a floating-point notation format, and a division. Related to the device.

[0002]

2. Description of the Related Art Conventionally, as a method of expressing a numerical value in a floating-point format, a method defined by the IEEE-745 standard (hereinafter referred to as a "standard format") is known. FIG. 7 shows the format of this standard format. As shown in the figure, the standard format includes a single-precision floating-point format in which a numerical value is represented by 32 bits and a double-precision floating-point format in which a numerical value is represented by 64-bits. 7 (a), 1 bit is assigned to the sign part s, 8 bits to the exponent part e, and 23 bits to the mantissa part f. On the other hand, in the double precision floating point format (see FIG. 7 (b)). , One bit is allocated to the sign part s, 11 bits are allocated to the exponent part e, and 52 bits are allocated to the mantissa part f.

[0003] Incidentally, since the concept is completely the same in each format only in the bit width of each part between single precision and double precision, in the following, specific examples will be described unless otherwise specified. Use single precision floating point format. The sign part s is defined so that a positive sign is represented by 0 and a negative sign is represented by 1.

The exponent part e uses a bias-expressed value obtained by adding a bias value 127 (01111111B) to an integer value expressed in a two's complement format, thereby obtaining -126.
Integer values in the range of +127 to consecutive positive integers 1-2
54 (00000001B to 11111110B). However, 00000000B and 11111111B
Is excluded from the range of the above numerical values in order to represent a special state such as infinity, not-a-number, and denormalized number described later.

The bias value is represented by 2 ⁿ -1 -1 when the number of bits of the exponent part e is n. Therefore, in double precision, the bias value is 1023 (0111111111).
11B), and is defined to treat integers in the range of −1022 to +1022 as continuous integer values (00000000001B to 11111111110B).

On the other hand, if the exponent part e is a value expressed in the bias expression (00000001B to 11111110B), the mantissa part f has 23 bits after the decimal point when the numerical value is expressed in the form of 1.XXX. When the exponent part e is 00000000B, the value is expressed as 0.XX
It is defined to represent a value of 23 bits below the decimal point when represented in the format X... X. The numerical value represented in the former case is called a normalized number, and the numerical value represented in the latter case is called a denormalized number.

That is, the data expressed in the floating-point format (at the time of normalization) is (-1) ^s × 1.
f × 2 ^e−127 , and in the case of double precision, (−1) ^s × 1. f
× 2 ^{e− 1023} . By the way, when performing multiplication / division of two numbers expressed in a floating-point format, it is necessary to perform addition / subtraction for the exponent part of the multiplicand data and the multiplier data.

The exponent part of the multiplicand data expressed as bias (hereinafter referred to as "first data") is e1, and the exponent part of the multiplier data (hereinafter referred to as "second data") is e2 and e.
Data (hereinafter, “real first data” and “real second data”) in which 1,1 and e2 are represented by 2's complements are E1 and E2, and furthermore, an added value of E1 and E2 (hereinafter “real addition result data”)
E3, and the subtraction value of E1 and E2 (hereinafter, referred to as "actual subtraction result data") is E4, and the data expressing the bias of E4, E3, and E4 (hereinafter, referred to as "addition result data" and "subtraction result data") are e3. Assuming e4, the following (1) to
Equation (6) holds.

E1 [7: 0] = E1 [7: 0] +01111111 (1) e2 [7: 0] = E2 [7: 0] +01111111 (2) e3 [7: 0] = E3 [7: 0] +01111111 (3) e4 [7: 0] = E4 [7: 0] +01111111 (4) E3 [7: 0] = E1 [7: 0] + E2 [7: 0] (5) E4 [7: 0] = E1 [7: 0] -E2 [7: 0] (6) Here, X [i] represents the value of the i-th bit of the data X expressed in binary, and X [i: j] is The values from the i-th bit to the j-th bit are represented.

Here, when equation (5) is substituted into equation (3), equation (7) is obtained. When equation (1) and (2) are further transformed and substituted into equation (7), equation (8) is obtained. Is obtained. e3 [7: 0] = (E1 [7: 0] + E2 [7: 0]) + 01111111 (7) = e1 [7: 0] + e2 [7: 0] −01111111 (8) Therefore, expressed in floating point format When the multiplication of two numbers is performed, one addition and one subtraction are required in the operation for the exponent part e. In order to realize such an arithmetic processing, for example, as shown in FIG.
Adder 102 for adding data e1 and second data e2
And a subtractor 104 for subtracting the bias value from the output of the adder 102, or a subtractor 106 for subtracting the bias value from the second data e2, as shown in FIG. It was necessary to provide an adder 108 for adding the output of the subtractor 106 to one data e1.

On the other hand, if equation (6) is substituted into equation (4), equation (9) is obtained. If equation (1) and (2) are further transformed and substituted into equation (9), equation (10) becomes can get. e4 [7: 0] = (E1 [7: 0] −E2 [7: 0]) + 01111111 (9) = e1 [7: 0] −e2 [7: 0] +01111111 (10) Therefore, in floating point format In the case of performing the division by two expressed, one subtraction and one addition are required for the operation on the exponent part e. In order to realize such an arithmetic processing, for example, as shown in FIG.
Subtractor 112 for subtracting second data e2 from data e1
And an adder 114 for adding a bias value to the output of the subtractor 112, or a subtractor 116 for subtracting the bias value from the second data e2, as shown in FIG. It was necessary to provide a subtractor 118 for subtracting the output of the subtractor 116 from one data e1.

[0012]

That is, the exponent part (first and second data) e of the numerical value represented in the floating point format
1 and e2, to which bias values have been added, it is not possible to obtain correct results (addition result data e3 and subtraction result data e4) by simply performing addition and subtraction, and to add or subtract by addition and subtraction. Calculators 104, 106, 114, 116 for compensating for the bias value
However, there is a problem that the calculation time and the circuit scale are increased separately.

On the other hand, Japanese Patent Application Laid-Open No. Hei 5-27949 discloses an argument (1,000,000) in which 1 is added in advance to the sum of numerical values represented by bias, and 1 is added to the bias value later.
A device for subtraction in B) is disclosed. In this case, since the operation for compensating the bias value need only be performed using the upper bits whose argument is 1, the configuration of the device can be simplified.

However, in this circuit configuration, if the number of bits is extended to the most significant side to detect an overflow or an underflow, the argument must be extended accordingly. For example, as shown in FIG. 10, in the case where two bits are extended, an arithmetic unit K2 for performing addition and subtraction of three bits is required to compensate for a bias value, which hinders miniaturization of the device.

The present invention has been made in order to solve the above problems.
It is an object of the present invention to simplify the configuration of various arithmetic devices that perform addition and subtraction of two numbers represented by a bias.

[0016]

Here, the addition of the binary values (the first data e1 and the second data e2) represented by the bias is considered based on the above equations (1) to (6). First, when a bias value is added to both sides of equation (5), (11)
Equation (12) is obtained by transforming equations (1) and (3) into equation (11).

E3 [7: 0] + 01111111 = E1 [7: 0] + E2 [7: 0] +01111111 (11) e3 [7: 0] = e1 [7: 0] + E2 [7: 0] (12) On the other hand , (2) is modified to obtain expression (13), and by expressing the bias value using two's complement, expression (14) is obtained. Further, the bias value expressed using the two's complement is separated into 10000000B and 1B, and the most significant bit e2 [7] of the second data e2 and the other bits e2
Equation (15) is obtained by rearranging the equations separately from [6: 0]. Here, ~ X is a negative value of X, and {X, Y} represents a connection between X (upper bit) and Y (lower bit).

E2 [7: 0] = e2 [7: 0] -01111111 (13) = e2 [7: 0] +10000001 (14) = e2 [7: 0] + 10000000 + 1 = ｛(e2 [7] +1), (E2 [6: 0] +0000000)｝ + 1 = ｛｛e2 [7], e2 [6: 0]｝ + 1 (15) Then, if the expression (15) is substituted into the expression (12), (1)
Equation 6) is obtained.

E3 [7: 0] = e1 [7: 0] + ｛~ e2 [7], e2 [6: 0]｝ + 1 (16) That is, as is apparent from the equation (16), the bias expression is performed. From the first and second data e1 and e2, it is sufficient to add 1 to the sum of the value obtained by inverting the most significant bit of the second data and the first data in order to obtain the addition result data e3 represented by the bias. is there.

Therefore, in the adder according to the first aspect, inverting means for outputting n-bit data obtained by inverting the most significant bit of the second data, and the sum of the data output by the inverting means and the first data. And an addition increment means for outputting an n-bit operation result obtained by adding 1 to the result data as addition result data, thereby realizing the operation process corresponding to the above equation (16).

In particular, the adding increment means is, for example,
As described above, if the operation on both least significant bits of a pair of data to be added is performed using a full adder in which the carry input is fixed to 1, in order to add 1, 1 There is no need to provide a special configuration.

That is, according to the adder of the present invention, in addition to the adder for adding two numbers represented in two's complement format,
With a very simple configuration of providing an inverting means for inverting one bit, it is possible to realize an addition process of two numbers expressed in bias. For example, the addition increment means performs an operation on both least significant bits of a pair of data to be added and a first logical operation for obtaining an exclusive NOR of these two least significant bits. Means and a second logical operation means for calculating the logical sum of both least significant bits. In this case, the output of the first logical operation means is used as the least significant bit of the addition result data. , The output of the second logical operation means may be a carry to the upper bits.

In other words, the logical value table of the full adder in which the carry input is fixed at 1 is as shown in FIG. 6 (b). Instead, it can be realized with such a simple configuration. Next, in the adder according to the fourth aspect, unlike the adder according to the first aspect, the output of the inversion means and the first data are not directly input to the addition increment means, but the first expansion means. The n + 2 bit data obtained by extending the most significant bit side of the first data by 2 bits 0 and the n + 2 bit data obtained by extending the n bit data output from the inverting means by 2 bit sign by the second extending means are It is configured to be input to the addition increment means.

In the adder of the present invention configured as described above, since the inversion process is performed before the bit width is expanded, the configuration for performing the process of compensating for the bias value is different from the conventional device. Thus, the device does not increase in accordance with the expanded bit width, and the apparatus can be made compact regardless of whether the bit width is expanded.

The sign extension means that a bit having the same value as the most significant bit is added to the most significant bit of the data, and the 0 extension means that the value is added to the most significant bit of the data. This means adding a bit of 0 '. The reason why the first expanding means extends the data to 0 is that the first and second data represented by the bias are 000000 as described above.
This is because the first data supplied to the first expanding means without any processing is always a positive number, since it is treated as an unsigned number in the range of 01B to 11111110B.

On the other hand, the reason why the sign is extended by the second extension means is that the data supplied to the second extension means has been subjected to a process of inverting the most significant bit, that is, the most significant bit. Inverting the bits here corresponds to subtracting a number that is one greater than the bias value. Therefore, the data supplied to the second expanding means is converted into signed data which is smaller by 1 than the actual second data which is not expressed in a bias, and may be either a positive number or a negative number. is there.

The addition incrementing means uses data processing of n + 2 bits instead of n bits. Of the n + 2 bits operation results of the addition incrementing means, the lower n bits are output as addition result data. , The upper two bits are output as exception determination data for determining overflow or underflow of the addition result data.

The upper bits of the exception determination data represent the sign of the addition result data expressed in a biased manner, and the lower bits represent the presence or absence of a carry to the (n + 1) th bit when the addition result data is a positive number. I have. That is, when the output data of n + 2 bits from the addition increment means is a negative number, an underflow occurs, and when the output data of the n + 2 bits is a positive number and carries to the (n + 1) th bit, an overflow occurs. Can be determined.

Therefore, for example, as described in claim 5,
If the third logical operation means for calculating the logical product of the inverted value of the upper bit of the exception determination data and the lower bit is provided, the output of the third logical operation means can be used to determine that the addition result data overflows. The upper bit of the exception determination data can be used as it is as an underflow exception signal indicating that the addition result data underflows.

The configuration of the addition increment means disclosed in claims 2 and 3 may be applied to the addition device according to claim 4 or 5. Next, the biased expression 2
Consider subtraction of values (first data e1 and second data e2).

First, when a bias value is added to both sides of the equation (6), the equation (17) is obtained, and the equation (17) is added to the equation (17).
By transforming equation (4) and substituting, equation (18) is obtained. E4 [7: 0] + 01111111 = E1 [7: 0] −E2 [7: 0] +01111111 (17) e4 [7: 0] = e1 [7: 0] −E2 [7: 0] (18) By transforming equation (2), equation (19) is obtained.
The expression (20) is obtained by expressing the data e2 [7: 0] in a two's complement format and rearranging the expression.
By rearranging the expression by separating the most significant bit e2 [7] of the data e2 from the other bits e2 [6: 0], the expression (21) is obtained.

-E2 [7: 0] =-e2 [7: 0] +01111111 (19) = (~ e2 [7: 0] +1) + 01111111 = ~ e2 [7: 0] +10000000 (20) = ｛(~ e2 [7] +1), (~ e2 [6: 0] +0000000)} = {e2 [7], ~ e2 [6: 0]} (21) Then, substitute equation (21) into equation (18). If (2
Equation 2) is obtained.

E4 [7: 0] = e1 [7: 0] + {e2 [7], ~ e2 [6: 0]} (22) In other words, as is clear from the equation (22), the bias expression is performed. To obtain the subtraction result data e4 expressed in a bias form from the first and second data e1 and e2, the second data e
A value obtained by inverting the bits other than the most significant bit of 2 (subtraction data);
What is necessary is just to obtain the sum with the first data e1 (subtracted data).

Therefore, in the subtraction device according to the present invention, the inversion means for outputting n-bit data obtained by inverting other than the most significant bit of the subtraction data, and the data output by the inversion means and the subtracted data are used. By providing an addition means for outputting an n-bit operation result of the addition as subtraction result data, an operation process corresponding to the above equation (22) is realized.

That is, according to the subtraction apparatus of the present invention, in addition to the adder for adding two numbers expressed in two's complement format, inverting means for inverting n-1 bits other than the most significant bit of the subtraction data With the extremely simple configuration of providing the above, it is possible to realize a subtraction process of two numbers in a bias expression.

The adder according to any one of claims 1 to 5 is, for example, as follows.
Multiplicand data and multiplier data expressed in a floating-point format including a mantissa represented by a binary number represented by an absolute value, an exponent represented by a binary number represented by a bias, and a sign representing the sign of the mantissa. Can be suitably used as a device for calculating the sum of both exponents of multiplicand data and multiplier data.

According to a sixth aspect of the present invention, there is provided a subtraction apparatus for calculating a quotient of dividend data and divisor data also expressed in a floating-point format. It can be suitably used as a device for determining the difference between both exponents of data.

[0038]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a block diagram of an 8 expressed in 2's complement format.
In the bit data, the bias value 127 (= 2 ⁷ -1 = 01)
111111B) is a configuration diagram of the adder of the first embodiment that performs an addition process on the first data e1 and the second data e2 represented by the bias, and outputs 8-bit addition result data e3 represented by the bias. It is. Also, FIG.
FIG. 2 is a block diagram illustrating a schematic configuration of a multiplication device to which a product of a pair of input data D1 and D2 expressed in a single precision floating point format is applied, to which the addition device according to the embodiment is applied.

As shown in FIG. 2, the multiplication device MUL obtains the output data Do by calculating the exclusive OR of the input data D1 and D2 based on the sign sections s1 and s2 of the input data D1 and D2.
A code operation unit M1 for obtaining the sign of
An exponent addition unit M2 for obtaining an addition value of both based on exponent parts e1 and e2 of D2, and a mantissa multiplication unit M3 for obtaining a multiplication value of both based on mantissa parts f1 and f2 of both input data D1 and D2. ing.

The multiplication device MUL further includes a mantissa normalizing section M4 for shifting the multiplication result f3 in the mantissa multiplying section M3 so as to have a normalized form of "1.XXX ... X", and a mantissa normalizing section M4. The multiplication result f3 ′ normalized in M4 is subjected to a rounding process (any of rounding / rounding down / rounding up) for a portion (from the 24th digit after the decimal point) protruding from the number of bits allocated to the mantissa. If, as a result of the rounding process, a carry of an integer part occurs, the multiplication result is shifted by mantissa rounding unit M5 for normalization again and normalization in mantissa normalizing unit M4 and mantissa rounding unit M5. An exponent correction unit M6 for increasing or decreasing the addition result e3 in the exponent addition unit M2 by an amount.

Then, the operation result s in the sign operation unit M1
o, addition result data e corrected by the exponent correction unit M6
o and the multiplication result data fo processed by the mantissa normalization unit M4 and the mantissa rounding unit M5 are output to the sign unit s of the output data Do.
o, exponent eo, and mantissa fo.

The exponent adder M2 is composed of the adder 10 of the present embodiment. As shown in FIG. 1A, the adder 10 of the present embodiment includes the second data e2.
Circuit 12 as inverting means for inverting and outputting only the most significant bit (MSB) e2 [7] of the first
Data e1 and data ｛to e2 output by the inversion circuit 12.
[7], e2 [6: 0]}, and an 8-bit adder 14 as an addition incrementing means.

It is to be noted that the 8-bit adder 14 is provided in FIG.
As shown in FIG. 1, the known adder includes eight full adders F0 to F7, and each carry output is connected so as to be a carry input of a full adder that processes the most significant bit.
However, the carry input of the full adder F0 for adding the least significant bit is fixed to 1.

The adder 10 according to the present embodiment having the above-described configuration realizes the operation of the contents expressed by the expressions (16) and (8), and the bias-expressed 8-bit first data is obtained.
From the second data e1 and e2,
It generates and outputs bit addition result data e3.

As described above, according to the adder 10 of the present embodiment, the addition processing of the two numbers (the first and second data e1 and e2) represented by the bias is performed when the carry input is one.
This is realized by merely providing an inverting circuit 12 for inverting the most significant bit of the second data e2, in addition to the 8-bit adder 14 for performing the addition process of the two's complement expressed in two's complement format. , And the multiplication device MUL using the adding device 10 can be miniaturized.

In this embodiment, the 8-bit adder 1
4 is configured using eight full adders F0 to F7, and the carry input of the full adder F0 that performs the operation of the least significant bit is fixed to 1, but as shown in FIG. A circuit for performing the operation of the least significant bit includes an exclusive-NOR (XNOR) circuit L1 as a first logical operation means that outputs 1 when both least significant bits are equal to each other and 1 , An OR (OR) circuit L2 as a second logical operation means for outputting 1 and an XNOR circuit L
The output of 1 may be the least significant bit e3 [0] of the addition result data, and the output of the OR circuit L2 may be the carry output Co to the upper bit.

That is, since the carry input is fixed to 1 in the least significant bit full adder F0, the carry input Ci is removed from the logical value table shown in FIG. 6B.
It is only necessary to realize the operation of the logic value table shown in (b), and therefore, it can be realized with a simple circuit configuration including only the XNOR circuit L1 and the OR circuit L2 as described above. [Second Embodiment] Next, a second embodiment will be described.

FIG. 4 shows that 11-bit data expressed in 2's complement format has a bias value 1023 (= 2 ¹⁰ -1 = 01).
111111111B) and the bias-expressed first
FIG. 11 is a configuration diagram of an adder according to a second embodiment that performs an addition process on data e1 and second data e2 and outputs 11-bit addition result data e3 represented by bias.

As shown in FIG. 4, the adder 20 of this embodiment converts the second data e2 into the most significant bit e2 [1
0] is inverted by 2 bits and the first data e1 is extended to the upper side by 2 bits 0 to generate 13-bit data. The data extending circuit 26 and the second extending means for extending the output data {｛e2 [10], e2 [9: 0]} of the inverting circuit 22 to the upper side by 2 bits to generate 13-bit data. A second data extension circuit 27, a 13-bit adder 24 as an addition incrementing unit that takes both output data from the first and second data extension circuits 26 and 27 as an addition input,
Of the output e3 [12: 0] of the 13-bit adder 24,
The upper two bits e3 [12:11] are used as exception determination data, and the overflow exception signal V
and an exception signal generation circuit 28 for generating an underflow Vu exception signal.

The first data extension circuit 26 is configured to perform a 0 extension by adding a signal having a value of 0, while the second data extension circuit 27 is configured to perform a 0 extension. Most significant bit of output data ~ e2 [1
0] to extend the sign by branching the signal line.

The exception signal generation circuit 28 outputs a negation (NOT) circuit L3 for outputting a negative value of the upper bit e3 [12] of the exception determination data, and outputs the output of the NOT circuit L3 and the lower bit e3 of the exception determination data. [11] is a logical product (AND) circuit L4 that outputs 1 when both are 1; the output of the AND circuit L4 is used as an overflow exception signal Xo;
[12] is directly output as the underflow exception signal Xu. These NOT circuits L3
And the AND circuit L4 correspond to a third logical operation means.

The 11-bit adder 24 has the same configuration as the 8-bit adder 14 of the first embodiment except that the number of bits is increased, and the carry input of the full adder for processing the least significant bit is provided. Is fixed at 1. In the adder 20 of the present embodiment configured as described above, the operation of the contents shown in the expressions (16) and (8) is realized with an 11-bit width, and the first and first bits of the 11-bit expressed in the bias expression are realized. Second
From the data e1 and e2, 11-bit addition result data e3 [10: 0] expressed in a bias is generated and output.

Therefore, according to the adder 20 of the present embodiment, similarly to the first embodiment, the configuration for performing the process of compensating the bias value can be reduced. Also,
In the adder 20 of the present embodiment, based on the exception determination data e3 [12:11] obtained by the first and second data expansion circuits 26 and 27 expanding the data, the exception signal generation circuit 28 An overflow exception signal Xo and an underflow exception signal Xu are generated. Therefore, in various devices configured using the addition device 20 of the present embodiment, the addition result data e3 [10: expressed in a bias based on the exception signals Xo and Xu.
0] can be performed more accurately, and the reliability of the device can be improved.

The adder 20 of the present embodiment, for example, constructs a multiplying device for obtaining the product of a pair of input data expressed in a double-precision floating-point format, and adds the exponent of both input data. It can be suitably used for a component part for performing. Third Embodiment Next, a third embodiment will be described.

[0055] Figure 5 is a 8-bit data represented in two's complement form, the bias value 127 (= 2 ⁷ -1 = 011111
11B), the first data (subtracted data) e1 and the second data (subtracted data) e expressed in a biased manner by adding
2. The subtraction device 3 of the third embodiment that performs the subtraction process of 2 and outputs 8-bit subtraction result data e4 expressed in a biased manner
FIG.

As shown in FIG. 5, the subtraction device 30 of the present embodiment converts the second data e2 into 7 bits other than the most significant bit.
An inverting circuit 32 as an inverting means for inverting and outputting the bit data e2 [6: 0], and the first data e1 and the data {e2 [7], to e2 [6: 0] output by the inverting circuit 32 And an 8-bit adder 34 as addition means using｝ as an addition input.

The 8-bit adder 34 is similar to the 8-bit adder 14 in the first embodiment except that the least significant bit is processed using a half adder without a carry input instead of a full adder. It is configured. The subtraction device 30 of the present embodiment configured as described above realizes the operation of the content shown in the expression (22), and hence the expression (10), and performs bias-expressed 8-bit first and second data e1, Based on e2, bias-expressed 8-bit subtraction result data is generated and output.

As described above, according to the subtraction device 30 of this embodiment, the carry input is fixed to 1 in the subtraction processing of the two numbers (the first and second data e1 and e2) represented by the bias. Since it is realized only by providing an inverting circuit 32 for inverting other than the most significant bit of the second data e2, in addition to the 8-bit adder 34 for performing the addition process of two numbers expressed in the two's complement format, Can be made compact.

The subtraction device 30 of the present embodiment can be suitably used, for example, when configuring a division device for obtaining a quotient of a pair of input data expressed in a single precision floating point format. In addition, the division device, of the multiplication devices shown in FIG.
The mantissa multiplication unit M3 is replaced with an exponent subtraction unit consisting of 0,
It can be easily configured by replacing it with a mantissa division unit that performs division between mantissa parts f1 and f2.

As described above, several embodiments of the present invention have been described. However, the present invention is not limited to the above embodiments, and can be implemented in various modes. For example, in each of the above embodiments, the first and second data e1, e
Although the case where the number of bits of 2 is 8 bits or 11 bits has been described, the present invention is not limited to this, and the first and second data e
The number of bits of 1 and e2 may be any number of bits.

In the above embodiment, the addition method executed by the 8-bit adders 14 and 34 and the 11-bit adder 24 is limited to a specific addition method such as a carry addition method and a carry look-ahead addition method. Instead, any method may be adopted.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of an addition device according to a first embodiment, and a block diagram illustrating details of an 8-bit adder included in the addition device.

FIG. 2 is a block diagram illustrating a schematic configuration of a multiplication device configured using the addition device according to the first embodiment.

FIG. 3 is a circuit diagram showing a modification of a component for processing the least significant bit of an 8-bit adder, and a logical value table showing the circuit operation.

FIG. 4 is an overall configuration diagram of an adding device according to a second embodiment.

FIG. 5 is an overall configuration diagram of a subtraction device according to a third embodiment.

FIG. 6 is a logical value table showing the operation of the full adder, and a logical value table when the carry input of the full adder is fixed to 1;

FIG. 7 is an explanatory diagram showing a standard format of a floating-point format.

FIG. 8 is a circuit diagram illustrating a configuration of a conventional device that performs addition of two numbers represented by a bias.

FIG. 9 is a circuit diagram illustrating a configuration of a conventional device that performs subtraction of two numbers represented by bias.

FIG. 10 is a circuit diagram illustrating a configuration of another conventional device that performs addition of two numbers represented by a bias.

[Explanation of symbols]

10, 20 ... Addition device 12, 22, 32 ... Inversion circuit 14, 24, 34 ... n-bit adder 26, 27 ... Data expansion circuit 28 ... Exception signal generation circuit 30 ... Subtraction device 3
2: Inverting circuit F0 to F7: Full adder L1: XNOR circuit L
2 OR circuit L3 NOT circuit L4 AND circuit M1 sign operation unit M2 exponent addition unit M3 mantissa multiplication unit M4 mantissa normalization unit M5 mantissa rounding unit M6 exponent correction unit MUL multiplication device

Claims (8)

[Claims] 1. A first data which is bias-expressed by adding a pair of binary data represented in a two's complement notation format in which the number of bits is n by a bias value of 2 ^n-1 -1. And a second data, and outputs addition result data obtained by bias-expressing the sum of the pair of binary data, wherein n-bit data obtained by inverting the most significant bit of the second data And an addition incrementing unit that outputs an n-bit operation result obtained by adding 1 to the sum of the data output by the inversion unit and the first data as the addition result data. An addition device, characterized in that: 2. The addition increment means performs an operation on both least significant bits of a pair of data to be added using a full adder whose carry input is fixed to 1. Addition device. 3. The addition increment means includes: first logical operation means for calculating an exclusive NOR of both least significant bits of a pair of data to be added, and both least significant bits; Using the second logical operation means for calculating the logical sum of the data, setting the output of the first logical operation means as the least significant bit of the addition result data, and setting the output of the second logical operation means to the upper bit. The adder according to claim 1, wherein the adder is a carry. 4. A first data which is bias-expressed by adding a pair of binary data expressed in a two's complement notation format in which the number of bits is n by a bias value of 2 ^n-1 -1. And a second data, and outputs addition result data obtained by bias-expressing the sum of the pair of binary data, wherein n-bit data obtained by inverting the most significant bit of the second data Inverting means for outputting n + 2 bit data obtained by extending the most significant bit side of the first data by 2 bits 0, and a 2-bit code for n-bit data output from the inverting means. Second extension means for outputting the extended n + 2 bit data; n + 2 bit data output from the first extension means and n + 2 bit data output from the second extension means as 1 And an addition incrementing means for outputting an (n + 2) -bit operation result obtained by adding the following. Among the operation results of the addition incrementing means, the lower n bits are output as the addition result data, and the upper 2 bits are output as the addition result. An adding device for outputting as exception determination data for determining overflow or underflow of data. 5. The addition device according to claim 4, further comprising: third logical operation means for obtaining a logical product of an inverted value of an upper bit of the exception determination data and a lower bit, wherein the third logical operation means An output is an overflow exception signal indicating that the addition result data has overflown, and an upper bit of the exception determination data is output as an underflow exception signal indicating that the addition result data has underflow. An addition device characterized by the above-mentioned. 6. Subtracted data represented by a bias value by adding a pair of binary data represented in a two's complement notation format having n bits, respectively, with a bias value of 2 ^n-1 -1. And subtraction data, and outputs subtraction result data obtained by bias-expressing the difference between the pair of binary data. The n-bit data obtained by inverting other than the most significant bit of the subtraction data. An inverting means for outputting, and an adding means for outputting, as the subtraction result data, an n-bit operation result obtained by adding the data output by the inverting means and the data to be subtracted. apparatus. 7. A floating-point format represented by a mantissa part represented by a binary number represented by an absolute value, an exponent part represented by a binary number represented by a bias, and a sign part representing the sign of the mantissa. A multiplication device for calculating a product of multiplicand data and multiplier data, wherein a sum of both exponents of the multiplicand data and multiplier data is obtained by the adding device according to any one of claims 1 to 5. . 8. A floating-point format including a mantissa part represented by a binary number represented by an absolute value, an exponent part represented by a binary number represented by a bias, and a sign part representing the sign of the mantissa. A division device for calculating a quotient of dividend data and divisor data, wherein a difference between both exponent parts of the dividend data and divisor data is obtained by the subtraction device according to claim 6.