CN102880445A - Modulo subtracter - Google Patents
Modulo subtracter Download PDFInfo
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- CN102880445A CN102880445A CN2012102649366A CN201210264936A CN102880445A CN 102880445 A CN102880445 A CN 102880445A CN 2012102649366 A CN2012102649366 A CN 2012102649366A CN 201210264936 A CN201210264936 A CN 201210264936A CN 102880445 A CN102880445 A CN 102880445A
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Abstract
The invention discloses a modulo (2<n>+1) subtracter, which specifically comprises an n-bit phase inverter, a first one-bit phase inverter, a second one-bit phase inverter, a two-input alternative denial gate, a two-input joint denial gate, a first n-bit binary adding device and a second n-bit binary adding device. According to the modulo (2<n>+1) subtracter, a correction signal is generated in advance by the simple logic operation of the most significant bit of two subtrahends, so that corresponding correction processing is carried out during first-time addition, a correction control signal generated by the most significant bit of the two subtrahends is adopted during second-time correction so as to reduce the correction time of a substracter operation result into two times from three times, and therefore, resources consumed by the modulo (2<n>+1) subtracter are reduced, and the operation speed is improved.
Description
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to a kind of design of subtracter.
Background technology
Before introducing subtracter, first residue number system (RNS, Residue Number Systems) is done an explanation.Residue number system RNS be a kind of by one group in twos the remainder of relatively prime remainder base describe the numeral the numerical representation method system.By { m
1, m
2..., m
LL remainder base forming, integer X, 0≤X＜M, wherein M=m
1* m
2* ... * m
L, it is X={x that unique expression mode is arranged in the RNS system
1, x
2..., x
L,
Wherein
X is for mould m in expression
iRemainder.Two operands operate in residue number system, and operational character is Θ, can be defined as:
{ z
1, z
2..., z
L}={ x
1, x
2..., x
LΘ { y
1, y
2..., y
L, wherein,
Here Θ can be modulo addition, mould subtraction or mould multiplication.These arithmetical operations all are executed in parallel in residue number system, and processing all is very little remainder rather than very large number.
For the selection of remainder base, { 2
n, 2
n-1,2
n+ 1} is very important arithmetic channel, is widely used, because when considering area * time
2The time, they provide the most effective circuit, and are the most effective at residue number system and binary Cheng Zhongye that turns over mutually.This shows, for mould (2
n+ 1) research of subtracter is very significant.
Because RNS arithmetic generally is converted into addition to subtraction and carries out computing, for mould (2
n+ 1) subtraction, establishing A is that minuend and B are subtrahend, has:
Directly carry out
Computing, operation result can overflow, namely operation result has more than or equal to 2
n+ 1 situation is once revised, and the result can be overflowed equally, need to once revise again.Revising generally is to finish by addition, and whole process is equivalent to needs three sub-additions, therefore compare consumes resources, and three sub-addition computings is all on critical path, so that arithmetic speed is very low.
Summary of the invention
The objective of the invention is in order to solve existing towards mould (2
n+ 1) subtracter consumes resources, the problem that speed is lower has proposed a kind of mould (2
n+ 1) subtracter.
Technical scheme of the present invention is: a kind of mould (2
n+ 1) subtracter comprises: n bit Inverting device, the one one bit Inverting device, the 21 bit Inverting device, two input nand gates, two input rejection gates, a n position binary adder and the 2nd n position binary addition;
If A and B are described mould (2
n+ 1) input of subtracter, wherein, A is minuend, and B is subtrahend, and total n+1 position is respectively [n:0], and Y is described mould (2
n+ 1) output of subtracter, total n+1 position is [n:0], wherein A[u:v], B[u:v] and Y[u:v] representing respectively the v position of A, B and Y to the number of u position correspondence, concrete annexation is as follows:
The input end of described n bit Inverting device is used for inputting described mould (2
n+ 1) the low n position of the input subtrahend B of subtracter, i.e. B[n-1:0], described n bit Inverting device is output as
The input end of described the one one bit Inverting device is used for inputting described mould (2
n+ 1) most significant digit of the subtrahend B of subtracter, i.e. B[n], described the one one bit Inverting device is output as
Two input ends of described two input nand gates are respectively applied to input described mould (2
n+ 1) the most significant digit A[n of the minuend A of subtracter] and the output of the one one bit Inverting device
Described two input nand gates are output as T;
Two input ends of described two input rejection gates are respectively applied to input described mould (2
n+ 1) the most significant digit A[n of the minuend A of subtracter] and the output of the one one bit Inverting device
Described two input rejection gates are output as W;
The addend input end of described first adder is used for inputting described mould (2
n+ 1) the low n position A[n-1:0 of the minuend A of subtracter] and the output of n bit Inverting device
The carry input of described first adder is used for inputting the output T of described two input nand gates, and the output terminal of described first adder is used for output R[n:0];
The input end of described the 21 bit Inverting device is used for inputting the output R[n:0 of described first adder] most significant digit, i.e. R[n], described the 21 bit Inverting device is output as
The addend input end of described second adder is used for inputting the output R[n:0 of described first adder] low n position R[n-1:0] and the output of the 21 bit Inverting device
The carry input of described second adder is used for inputting the output W of described two input rejection gates, and the output terminal of described second adder is used for output Y[n:0], be described mould (2
n+ 1) output of subtracter.
Beneficial effect of the present invention: mould (2 of the present invention
n+ 1) subtracter produces in advance corrected signal by the most significant digit simple logic computing of two subtrahends, thereby realize just carrying out during addition in the first time corresponding correcting process, and the Correction and Control signal that the most significant digit of two subtrahends of employing produces when revising for the second time, thereby reduced the correction number of times of subtracter operation result, be reduced to secondary from three times, thereby reduced mould (2
n+ 1) the spent resource of subtracter, and improved its arithmetic speed.
Description of drawings
Fig. 1 is mould (2 of the present invention
n+ 1) subtracter structural representation.
Embodiment
The invention will be further elaborated below in conjunction with accompanying drawing and specific embodiment.
Mould (2 of the present invention
n+ 1) the subtracter structure as shown in Figure 1, wherein, 1 is n bit Inverting device, 2 is the one one bit Inverting device, 3 is two input nand gates, 4 be 2 the input rejection gates, 5 is a n position totalizer, 6 is the 21 bit Inverting device, 7 is the 2nd n position totalizer; 1 be input as B[n-1:0], be output as
2 input B[n], be output as
3 be input as A[n] and
Be output as T; 4 be input as A[n] and
Be output as W; 5 be input as A[n-1:0],
And T, be output as R[n:0]; 6 be input as R[n], be output as
7 be input as R[n-1:0],
Be output as Y[n:0].Concrete annexation can be with reference to the summary of the invention part.
Here, mould (2 of the present invention
n+ 1) subtracter just carries out corresponding correcting process in the first time during addition, thereby has reduced the correction number of times of subtracter input results, is reduced to secondary from three times.In enforcement of the present invention, can adopt hardware description language (VHDL or Verilog) according to mould proposed by the invention (2
n+ 1) structural design of subtracter goes out required mould (2
n+ 1) subtracter just can carry out emulation and comprehensive; This subtracter can be finished required computing within a clock period, simple high-speed and high-efficiency, and Computer Simulation shows that this subtracter is with respect to existing mould (2
n+ 1) subtracter all improves a lot aspect Area and Speed.
Those of ordinary skill in the art will appreciate that, embodiment described here is in order to help reader understanding's principle of the present invention, should to be understood to that the protection domain of inventing is not limited to such special statement and embodiment.Everyly make various possible being equal to according to foregoing description and replace or change, all be considered to belong to the protection domain of claim of the present invention.
Claims (1)
1. mould (2
n+ 1) subtracter comprises: n bit Inverting device, the one one bit Inverting device, the 21 bit Inverting device, two input nand gates, two input rejection gates, a n position binary adder and the 2nd n position binary addition;
If A and B are described mould (2
n+ 1) input of subtracter, wherein, A is minuend, and B is subtrahend, and total n+1 position is respectively [n:0], and Y is described mould (2
n+ 1) output of subtracter, total n+1 position is [n:0], wherein A[u:v], B[u:v] and Y[u:v] representing respectively the v position of A, B and Y to the number of u position correspondence, concrete annexation is as follows:
The input end of described n bit Inverting device is used for inputting described mould (2
n+ 1) the low n position of the input subtrahend B of subtracter, i.e. B[n-1:0], described n bit Inverting device is output as
The input end of described the one one bit Inverting device is used for inputting described mould (2
n+ 1) most significant digit of the subtrahend B of subtracter, i.e. B[n], described the one one bit Inverting device is output as
Two input ends of described two input nand gates are respectively applied to input described mould (2
n+ 1) the most significant digit A[n of the minuend A of subtracter] and the output of the one one bit Inverting device
Described two input nand gates are output as T;
Two input ends of described two input rejection gates are respectively applied to input described mould (2
n+ 1) the most significant digit A[n of the minuend A of subtracter] and the output of the one one bit Inverting device
Described two input rejection gates are output as W;
The addend input end of described first adder is used for inputting described mould (2
n+ 1) the low n position A[n-1:0 of the minuend A of subtracter] and the output of n bit Inverting device
The carry input of described first adder is used for inputting the output T of described two input nand gates, and the output terminal of described first adder is used for output R[n:0];
The input end of described the 21 bit Inverting device is used for inputting the output R[n:0 of described first adder] most significant digit, i.e. R[n], described the 21 bit Inverting device is output as
The addend input end of described second adder is used for inputting the output R[n:0 of described first adder] low n position R[n-1:0] and the output of the 21 bit Inverting device
The carry input of described second adder is used for inputting the output W of described two input rejection gates, and the output terminal of described second adder is used for output Y[n:0], be described mould (2
n+ 1) output of subtracter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210264936.6A CN102880445B (en) | 2012-07-27 | 2012-07-27 | Modulo subtracter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210264936.6A CN102880445B (en) | 2012-07-27 | 2012-07-27 | Modulo subtracter |
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| Publication Number | Publication Date |
|---|---|
| CN102880445A true CN102880445A (en) | 2013-01-16 |
| CN102880445B CN102880445B (en) | 2015-03-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210264936.6A Expired - Fee Related CN102880445B (en) | 2012-07-27 | 2012-07-27 | Modulo subtracter |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001034455A (en) * | 1999-07-21 | 2001-02-09 | Denso Corp | Adding device, subtracting device, multiplying device and dividing device |
| CN102226885A (en) * | 2011-05-24 | 2011-10-26 | 电子科技大学 | Modulo 2n-2k-1 adder and design method thereof |
-
2012
- 2012-07-27 CN CN201210264936.6A patent/CN102880445B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001034455A (en) * | 1999-07-21 | 2001-02-09 | Denso Corp | Adding device, subtracting device, multiplying device and dividing device |
| CN102226885A (en) * | 2011-05-24 | 2011-10-26 | 电子科技大学 | Modulo 2n-2k-1 adder and design method thereof |
Non-Patent Citations (2)
| Title |
|---|
| E. VASSALOS等: "On the Design of Modulo 2n±1 Subtractors and Adders/Subtractors", 《CIRCUITS SYST SIGNAL PROCESS》 * |
| SOMAYEH TIMARCHI等: "New Design of RNS Subtractor for modulo 2n+1", 《INFORMATION AND COMMUNICATION TECHNOLOGIES，2006》 * |
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| CN102880445B (en) | 2015-03-11 |
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Granted publication date: 20150311 Termination date: 20160727 |