CN102226885A - Modulo 2n-2k-1 adder and design method thereof - Google Patents

Abstract

The present invention provides a kind of moulds

Adder and design method, the mould

Adder includes data pre-processing unit, carry generation unit, carry amending unit and summation unit. The mould Adder designs method correspondingly includes data prediction step, carry generation step, carry amendment step and summation step. Mould provided by the present invention

Adder and design method are corrected using carry twice, duplicate carry information is avoided to calculate, data prediction and carry correction algorithm special simultaneously allows using any existing quick prefix operating structure for calculating carry information, to increase design flexibility, arithmetic speed can be greatly improved.

Description

A kind of mould 2 n-2 k-1 totalizer and method for designing

Technical field

The present invention relates to the signal Processing field, specifically, relate to and a kind ofly be used for communicating by letter and the mould adder and the method for designing based on residue number system (RNS) of signal Processing.

Background technology

At present, along with the development of large scale integrated circuit,, generally believe that in the integrated circuit (IC) design in future large-scale parallel processing technique will replace traditional serial processing mode for satisfying the requirement that integrated circuit processing power and processing speed are improved day by day.Wherein adopting parallel numerical representation method system to replace traditional numerical representation method system is a direction of development, mainly is to realize parallel the carrying out of calculating and handling in the numerical representation method mode, improves the speed of computing thereby start with from front-end algorithm.

System (RNS:Residue Number System) is exactly a parallel numerical characterization system, be characterized in the complex calculation of traditional long number (Bit) is realized with the simple operation of a plurality of parallel less figure places, thereby reduced the complexity of single computing.Therefore, " residue number system " obtained widespread use in digital signal processing (DSP:Digital Signal Processing).In the digital signal processing method based on residue number system, in Fourier transform, digital filter, matrix inversion etc., mould adder is the basic processing unit that makes up other computing module.The mould adder design of optimizing is that residue number system is applied to the key point in the digital signal processing.

Mould 2 of the present invention ⁿ-2 ^k-1 totalizer has adopted twice carry correction, avoided the carry information calculations that repeats, simultaneously special data pre-service and carry correction algorithm allow to use any quick prefix computing of existing scale-of-two structure and are used to calculate carry information, thereby increased the flexible design degree, be easy to realize the balance between time delay, power consumption and area.

Summary of the invention

The purpose of this invention is to provide a kind of mould 2 ⁿ-2 ^k-1 (totalizer and the method for designing of 1≤k≤n-2), this totalizer have been avoided the carry information calculations that repeats by adopting the method for twice carry correction.Mould 2 of the present invention ⁿ-2 ^k-1 totalizer can be widely used in can significantly improving arithmetic speed in each arithmetic element in signal Processing field.

An object of the present invention is to provide a kind of mould 2 ⁿ-2 ^k-1 (totalizer of 1≤k≤n-2) comprises the data pretreatment unit, be used to finish the required carry of Parallel Prefix computing generates and carry propagation information to (g _i, p _i); The carry generation unit is used to finish the high-speed carry calculating of A+B+T to obtain

And c _Out, its core is a Parallel Prefix arithmetic element, and wherein A, B are two addends, and T is a correction, T=2 ^k+ 1; The carry amending unit is used for according to c _OutRight

Revise to obtain finishing the required carry of modulo addition

Sum unit, according to everybody carry information and part and information calculations obtains corresponding and a s _i

Mould 2 of the present invention ⁿ-2 ^k-1 totalizer, further, it is right that described data pretreatment unit generates the required prefix computing of prefix computing according to addend A and B step-by-step G wherein _iAnd p _iRepresent respectively the i position (i=0,1 ..., carry n-1) generates and the carry propagation position, g _i=a _ib _i(be a _iAnd b _iCarry out scale-of-two " with " logical operation), produce a carry to the i+1 position when two addends of expression and if only if i position are " 1 ";

("

" computing of expression scale-of-two XOR), have only in two addends of expression and if only if i position one could be during for " 1 " with the carry propagation of i-1 position to the i+1 position.

Mould 2 of the present invention ⁿ-2 ^k-1 totalizer, further, described carry amending unit is according to c _OutRight

Revise to obtain finishing the required carry of modulo addition

Described carry correction makes two bites at a cherry, the carry information that obtains after revising for the first time

As many as

Perhaps Be the carry information of A+B+T or A+B+T-1; Revising for the second time is according to c _OutValue right

Revise, obtain final revised carry information

Mould 2 of the present invention ⁿ-2 ^k-1 totalizer, further, described summation operation unit calculates

The time consider c _OutCorrection result under the control, i.e. c _Out=0 o'clock,

Carry information for A+B; Otherwise, then be the carry information of A+B+T.

Another object of the present invention provides a kind of mould 2 ⁿ-2 ^k-1 (method for designing of totalizer of 1≤k≤n-2) comprises step: the data pre-treatment step, finish that the required carry of Parallel Prefix computing generates and carry propagation information to (g _i, p _i); Carry generates step, calculates the high-speed carry of finishing A+B+T by Parallel Prefix and calculates to obtain

And c _Out, wherein A, B are two addends, T is a correction, T=2 ^k+ 1; Carry correction step is according to c _OutRight

Revise to obtain finishing the required carry of modulo addition Summation step, according to everybody carry information and part and information calculations obtains corresponding and a s _i

Mould 2 of the present invention ⁿ-2 ^kThe method for designing of-1 totalizer, further, wherein in the data pre-treatment step, it is right that addend A and B step-by-step generate the required prefix computing of prefix computing

G wherein _iAnd p _iRepresent respectively the i position (i=0,1 ..., carry n-1) generates and the carry propagation position, g _i=a _ib _i(be a _iAnd b _iCarry out scale-of-two " with " logical operation), produce a carry to the i+1 position when two addends of expression and if only if i position are " 1 ";

("

" computing of expression scale-of-two XOR), have only in two addends of expression and if only if i position one could be during for " 1 " with the carry propagation of i-1 position to the i+1 position.

Mould 2 of the present invention ⁿ-2 ^kThe method for designing of-1 totalizer, further, wherein in the carry correction step, according to c _OutRight

Revise to obtain finishing the required carry of modulo addition

Described carry correction makes two bites at a cherry, the carry information that obtains after revising for the first time As many as

Perhaps

Be the carry information of A+B+T or A+B+T-1; Revising for the second time is according to c _OutValue right

Revise, obtain final revised carry information

Mould 2 of the present invention ⁿ-2 ^kThe method for designing of-1 totalizer further, wherein in the summation step, is calculated

The time, consider c _OutCorrection result under the control, i.e. c _Out=0 o'clock,

Carry information for A+B; Otherwise, then be the carry information of A+B+T.

Mould adder of the present invention is the basic processing unit of residue number system, and it designs efficiently and realizes is the assurance of the good parallel characteristics of RNS.Mould 2 provided by the present invention ⁿ-2 ^k-1 totalizer and method for designing have adopted twice carry correction, avoided the carry information calculations that repeats, simultaneously special data pre-service and carry correction algorithm allow to use any existing quick prefix computing structure and are used to calculate carry information, thereby increased design flexibility, can significantly improve arithmetic speed.

Description of drawings

Fig. 1 is a mould 2 ⁿ-2 ^kThe structural drawing of-1 totalizer;

Fig. 2 is a specific embodiment mould 2 ⁸-2 ⁴The specific implementation structure of-1 totalizer;

Fig. 3 has showed mould 2 ⁸-2 ⁴Each processing unit function of-1 totalizer.

Embodiment

Below in conjunction with embodiment foregoing invention content of the present invention is described in further detail.

But this should be interpreted as that the scope of the above-mentioned theme of the present invention only limits to following embodiment.Not breaking away under the above-mentioned technological thought situation of the present invention, according to ordinary skill knowledge and customary means, make various replacements and change, all should comprise within the scope of the invention.

A kind of mould 2 ⁿ-2 ^k-1 totalizer (1≤k≤n-2), comprising:

The data pretreatment unit is used to finish required carry generation of Parallel Prefix computing and carry propagation information to (g _i, p _i);

The carry generation unit is used to finish the high-speed carry calculating of A+B+T to obtain

And c _Out, its core is a Parallel Prefix arithmetic element; Wherein A, B are two addends, and T is a correction, T=2 ^k+ 1;

The carry amending unit is used for according to c _OutRight Revise to obtain finishing the required carry of modulo addition And,

Sum unit, according to everybody carry information and part and information calculations obtains corresponding and a s _i

It is right that described data pretreatment unit generates the required prefix computing of prefix computing according to addend A and B step-by-step

G wherein _iAnd p _iRepresent respectively the i position (i=0,1 ..., carry n-1) generates and the carry propagation position, g _i=a _ib _i(be a _iAnd b _iCarry out scale-of-two " with " logical operation), produce a carry to the i+1 position when two addends of expression and if only if i position are " 1 ";

("

" computing of expression scale-of-two XOR), have only in two addends of expression and if only if i position one could be during for " 1 " with the carry propagation of i-1 position to the i+1 position.

Described carry amending unit is according to c _OutRight

Revise to obtain finishing the required carry of modulo addition

Described carry correction makes two bites at a cherry, the carry information that obtains after revising for the first time

As many as Perhaps

Be the carry information of A+B+T or A+B+T-1; Revising for the second time is according to c _OutValue right

Revise, obtain final revised carry information

Described sum unit is calculated

The time consider c _OutCorrection result under the control, i.e. c _Out=0 o'clock,

Carry information for A+B; Otherwise, then be the carry information of A+B+T.

A kind of mould 2 ⁿ-2 ^k-1 totalizer (method for designing of 1≤k≤n-2) may further comprise the steps:

The data pre-treatment step is finished required carry generation of Parallel Prefix computing and carry propagation information to (g _i, p _i);

Carry generates step, calculates the high-speed carry of finishing A+B+T by Parallel Prefix and calculates to obtain And c _Out, wherein A, B are two addends, T is a correction, T=2 ^k+ 1;

Carry correction step is according to c _OutRight

Revise to obtain finishing the required carry of modulo addition

And,

Summation step, according to everybody carry information and part and information calculations obtains corresponding and a s _i

A kind of mould 2 ⁿ-2 ^kThe method for designing of-1 totalizer, wherein in the data pre-treatment step, it is right that addend A and B step-by-step generate the required prefix computing of prefix computing

G wherein _iAnd p _iRepresent respectively the i position (i=0,1 ..., carry n-1) generates and the carry propagation position, g _i=a _ib _i(be a _iAnd b _iCarry out scale-of-two " with " logical operation), produce a carry to the i+1 position when two addends of expression and if only if i position are " 1 "; ("

" computing of expression scale-of-two XOR), have only in two addends of expression and if only if i position one could be during for " 1 " with the carry propagation of i-1 position to the i+1 position.

A kind of mould 2 ⁿ-2 ^kThe method for designing of-1 totalizer is wherein in the carry correction step, according to c _OutRight

Revise to obtain finishing the required carry of modulo addition

Described carry correction makes two bites at a cherry, the carry information that obtains after revising for the first time

As many as

Perhaps

Be the carry information of A+B+T or A+B+T-1; Revising for the second time is according to c _OutValue right

Revise, obtain final revised carry information

A kind of mould 2 ⁿ-2 ^kThe method for designing of-1 totalizer wherein in the summation step, is calculated The time, consider c _OutCorrection result under the control, i.e. c _Out=0 o'clock,

Carry information for A+B; Otherwise, then be the carry information of A+B+T.

Fig. 1 shows mould 2 ⁿ-2 ^kThe structural drawing of-1 totalizer.It is made of data pretreatment unit 101, carry generation unit 102, carry amending unit 103 and sum unit 104 etc.Different with the ordinary binary additive operation, modulo addition does not have final carry output.The mould m of additive operation carry out to(for) two integer A, B (A, B ∈ [0, m)) is defined as:

$C={<A+B>}_m$

$=\left\{\begin{array}{cc}A+B& A+B<m\\ A+B-m& A+B\&GreaterEqual;m\end{array}\right.---\left(1\right)$

Be A and B's and if less than m, then directly get itself and operation result as the modulo addition result.Otherwise, deduct the net result of m as modulo addition.In fact, formula (1) and following formula equivalence:

$C=\left\{\begin{array}{cc}A+B& A+B+T<2^n\\ {<A+B+T>}_{2^n}& A+B+T\&GreaterEqual;2^n\end{array}\right.---\left(2\right)$

Wherein

Be that n is greater than log ₂The smallest positive integral of m, T=2 ⁿ-m.Formula (2) shows that if the carry of A+B+T is output as " 1 ", then the result of modulo addition is the low n bit of A+B+T; Otherwise, be A+B.

Usually, the realization of mould adder all needs to calculate respectively the value of A+B+T and A+B, compares judgement at last again, thereby obtains the result of final modulo addition.The present invention makes full use of mould 2 ⁿ-2 ^kThe characteristics of the correction T of-1 totalizer by suitable data pre-service, make each bit carry information of A+B+T

And c _OutCalculating can use the structure of prefix computing arbitrarily.Then, according to the highest carry c of A+B+T _OutRight

Revise each the required bit true carry information of modulo addition that obtains

Thereby avoided the carry information of independent calculating A+B+T and A+B.

It is right to generate the required prefix computing of prefix computing according to addend A, B step-by-step:

$(g_i,p_i)=(a_i{b}_i,a_i\&CirclePlus;b_i)---\left(3\right)$

Wherein, g _iAnd p _iRepresent respectively the i position (i=0,1 ..., n-1) carry generates and carry propagation position information, p _iBe also referred to as part and information.g _i=a _ib _i(be a _iSame b _iCarry out scale-of-two " with " logical operation) produce a carry to the i+1 position when two addends of expression and if only if i position are " 1 ";

("

" computing of expression scale-of-two XOR) and have only in two addends of expression and if only if i position one could be during for " 1 " with the carry propagation of i-1 position to the i+1 position.

The prefix arithmetic element is used to generate each required bit carry information of sum unit, and the computing of binary addition prefix is:

$\left\{\begin{array}{c}(G_{i:i}^0,P_{i:i}^0)=(g_i,p_i)\\ (G_{i:k}^l,P_{i:k}^l)=(G_{i:j+1}^{l-1},P_{i:j+1}^{l-1})\&CenterDot;(G_{j:k}^{l-1},P_{j:k}^{l-1})\\ =(G_{i:j+1}^{l-1}+P_{i:j+1}^{l-1}{G}_{j:k}^{l-1},P_{i:j+1}^{l-1}{P}_{j:k}^{l-1})\end{array}\right.---\left(4\right)$

Wherein, i=0,1 ..., n-1,0≤k≤j≤i, l=1,2 ..., m, the l little then carry propagation time delay that heals is littler, the computing of " " expression prefix.The 0th grade prefix operation result is (g _i, p _i), in fact the data pre-service also can be considered the part of prefix computing, promptly

Be illustrated in k position that the l level calculates to i position prefix operation result, be also referred to as the computing of prefix group.

Formula (4) shows

("+" expression scale-of-two " or " logical operation), promptly the k position to the carry of i position by the group carry of j+1 position to the i position

Decision, or by the group carry propagation of j+1 position to the i position Determine whether carry output with a last group (the k position is to the j position)

Output as this prefix computing; And

Only show when the k position to j position and j+1 position to the i position this two group carry propagate the carry that all allows low level by the time, the k position just allows other carry by its propagation to the i position.In fact, work as i=0,1 ..., when n-1,0≤k≤j≤i and v≤j, formula (5) is also set up.

$\begin{array}{c}(G_{i:k}^l,P_{i:k}^l)=(G_{i:v}^{l-1},P_{i:v}^{l-1})\&CenterDot;(G_{j:k}^{l-1},P_{j:k}^{l-1})\\ =(G_{i:v}^{l-1}+P_{i:v}^{l-1}{G}_{j:k}^{l-1},P_{i:v}^{l-1}{P}_{j:k}^{l-1})\end{array}---\left(5\right)$

For data pretreatment unit 101, because the present invention has adopted the carry information to A+B+T The method of revising has obtained the required carry information of modulo addition, therefore, the carry that the data pretreatment unit only needs to produce A+B+T generate and carry propagation information to (g _i, p _i).By formula (2), work as m=2 ⁿ-2 ^k-1 o'clock,

Make the binary representation of A and B be respectively a _N-1A _ka _K-1A ₁a ₀And b _N-1B _kb _K-1B ₁b ₀, the binary form of correction T is shown Shown in 102 among Fig. 1, the calculating of A+B+T be can be considered the totalizer A1 of two cascades and the additive operation that A2 finishes low k bit and high n-k bit respectively.Order

Then the additive operation finished of totalizer A1 and A2 is as the formula (6):

$\left\{\begin{array}{c}{S}_{A1}=a_{k-1}...a_1{a}_0+b_{k-1}...b_1{b}_0+T_{A1}\\ S_{A2}=a_{n-1}...a_k+b_{n-1}...b_k+T_{A2}+c_{A1}\end{array}\right.---\left(6\right)$

C wherein _A1The final carry output of expression totalizer A1.

For the T among the totalizer A1 _A1, only lowest order is " 1 ", and is therefore visual for the acquiescence lowest order is the k bit adder computing of " 1 ", this and ordinary binary addition are in full accord.Its data preprocessing method that is used for the prefix computing is identical with the traditional binary totalizer, only need consider its lowest order for " 1 ", its carry generate and diffuse information into:

$\left\{\begin{array}{cc}(g_0,p_0)=(a_0+b_0,\stackrel{\&OverBar;}{a_0\&CirclePlus;b_0}),& i=0\\ (g_i,p_i)=(a_i{b}_i,a_i\&CirclePlus;b_i),& i=\mathrm{1,2},...,k-1\end{array}\right.---\left(7\right)$

By formula (6) as can be known, for totalizer A2, not only need to add constant T _A2, also need to handle the carry output c that totalizer A1 is produced _A1Therefore, this totalizer can be thought the binary adder of one three input, and these three inputs are respectively a _N-1A _k, b _N-1B _kAnd T _A2Usually, three-input adder can be obtained by two-stage two input summers.Therefore,, three-input adder can be become two input summers and handle, promptly work as i=k by following mode, k+1 ..., during n-1, at first calculate a _iAnd b _iCarry generate and carry propagation information (g ' _i, p ' _i):

$(g_i^{\&prime;},p_i^{\&prime;})=(a_i{b}_i,a_i\&CirclePlus;b_i),i=k,k+1,...,n-1---\left(8\right)$

To then, (g ' _i, p ' _i) and As partial input, obtain final data pre-service result:

$\left\{\begin{array}{cc}(g_k,p_k)=(g_k^{\&prime;},\stackrel{\&OverBar;}{p_k^{\&prime;}}),& i=k\\ (g_i,p_i)=(i_i^{\&prime;}{g}_{i-1}^{\&prime;},p_i^{\&prime;}\&CirclePlus;g_{i-1}^{\&prime;}),& i=k+1,...,n-1\end{array}\right.---\left(9\right)$

In addition, the final carry output c of A2 _A2Calculate by following formula:

c _A2＝a _n-1b _n-1＝g′ _n-1 (10)

For carry generation unit 102, according to n (g of data pretreatment unit 101 outputs _i, p _i) information is right, generates the carry of each bit fast

It can adopt the prefix algorithm of existing any one n bit width to realize, as SK, BK, KS, HC and ELM prefix trees etc.Carry

Calculate by following formula:

$c_{i+1}^T=G_{i:0}+P_{i:0}{c}_{\mathrm{in}}---\left(11\right)$

In addition, the Parallel Prefix unit has only calculated n (g _i, p _i) information is right, but because the highest carry c of data preprocessing part _A2And have neither part nor lot in the prefix computing.Therefore, need be with its highest carry with prefix trees Computing is to obtain the carry output c of A+B+T _OutThen, by It is right whether decision needs

Correction is to obtain the carry of A+B.Consider in 101 (g ₀, p ₀) given tacit consent to minimum carry and be input as c _In=1, therefore, c _OutCan calculate by following formula:

$\begin{array}{c}{c}_{\mathrm{out}}={\mathrm{<figure-callout\; id="2"\; label="c\; A"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">c</figure-callout>}}_A+c_n^T\\ ={\mathrm{<figure-callout\; id="2"\; label="c\; A"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">c</figure-callout>}}_A+G_{n-1:0}\\ ={\mathrm{<figure-callout\; id="2"\; label="c\; A"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">c</figure-callout>}}_A+G_{n-1:l}+P_{n-1:l}{G}_{l-1:0}\\ ={\mathrm{<figure-callout\; id="2"\; label="c\; A"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">c</figure-callout>}}_A+G_{n-1:l}+P_{n-1:l}{c}_l^T\end{array}---\left(12\right)$

0≤l≤n-1 wherein.

For the carry amending unit, its major function is, the highest carry c of the A+B+T that calculates according to the carry generation unit _Out, to each bit carry information of A+B+T Revise, to obtain the required carry information of addition

To avoid the carry information of double counting A+B.For the mould adder among the present invention, T=2 ^k+ 1, its binary form is shown Can think that the transportation of A+B+T is broken down into two ones: at first calculate

Calculate then

Two " 1 " in the binary representation of T can be considered as the minimum carry of 102 totalizer A1 and A2.Corresponding therewith, can obtain each bit carry information of A+B by twice correction.Correction result obtains for the first time

Carry information, revise for the second time and then can obtain the carry information of A+B, and whether revise the highest carry c by A+B+T _OutDecision.

Revise for the first time: because the binary form of T is shown Can with

Be considered as (A+B+T-1)+c _In(c _In=1) each bit carry output, therefore, the output of the carry of A+B+T-1

(i=0,1,2 ..., the following formula that passes through n-2) calculates:

$c_{i+1}^{T-1}=\stackrel{\&OverBar;}{P_{i:0}}{c}_{i+1}^T---\left(13\right)$

Basic theories by mould adder knows that the prerequisite that the carry of A+B+T is revised is c _Out=0.Here can equivalence be an alternative logic, c _OutAs the control end of selector switch, and

With Be data input pin, output is correction result for the first time, makes it be

$c_{i+1}^{c_1}=\stackrel{\&OverBar;}{c_{\mathrm{out}}}{c}_{i+1}^{T-1}+c_{\mathrm{out}}{c}_{i+1}^T$

$=\stackrel{\&OverBar;}{c_{\mathrm{out}}}\stackrel{\&OverBar;}{P_{i:0}}{c}_{i+1}^T+c_{\mathrm{out}}{c}_{i+1}^T---\left(14\right)$

$=c_{i+1}^T(c_{\mathrm{out}}+\stackrel{\&OverBar;}{P_{i:0}})$

Revise for the second time:, after revising for the first time, obtain by formula (14)

As many as Or Be the carry information of A+B+T or A+B+T-1.And then according to c _OutValue right

Carry out the second time and revise, the carry information that order obtains after revising for the second time is

Adopt and revise for the first time identical disposal route, as if c _Out=0

Be A+B+T-1-2 ^kThe carry information of (being A+B), otherwise

Be the carry information of A+B+T, promptly

Be the needed actual carry information of mould adder.Revising for the second time fundamental purpose is to eliminate T _A2In the influence of lowest order " 1 ".

Because T=2 ^k+ 1, work as i=1,2 ..., during k, T _A2In " 1 " no longer influence

Therefore:

$c_i^{\mathrm{real}}=c_i^{c_1}(i=\mathrm{1,2},...,k)---\left(15\right)$

Work as i=k+1 ..., during n-1, reply

Correction is to eliminate T _A2The influence that is brought.By the analysis of data preprocessing part as can be known, totalizer A2 is two addend p ' that bring the position input among Fig. 1 this moment _N-1P ' _K+1P ' _kAnd g ' _N-2G ' _K+1G ' _k1 sum operation, A1 exports through revised carry among Fig. 1 and the carry of A2 is input as

Notice g ' _N-2G ' _K+1G ' _k1 lowest order is " 1 ", therefore can think that A2 has finished minimum carry and has been input as " 1 ", and addend is p ' _N-1P ' _K+1P ' _kWith

Additive operation, promptly two kinds of operation results of the (a) and (b) of formula (16) are identical, have identical carry information.In other words, can be once more to the carry information of totalizer A2

(i=k+1 .. n-1) revise to obtain the carry of A+B, again in conjunction with c _OutThen can obtain the final carry information of each required bit of modulo addition

Noting, is to carry out under the minimum carry of considering totalizer A2 is the situation of constant " 1 " owing to revise for the second time, so all should be by p ' with the carry propagation information that uses in the makeover process _N-1P ' _K+1P ' _kWith

Calculate.Can find lowest order difference only under this dual mode, addend g ' (a) by the addend in two kinds of additive operations of comparison expression (16) _N-2G ' _K+1G ' _k1 lowest order is " 1 ", and addend (b)

Lowest order be

The i.e. lowest order difference only of carry propagation information under two kinds of situations.(a) carry propagation information is tried to achieve by formula (8) and (9), and the carry propagation information that makes (b) is p " _k, then:

$\left\{\begin{array}{cc}{p}_k^{\&prime;\&prime;}=p_k^{\&prime;}\&CirclePlus;{\mathrm{<figure-callout\; id="1"\; label="c\; k\; c"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">c</figure-callout>}}_{k{c}_{}}^{{}_1}={\mathrm{<figure-callout\; id="1"\; label="c\; k\; c"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">c</figure-callout>}}_{k{c}_{}}^{{}_1}\&CirclePlus;\stackrel{\&OverBar;}{p_k}& i=k\\ p_i^{\&prime;\&prime;}=p_i& i=k+1,...,n-1\end{array}\right.---\left(17\right)$

Make its group propagate the position and be P " _I:k, then:

P″ _i:k＝P _i:k+1p″ _k (18)

Work as i=k+1, k+2 ..., during n-2, by formula (14), revised carry information is for the second time:

$c_{i+1}^{\mathrm{real}}=(\stackrel{\&OverBar;}{P_{i:k}^{\&prime;\&prime;}}+c_{\mathrm{out}})c_{i+1}^{{\mathrm{<figure-callout\; id="1"\; label="c"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">c</figure-callout>}}_1}$

$=(\stackrel{\&OverBar;}{P_{i:k+1}{p}_k^{\&prime;\&prime;}}+c_{\mathrm{out}})c_{i+1}^{c_1}---\left(19\right)$

$=c_{i+1}^T(c_{\mathrm{out}}+\stackrel{\&OverBar;}{P_{i:0}})(\stackrel{\&OverBar;}{P_{i:k+1}{p}_k^{\&prime;\&prime;}}+c_{\mathrm{out}})$

With formula (17) substitution (19), then:

$c_{i+1}^{\mathrm{real}}=c_{i+1}^T(c_{\mathrm{out}}+\stackrel{\&OverBar;}{P_{i:0}})(\stackrel{\&OverBar;}{P_{i:k+1}({\mathrm{<figure-callout\; id="1"\; label="c\; k\; c"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">c</figure-callout>}}_{k{c}_{}}^{{}_1}\&CirclePlus;\stackrel{\&OverBar;}{p_k})}+c_{\mathrm{out}})$

$=c_{i+1}^T(c_{\mathrm{out}}+(\stackrel{\&OverBar;}{P_{i:k+1}}+c_k^{c_1}\stackrel{\&OverBar;}{p_k}+\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="c\; k\; c"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">c</figure-callout>}}_{k{c}_{}}^{{}_1}}{p}_k)(c_{\mathrm{out}}+\stackrel{\&OverBar;}{P_{i:0}}))$

$=c_{i+1}^T(c_{\mathrm{out}}+\stackrel{\&OverBar;}{P_{i:0}}\stackrel{\&OverBar;}{P_{i:k+1}}+(\stackrel{\&OverBar;}{P_{i:k+1}}+\stackrel{\&OverBar;}{p_k}+\stackrel{\&OverBar;}{P_{k-1:0}})(c_k^{c_1}\stackrel{\&OverBar;}{p_k}+\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="c\; k\; c"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">c</figure-callout>}}_{k{c}_{}}^{{}_1}}{p}_k))$ (20)

$=c_{i+1}^T\left(\begin{array}{c}{c}_{\mathrm{out}}+\stackrel{\&OverBar;}{P_{i:0}}\stackrel{\&OverBar;}{P_{i:k+1}}+\stackrel{\&OverBar;}{P_{i:k+1}}\stackrel{\&OverBar;}{p_k}{\mathrm{<figure-callout\; id="1"\; label="c\; k\; c"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">c</figure-callout>}}_{k{c}_{}}^{{}_1}+\stackrel{\&OverBar;}{P_{i:k+1}}{p}_k\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="c\; k\; c"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">c</figure-callout>}}_{k{c}_{}}^{{}_1}}+\\ \stackrel{\&OverBar;}{p_k}{\mathrm{<figure-callout\; id="1"\; label="c\; k\; c"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">c</figure-callout>}}_{k{c}_{}}^{{}_1}+\stackrel{\&OverBar;}{P_{k-1:0}}\stackrel{\&OverBar;}{p_k}{\mathrm{<figure-callout\; id="1"\; label="c\; k\; c"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">c</figure-callout>}}_{k{c}_{}}^{{}_1}+\stackrel{\&OverBar;}{P_{k-1:0}}{p}_k\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="c\; k\; c"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">c</figure-callout>}}_{k{c}_{}}^{{}_1}}\end{array}\right)$

$=c_{i+1}^T(c_{\mathrm{out}}+\stackrel{\&OverBar;}{P_{i:0}}\stackrel{\&OverBar;}{P_{i:k+1}}+\stackrel{\&OverBar;}{p_k}{\mathrm{<figure-callout\; id="1"\; label="c\; k\; c"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">c</figure-callout>}}_{k{c}_{}}^{{}_1}+\stackrel{\&OverBar;}{P_{i:k+1}}\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="c\; k\; c"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">c</figure-callout>}}_{k{c}_{}}^{{}_1}}{p}_k+\stackrel{\&OverBar;}{P_{k-1:0}}\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="c\; k\; c"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">c</figure-callout>}}_{k{c}_{}}^{{}_1}}{p}_k)$

$=c_{i+1}^T(c_{\mathrm{out}}+\stackrel{\&OverBar;}{P_{i:k+1}}+\stackrel{\&OverBar;}{p_k}{\mathrm{<figure-callout\; id="1"\; label="c\; k\; c"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">c</figure-callout>}}_{k{c}_{}}^{{}_1}+p_k\stackrel{\&OverBar;}{P_{k-1:0}}\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="c\; k\; c"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">c</figure-callout>}}_{k{c}_{}}^{{}_1}})$

With formula (14) substitution formula (20), then:

$c_{i+1}^{\mathrm{real}}=c_{i+1}^T(c_{\mathrm{out}}+\stackrel{\&OverBar;}{P_{i:k+1}}+\stackrel{\&OverBar;}{P_{k-1:0}}\stackrel{\&OverBar;}{p_k}{c}_k^T+\stackrel{\&OverBar;}{P_{k-1:0}}{p}_k\stackrel{\&OverBar;}{c_k^T})$ (21)

$=c_{i+1}^T(c_{\mathrm{out}}+\stackrel{\&OverBar;}{P_{i:k+1}}+\stackrel{\&OverBar;}{P_{k-1:0}}(p_k\&CirclePlus;c_k^T))$

When i=k, P " _I:k=P " _K:k=p " _k, in like manner can get:

$c_{i+1}^{\mathrm{real}}=c_{i+1}^T(c_{\mathrm{out}}+\stackrel{\&OverBar;}{P_{k-1:0}}(p_k\&CirclePlus;c_k^T))---\left(22\right)$

Can get by formula (14), (15), (21) and (22), by c _OutThe mould after revising of control adds each required bit carry information of computing:

$c_{i+1}^{\mathrm{real}}=\left\{\begin{array}{cc}{c}_{i+1}^T(c_{\mathrm{out}}+\stackrel{\&OverBar;}{P_{i:0}})& i=\mathrm{0,1},...,k-1\\ c_{i+1}^T(c_{\mathrm{out}}+\stackrel{\&OverBar;}{P_{k-1:0}}(p_k\&CirclePlus;c_k^T))& i=k\\ c_{i+1}^T(c_{\mathrm{out}}+\stackrel{\&OverBar;}{P_{i:k+1}}+\stackrel{\&OverBar;}{P_{k-1:0}}(p_k\&CirclePlus;c_k^T))& i=k+1,...,n-2\end{array}\right.---\left(23\right)$

Order:

$\left\{\begin{array}{c}{\mathrm{<figure-callout\; id="1"\; label="z"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">z</figure-callout>}}_1=\stackrel{\&OverBar;}{P_{k-1:0}}(p_k\&CirclePlus;c_k^T)\\ z_2^i=\stackrel{\&OverBar;}{P_{i:k+1}}+\stackrel{\&OverBar;}{P_{k-1:0}}(p_k\&CirclePlus;c_k^T)\end{array}\right.---\left(24\right)$

Then:

$c_{i+1}^{\mathrm{real}}=\left\{\begin{array}{cc}{c}_{i+1}^T(c_{\mathrm{out}}+\stackrel{\&OverBar;}{P_{i:0}})& i=\mathrm{0,1},...,k-1\\ c_{i+1}^T(c_{\mathrm{out}}+z_1)& i=k\\ c_{i+1}^T(c_{\mathrm{out}}+z_2^i)& i=k+1,...,n-2\end{array}\right.---\left(25\right)$

So far, obtained each bit carry output of mould adder, for follow-up summation operation provides necessary information.

For summation operation unit 104, basic identical with general binary adder based on the prefix computing, but

Be to consider c _OutCorrection result under the control, i.e. c _Out=0 o'clock

Be the carry information of A+B, otherwise then be the carry information of A+B+T, therefore when summation, also should use corresponding A+B or part and the information of A+B+T.Order With

Part and the information of representing A+B and A+B+T respectively what the data pretreatment unit calculated are

, promptly

Simultaneously as can be known, only work as i=0, during k by the data pretreatment unit

Therefore, have

$\left\{\begin{array}{cc}{p}_0^0=\stackrel{\&OverBar;}{p_0},p_0^1=p_0& i=0\\ p_k^0=\stackrel{\&OverBar;}{p_k},{\mathrm{<figure-callout\; id="1"\; label="p\; k"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">p</figure-callout>}}_k^{}=p_k& i=k\\ p_i^0={\mathrm{<figure-callout\; id="1"\; label="p\; i"\; filenames="HDA0000063434080000012.png"\; state="\{\{state\}\}">p</figure-callout>}}_i^{}=p_i& i=1,...,k-1,k+1,...,n-1\end{array}\right.---\left(26\right)$

And then have

$s_0=\stackrel{\&OverBar;}{c_{\mathrm{out}}}{p}_0^0+c_{\mathrm{out}}{p}_0^1$

$=\stackrel{\&OverBar;}{c_{\mathrm{out}}}\stackrel{\&OverBar;}{p_0}+c_{\mathrm{out}}{p}_0---\left(27\right)$

$=c_{\mathrm{out}}\&CirclePlus;\stackrel{\&OverBar;}{p_0}$

$s_k=c_k^{\mathrm{real}}\&CirclePlus;(\stackrel{\&OverBar;}{c_{\mathrm{out}}}{p}_k^0+c_{\mathrm{out}}{p}_k^1)$

$=c_k^{\mathrm{real}}\&CirclePlus;(\stackrel{\&OverBar;}{c_{\mathrm{out}}}\stackrel{\&OverBar;}{p_k}+c_{\mathrm{out}}{p}_k)---\left(28\right)$

$=c_k^{\mathrm{real}}\&CirclePlus;c_{\mathrm{out}}\&CirclePlus;\stackrel{\&OverBar;}{p_k}$

$s_i=c_i^{\mathrm{real}}\&CirclePlus;p_i---\left(29\right)$

Last summation output can be expressed as:

$s_i=\left\{\begin{array}{cc}{c}_{\mathrm{out}}\&CirclePlus;\stackrel{\&OverBar;}{p_0}& i=0\\ c_k^{\mathrm{real}}\&CirclePlus;c_{\mathrm{out}}\&CirclePlus;\stackrel{\&OverBar;}{p_k}& i=k\\ c_i^{\mathrm{real}}\&CirclePlus;p_i& \text{i=1,...,k-1,k+1,...,n-1}\end{array}\right.---\left(30\right)$

In formula (30),

Can with Calculate simultaneously, therefore can not introduce extra time delay.

Fig. 2 shows mould 2 ⁸-2 ⁴The specific implementation structure of-1 totalizer.Existing n=8, k=4.201 is the data pretreatment unit, and Unit 101 in the corresponding diagram 1 produce the required information of 8 prefix computings to (g _i, p _i).Carry generation unit 102 in 202 corresponding diagram 1 utilizes the prefix computing to produce the carry information of each bit

And c _Out, and with P _I:0(i=1,2,3), z ₁,

Be stored in 205 etc. intermediate information.Carry amending unit 103 in 203 corresponding diagram 1 is according to 202 c that generate _OutAnd in conjunction with the P that is stored in 205 _I:0, z ₁,

Etc. intermediate information, right

Revise, thereby obtain the carry information that needs At last, the sum unit 104 of 204 corresponding diagram 1 according to formula (30), is done operations such as some simple NOT sum distances and is realized last summation operation, thereby obtain the result of final modular arithmetic.

Fig. 3 shows mould 2 among Fig. 2 ⁸-2 ⁴Each processing unit function of-1 totalizer.In data pretreatment unit 201,301,302 and 303 these three functional units have been used.Wherein, 301 and 303 is to produce the required information of prefix computing to (g according to formula (7) _i, p _i), and generating (g _i, p _i) process in, only need use simple " with ", " or ", operations such as NOT sum distance.Because T _A1Only lowest order is " 1 ", by formula (7), (g ₀, p ₀) generation meeting and other (g _i, p _i) the generation difference, therefore produce (g ₀, p ₀) time will be with 301 but not 303.In addition, (g ₄, p ₄) generation to consider T _A2Only lowest order is " 1 " this fact, and therefore, the method for its generation is different from other (g _i, p _i), as the formula (9).The 302nd, to the p ' in the formula (9) _kDo the operation of a negate.Carry generation unit 202 is prefix arithmetic elements, according to information to (g _i, p _i), generate carry information

And c _OutIn this process, use 304,305 and 306 these three functional units.The 304th, the prefix operator of standard, by formula (4) by earlier " with " back " or " computing obtain new information to (G ", P "), and

Directly from (G ", the G among the P ") ", promptly

The 305th, on 304 bases, done the prefix operator of simplifying, it only need obtain G " and, need not to calculate P ", 305 output result is

Unit 306 calculate c according to formula (12) _Out, n=7 wherein, l=4, x=g ' ₇,

(G _7:4, P _7:4) directly from a prefix operator on the crown.Though in Fig. 2, be grouped into 307 in Unit 203, because it does not participate in the calculating of carry correction, but participated in summation operation, therefore, in carry amending unit 203, only used 308 these functional units.It utilizes c _Out, the output in conjunction with 205 is P as a result _I:0(i=1,2,3), z ₁With Right

Revise one by one.At last, in sum unit 204, used 308 and 309 two unit, they all are nonequivalence operations.Wherein, 308 is relative 309, just one of them input done the operation of a negate.

Claims (8)

1. mould 2 ⁿ-2 ^k-1 totalizer is characterized in that, comprising:

The data pretreatment unit is used to finish required carry generation of Parallel Prefix computing and carry propagation information to (g _i, p _i);

The carry generation unit is used to finish the high-speed carry calculating of A+B+T to obtain

And c _Out, its core is a Parallel Prefix arithmetic element; Wherein A, B are two addends, and T is a correction, T=2 ^k+ 1;

The carry amending unit is used for according to c _OutRight

Revise to obtain finishing the required carry of modulo addition

And,

Sum unit, according to everybody carry information and part and information calculations obtains corresponding and a s _i

2. mould 2 as claimed in claim 1 ⁿ-2 ^k-1 totalizer is characterized in that, it is right that described data pretreatment unit generates the required prefix computing of prefix computing according to addend A and B step-by-step

G wherein _iAnd p _iRepresent respectively the i position (i=0,1 ..., carry n-1) generates and the carry propagation position, g _i=a _ib _i, produce a carry to the i+1 position when two addends of expression and if only if i position are " 1 ";

Have only in two addends of expression and if only if i position one could be during for " 1 " with the carry propagation of i-1 position to the i+1 position.

3. mould 2 as claimed in claim 1 ⁿ-2 ^k-1 totalizer is characterized in that, described carry amending unit is according to c _OutRight

Revise to obtain finishing the required carry of modulo addition

Described carry correction makes two bites at a cherry, the carry information that obtains after revising for the first time

As many as

Perhaps

Be the carry information of A+B+T or A+B+T-1; Revising for the second time is according to c _OutValue right

Revise, obtain final revised carry information

4. mould 2 as claimed in claim 1 ⁿ-2 ^k-1 totalizer is characterized in that, described sum unit is calculated

The time consider c _OutCorrection result under the control, i.e. c _Out=0 o'clock,

Carry information for A+B; Otherwise, then be the carry information of A+B+T.

5. mould 2 ⁿ-2 ^kThe method for designing of-1 totalizer is characterized in that, may further comprise the steps:

The data pre-treatment step is finished required carry generation of Parallel Prefix computing and carry propagation information to (g _i, p _i);

Carry generates step, calculates the high-speed carry of finishing A+B+T by Parallel Prefix and calculates to obtain

And c _Out, wherein A, B are two addends, T is a correction, T=2 ^k+ 1;

Carry correction step is according to c _OutRight

Revise to obtain finishing the required carry of modulo addition

And,

Summation step, according to everybody carry information and part and information calculations obtains corresponding and a s _i

6. mould 2 as claimed in claim 5 ⁿ-2 ^kThe method for designing of-1 totalizer is characterized in that, wherein in the data pre-treatment step, it is right that addend A and B step-by-step generate the required prefix computing of prefix computing

G wherein _iAnd p _iRepresent respectively the i position (i=0,1 ..., carry n-1) generates and the carry propagation position, g _i=a _ib _i, produce a carry to the i+1 position when two addends of expression and if only if i position are " 1 ";

Have only in two addends of expression and if only if i position one could be during for " 1 " with the carry propagation of i-1 position to the i+1 position.

7. mould 2 as claimed in claim 5 ⁿ-2 ^kThe method for designing of-1 totalizer is characterized in that, wherein in the carry correction step, according to c _OutRight

Revise to obtain finishing the required carry of modulo addition

Described carry correction makes two bites at a cherry, the carry information that obtains after revising for the first time

As many as

Perhaps

Be the carry information of A+B+T or A+B+T-1; Revising for the second time is according to c _OutValue right

Revise, obtain final revised carry information

8. mould 2 as claimed in claim 5 ⁿ-2 ^kThe method for designing of-1 totalizer is characterized in that, wherein in the summation step, calculates

The time, consider c _OutCorrection result under the control, i.e. c _Out=0 o'clock,

Carry information for A+B; Otherwise, then be the carry information of A+B+T.

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