JP2001027945A5 - - Google Patents

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Publication number
JP2001027945A5
JP2001027945A5 JP2000149271A JP2000149271A JP2001027945A5 JP 2001027945 A5 JP2001027945 A5 JP 2001027945A5 JP 2000149271 A JP2000149271 A JP 2000149271A JP 2000149271 A JP2000149271 A JP 2000149271A JP 2001027945 A5 JP2001027945 A5 JP 2001027945A5
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JP
Japan
Prior art keywords
multiply
bit
register file
accumulate
unit
Prior art date
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Application number
JP2000149271A
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English (en)
Japanese (ja)
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JP3683773B2 (ja
JP2001027945A (ja
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Priority claimed from US09/316,340 external-priority patent/US6493817B1/en
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Publication of JP2001027945A publication Critical patent/JP2001027945A/ja
Publication of JP2001027945A5 publication Critical patent/JP2001027945A5/ja
Application granted granted Critical
Publication of JP3683773B2 publication Critical patent/JP3683773B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2000149271A 1999-05-21 2000-05-22 Ｓｉｍｄ演算を実行するために標準ｍａｃユニットを利用する浮動小数点ユニット Expired - Fee Related JP3683773B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/316,340 US6493817B1 (en) 1999-05-21 1999-05-21 Floating-point unit which utilizes standard MAC units for performing SIMD operations
US316340 1999-05-21

Publications (3)

Publication Number Publication Date
JP2001027945A JP2001027945A (ja) 2001-01-30
JP2001027945A5 true JP2001027945A5 (enExample) 2005-03-10
JP3683773B2 JP3683773B2 (ja) 2005-08-17

Family

ID=23228645

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000149271A Expired - Fee Related JP3683773B2 (ja) 1999-05-21 2000-05-22 Ｓｉｍｄ演算を実行するために標準ｍａｃユニットを利用する浮動小数点ユニット

Country Status (3)

Country Link
US (1) US6493817B1 (enExample)
EP (1) EP1055997A1 (enExample)
JP (1) JP3683773B2 (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8024394B2 (en) * 2006-02-06 2011-09-20 Via Technologies, Inc. Dual mode floating point multiply accumulate unit
CN101438232B (zh) * 2006-05-16 2015-10-21 英特尔公司 不同浮点格式的浮点加法
US8261025B2 (en) 2007-11-12 2012-09-04 International Business Machines Corporation Software pipelining on a network on chip
US8526422B2 (en) 2007-11-27 2013-09-03 International Business Machines Corporation Network on chip with partitions
US8327120B2 (en) * 2007-12-29 2012-12-04 Intel Corporation Instructions with floating point control override
US8473667B2 (en) 2008-01-11 2013-06-25 International Business Machines Corporation Network on chip that maintains cache coherency with invalidation messages
US8490110B2 (en) 2008-02-15 2013-07-16 International Business Machines Corporation Network on chip with a low latency, high bandwidth application messaging interconnect
US20090271172A1 (en) * 2008-04-24 2009-10-29 International Business Machines Corporation Emulating A Computer Run Time Environment
US8423715B2 (en) 2008-05-01 2013-04-16 International Business Machines Corporation Memory management among levels of cache in a memory hierarchy
US8392664B2 (en) 2008-05-09 2013-03-05 International Business Machines Corporation Network on chip
US8214845B2 (en) 2008-05-09 2012-07-03 International Business Machines Corporation Context switching in a network on chip by thread saving and restoring pointers to memory arrays containing valid message data
US8494833B2 (en) 2008-05-09 2013-07-23 International Business Machines Corporation Emulating a computer run time environment
US8230179B2 (en) 2008-05-15 2012-07-24 International Business Machines Corporation Administering non-cacheable memory load instructions
US8438578B2 (en) 2008-06-09 2013-05-07 International Business Machines Corporation Network on chip with an I/O accelerator
US8195884B2 (en) * 2008-09-18 2012-06-05 International Business Machines Corporation Network on chip with caching restrictions for pages of computer memory
CN101986264B (zh) * 2010-11-25 2013-07-31 中国人民解放军国防科学技术大学 用于simd向量微处理器的多功能浮点乘加运算装置
JP2012174016A (ja) 2011-02-22 2012-09-10 Renesas Electronics Corp データ処理装置およびそのデータ処理方法
WO2019005088A1 (en) * 2017-06-30 2019-01-03 Intel Corporation HETEROGENEOUS MULTIPLIER

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4901268A (en) * 1988-08-19 1990-02-13 General Electric Company Multiple function data processor
CA2007059C (en) * 1989-01-27 1994-05-24 Steven P. Davies Register and arithmetic logic unit
DE69519449T2 (de) * 1994-05-05 2001-06-21 Conexant Systems, Inc. Raumzeigersdatenpfad
DE69927075T2 (de) * 1998-02-04 2006-06-14 Texas Instruments Inc Rekonfigurierbarer Koprozessor mit mehreren Multiplizier-Akkumulier-Einheiten
US6292886B1 (en) * 1998-10-12 2001-09-18 Intel Corporation Scalar hardware for performing SIMD operations
US6205462B1 (en) * 1999-10-06 2001-03-20 Cradle Technologies Digital multiply-accumulate circuit that can operate on both integer and floating point numbers simultaneously

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