JP3683773B2 - Ｓｉｍｄ演算を実行するために標準ｍａｃユニットを利用する浮動小数点ユニット - Google Patents

Ｓｉｍｄ演算を実行するために標準ｍａｃユニットを利用する浮動小数点ユニット Download PDF

Info

Publication number
JP3683773B2
JP3683773B2 JP2000149271A JP2000149271A JP3683773B2 JP 3683773 B2 JP3683773 B2 JP 3683773B2 JP 2000149271 A JP2000149271 A JP 2000149271A JP 2000149271 A JP2000149271 A JP 2000149271A JP 3683773 B2 JP3683773 B2 JP 3683773B2
Authority
JP
Japan
Prior art keywords
multiply
bit
register file
unit
accumulate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000149271A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001027945A5 (enExample
JP2001027945A (ja
Inventor
プレストン・ジェイ・レンストローム
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2001027945A publication Critical patent/JP2001027945A/ja
Publication of JP2001027945A5 publication Critical patent/JP2001027945A5/ja
Application granted granted Critical
Publication of JP3683773B2 publication Critical patent/JP3683773B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/382—Reconfigurable for different fixed word lengths
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
JP2000149271A 1999-05-21 2000-05-22 Ｓｉｍｄ演算を実行するために標準ｍａｃユニットを利用する浮動小数点ユニット Expired - Fee Related JP3683773B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/316,340 US6493817B1 (en) 1999-05-21 1999-05-21 Floating-point unit which utilizes standard MAC units for performing SIMD operations
US316340 1999-05-21

Publications (3)

Publication Number Publication Date
JP2001027945A JP2001027945A (ja) 2001-01-30
JP2001027945A5 JP2001027945A5 (enExample) 2005-03-10
JP3683773B2 true JP3683773B2 (ja) 2005-08-17

Family

ID=23228645

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000149271A Expired - Fee Related JP3683773B2 (ja) 1999-05-21 2000-05-22 Ｓｉｍｄ演算を実行するために標準ｍａｃユニットを利用する浮動小数点ユニット

Country Status (3)

Country Link
US (1) US6493817B1 (enExample)
EP (1) EP1055997A1 (enExample)
JP (1) JP3683773B2 (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI361379B (en) * 2006-02-06 2012-04-01 Via Tech Inc Dual mode floating point multiply accumulate unit
WO2007133101A1 (en) * 2006-05-16 2007-11-22 Intel Corporation Floating point addition for different floating point formats
US8261025B2 (en) * 2007-11-12 2012-09-04 International Business Machines Corporation Software pipelining on a network on chip
US8526422B2 (en) 2007-11-27 2013-09-03 International Business Machines Corporation Network on chip with partitions
US8327120B2 (en) 2007-12-29 2012-12-04 Intel Corporation Instructions with floating point control override
US8473667B2 (en) 2008-01-11 2013-06-25 International Business Machines Corporation Network on chip that maintains cache coherency with invalidation messages
US8490110B2 (en) 2008-02-15 2013-07-16 International Business Machines Corporation Network on chip with a low latency, high bandwidth application messaging interconnect
US20090271172A1 (en) * 2008-04-24 2009-10-29 International Business Machines Corporation Emulating A Computer Run Time Environment
US8423715B2 (en) 2008-05-01 2013-04-16 International Business Machines Corporation Memory management among levels of cache in a memory hierarchy
US8392664B2 (en) 2008-05-09 2013-03-05 International Business Machines Corporation Network on chip
US8494833B2 (en) 2008-05-09 2013-07-23 International Business Machines Corporation Emulating a computer run time environment
US8214845B2 (en) 2008-05-09 2012-07-03 International Business Machines Corporation Context switching in a network on chip by thread saving and restoring pointers to memory arrays containing valid message data
US8230179B2 (en) 2008-05-15 2012-07-24 International Business Machines Corporation Administering non-cacheable memory load instructions
US8438578B2 (en) 2008-06-09 2013-05-07 International Business Machines Corporation Network on chip with an I/O accelerator
US8195884B2 (en) * 2008-09-18 2012-06-05 International Business Machines Corporation Network on chip with caching restrictions for pages of computer memory
CN101986264B (zh) * 2010-11-25 2013-07-31 中国人民解放军国防科学技术大学 用于simd向量微处理器的多功能浮点乘加运算装置
JP2012174016A (ja) 2011-02-22 2012-09-10 Renesas Electronics Corp データ処理装置およびそのデータ処理方法
US20200097799A1 (en) * 2017-06-30 2020-03-26 Intel Corporation Heterogeneous multiplier
CN115545179A (zh) * 2022-10-13 2022-12-30 中国人民解放军国防科技大学 Gpdsp中面向深度学习的高效计算装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4901268A (en) * 1988-08-19 1990-02-13 General Electric Company Multiple function data processor
CA2007059C (en) * 1989-01-27 1994-05-24 Steven P. Davies Register and arithmetic logic unit
DE69519449T2 (de) * 1994-05-05 2001-06-21 Conexant Systems, Inc. Raumzeigersdatenpfad
DE69927075T2 (de) * 1998-02-04 2006-06-14 Texas Instruments Inc Rekonfigurierbarer Koprozessor mit mehreren Multiplizier-Akkumulier-Einheiten
US6292886B1 (en) * 1998-10-12 2001-09-18 Intel Corporation Scalar hardware for performing SIMD operations
US6205462B1 (en) * 1999-10-06 2001-03-20 Cradle Technologies Digital multiply-accumulate circuit that can operate on both integer and floating point numbers simultaneously

Also Published As

Publication number Publication date
EP1055997A1 (en) 2000-11-29
JP2001027945A (ja) 2001-01-30
US6493817B1 (en) 2002-12-10

Similar Documents

Publication Publication Date Title
JP3683773B2 (ja) Ｓｉｍｄ演算を実行するために標準ｍａｃユニットを利用する浮動小数点ユニット
US7593978B2 (en) Processor reduction unit for accumulation of multiple operands with or without saturation
US8074058B2 (en) Providing extended precision in SIMD vector arithmetic operations
US7797363B2 (en) Processor having parallel vector multiply and reduce operations with sequential semantics
US6687810B2 (en) Method and apparatus for staggering execution of a single packed data instruction using the same circuit
JP3547139B2 (ja) プロセッサ
US8122078B2 (en) Processor with enhanced combined-arithmetic capability
US6092094A (en) Execute unit configured to selectably interpret an operand as multiple operands or as a single operand
TWI471801B (zh) 降低於一處理器之積和熔加運算（ｆｍａ）單元中之功率消耗的技術
US6122721A (en) Reservation station for a floating point processing unit
JPH07295813A (ja) 複数の型のオペレーションを同時並列で実行するためのプロセッサコア、およびオペレーションに用いられるオペランドデータを処理し通信する方法
US7013321B2 (en) Methods and apparatus for performing parallel integer multiply accumulate operations
US20030005261A1 (en) Method and apparatus for attaching accelerator hardware containing internal state to a processing core
JP2001027945A5 (enExample)
US5815420A (en) Microprocessor arithmetic logic unit using multiple number representations
CN101438236A (zh) 用以在微处理器内组合来自多个寄存器单元的对应半字单元的方法及系统
US6282558B1 (en) Data processing system and register file
US6678710B1 (en) Logarithmic number system for performing calculations in a processor
US6728741B2 (en) Hardware assist for data block diagonal mirror image transformation
US7519646B2 (en) Reconfigurable SIMD vector processing system
JP3693556B2 (ja) 浮動小数点ユニットにおいてロードバイパスを実行する方法及び装置
KR101056553B1 (ko) 마이크로프로세서 내에서 시프팅 및 라운딩 연산들을 수행하기 위한 방법 및 시스템
JP2002157114A (ja) 乗算器及びそれを搭載した集積回路装置
US6792442B1 (en) Signal processor and product-sum operating device for use therein with rounding function
JPH09319453A (ja) 低消費電力マイクロプロセッサ

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040401

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040401

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050426

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20050510

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20050526

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090603

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100603

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100603

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110603

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees