JP2001024191A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a low cost semiconductor device capable of preventing drop of breakdown voltage. SOLUTION: Boron with a dose of 5×1014 cm-2 to 1016 cm12 is selectively ion implanted in a non-doped polysilicon wiring, p+Poly 16 (p+ polysilicon) which is p-type diode and p+ layer 15 are simultaneously formed, and a length of the polysilicon wiring in which the ion is implanted is formed 1 μm to 15 μm. Adjacently to the region, As (rsenic) with a does of 5×1014 cm-2 to 1016 cm-2 is selectively ion implanted in the non-doped polysilicon wiring, n+Poly 20 (n+ polysilicon) which will be n+ layer 15 and n-type diode is simultaneously formed, and a length of the polysilicon wiring in which the ion is implanted is formed 1 μm to 15 μm.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MIS (insulated gate) semiconductor device such as a lateral power MOSFET having a main current path in a lateral direction, and more particularly to a method for stabilizing breakdown voltage and reducing on-resistance. The present invention relates to a semiconductor device manufacturing method that can be achieved.

[0002]

2. Description of the Related Art There is a so-called lateral power MOSFET which is manufactured from a semiconductor substrate surface side using a planar type diffusion technique and has a main current path in a lateral direction. This horizontal power MO
The SFET is characterized by using a RESURF technique or the like and, when a reverse bias is applied to the source and the drain, the depletion layer is extended in the lateral direction to ensure a withstand voltage. This horizontal power MOSFE
Since T can be configured by a standard IC process, it has been commercialized as a power IC in which a control circuit and a lateral power MOSFET are monolithically formed.

FIG. 33 shows an n-channel lateral power MOS.
A conventional example (conventional example 1) of an FET is shown. This conventional example is USP4
No. 811075. In FIG. 33, the p-type 1
P-substrate 10 which is a high-resistance semiconductor substrate of about 25 Ω · cm
1 is formed on the n.sup. ^{+ As} a source region 105 and a drain region 106 formed at an interval of about 80 μm from each other.
Region and a source region 105 and a drain region 106
A p-type base region 102 forming a channel portion on the side;
An n offset region 103 including ap ⁺ region 999 in contact with the source region 105 at a higher concentration than the base region 102 and a drain region 106 and extended to the source region 105 side.
And a p offset region 104 (fixed to the source potential) formed on the surface side of the n offset region 103, and a field oxide film 108 formed on the p offset region 104
A gate oxide film 107 formed on the channel portion;
A gate electrode 109 on the gate oxide film 107; a source electrode 111 on the source region 105;
An upper drain electrode 112, an interlayer film 113 and a protective film 116 are provided. Source region 105 of this element
When a reverse bias is applied between the drain region 106 and the
A depletion layer extends in a well-balanced manner at two pn junctions between the p substrate 101 and the n offset region 103 and between the n offset region 103 and the p offset region 104, thereby relaxing the electric field by connecting the two depletion layers. High withstand voltage. FIG. 33 shows a state in which 750 V is applied, and equipotential lines are shown at 150 V intervals.

[0004] By the way, an actual product is usually packaged in a plastic mold, but an ionic product (ion 11) is contained in the plastic mold.
5 or charge), which causes the following adverse phenomena.

That is, when a high voltage is applied between the source and the drain (particularly at a high temperature) of a lateral power MOSFET in a state of being packaged in a plastic mold, + ions 115a and positive charges in the plastic mold are removed from the source electrode 111. And the negative ions 115 b and negative charges are attracted to the drain electrode 112 side. As a result, as shown in FIG. 34, in the portion where the + ions 115a and the positive charges are gathered, the protective film 114, the interlayer film 113, and the field oxide film 108 are used as capacitors to form -charge 1 on the substrate side.
15c is induced, and the p offset layer 104 is partially
Acts in the direction of turning. Further, a + charge 115d is induced in a portion where the − ions 115b and the negative charges are collected, and p
It acts in the direction that partially turns the offset layer 104 p-rotation. Therefore, the initial p offset layer 104 is deformed to
It becomes like the offset layer 104a. Then, the balance of the extension of the depletion layer is lost, and the electric field is locally increased,
This causes a decrease in the breakdown voltage between the source and the drain.

On the other hand, in the conventional example 1 of FIG. 33, the main current path between the source and the drain in the ON state is the n-offset region 103, but the surface layer of the n-offset region 103 is depleted during reverse bias. Since the p-offset layer 104 is formed for the purpose of accelerating the drain voltage, the p-off layer 104 easily pinches off (JFET effect) as the drain voltage increases, causing an increase in on-resistance.

On the other hand, from the element structure of the conventional example 1, p
FIG. 35 shows a conventional example 2 in which the offset layer 104 is omitted. In this case, since there is no p-offset layer, it is difficult to pinch off, and the on-resistance can be suppressed small.
Since the n-junction is only the junction of the p-substrate and the n-offset,
When a reverse bias is applied between the source and the drain, the depletion of the n-offset does not proceed, and the breakdown voltage is lower than that of the conventional example 1 (about 450 V).

[0008]

From the above description, the problems are organized into two. The first problem is that, in the device of Conventional Example 1 in which plastic molding is performed, when a high voltage is applied between the source and the drain at a high temperature, ions and charges in the plastic molding are applied to the source electrode side and the drain electrode side. It is attracted and segregates, inducing charges of opposite polarity on the substrate side using the protective film or the like as a capacitor, partially p-turning the p-offset layer, disrupting the balance of depletion, and lowering the breakdown voltage between the source and drain. That is.

The second problem is that in the element structure of the conventional example 1, the n-offset, which is the main current path in the ON state, is different from the p-substrate and p-type.
Since the pinch is sandwiched by the offsets, the pinch-off is easily caused with the rise of the drain voltage, so that the on-resistance is high. On the other hand, in the structure in which the p-offset is removed to reduce the on-resistance, the n-offset is depleted. There is a problem that it becomes difficult to make the structure difficult and the breakdown voltage is reduced.
SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device which solves the above-mentioned problems and can prevent a decrease in breakdown voltage at low cost.

[0010]

In order to achieve the above object, a first region of the first conductivity type having a higher concentration than the first conductivity type semiconductor substrate formed on a surface layer of the first conductivity type semiconductor substrate is provided. And a second region of a second conductivity type having a higher concentration than the first region formed on the surface layer of the first region and the second region formed on the surface layer of the first region in contact with the second region. A third region of a first conductivity type having a higher concentration than the first region, and contacting the first region;
A fourth region of a second conductivity type doped at a higher concentration than the semiconductor substrate of the first conductivity type, which is formed by either isolating or enclosing the first region; A fifth region of a second conductivity type having a higher concentration than a fourth region formed in a surface layer; and the first region including the first region and the fourth region.
A first insulating film formed on a conductive semiconductor substrate, a first electrode electrically contacting the second region and the third region,
In a method of manufacturing a semiconductor device provided with a second electrode that is in electrical contact with the fifth region, a polysilicon wiring connecting the first electrode and the second electrode is formed on the first insulating film. And a step of alternately and selectively implanting first conductivity type impurities and second conductivity type impurities into the polysilicon wiring to form a plurality of stages of pn diodes.

The step of forming the polysilicon wiring comprises:
The method may include a step of forming a polysilicon thin film by a low-pressure CVD method, and a step of patterning and etching the polysilicon thin film by a photoetching method.

A step of simultaneously performing ion implantation of a first conductivity type impurity for forming the third region and ion implantation of a first conductivity type impurity for forming a pn diode of the polysilicon wiring under the same conditions. Good.

Under the same conditions, ion implantation of a second conductivity type impurity for forming the second region and the fifth region and ion implantation of a second conductivity type impurity for forming a pn diode of the polysilicon wiring are performed. It is good to include the process performed simultaneously.

The method may include a step of setting a dose amount of the first conductivity type impurity at the time of ion implantation to 5 × 10 ¹⁴ cm ^{−2 to} 5 × 10 ¹⁶ cm ⁻² . The method may include a step of setting a dose amount of the second conductivity type impurity at the time of ion implantation to 5 × 10 ¹⁴ cm ^{−2 to} 5 × 10 ¹⁶ cm ⁻² .

The length of the first portion where the first conductivity type impurity is ion-implanted into the polysilicon wiring is 1 μm to 15 μm.
May be included. The second polysilicon wiring
The length of the second portion where the conductivity type impurity is ion-implanted is 1 μm.
It is preferable to include a step of setting the thickness to m to 15 μm.

The first region of the first conductivity type having a higher concentration than the first conductivity type semiconductor substrate formed on the surface layer of the first conductivity type semiconductor substrate, and the first region formed on the surface layer of the first region. A second region of a second conductivity type having a higher concentration than the first region, and a third region of a first conductivity type having a higher concentration than the first region formed on a surface layer of the first region in contact with the second region; A second conductive type second conductive type, which is formed to be in contact with, separated from, or enclosing the first region, doped at a higher concentration than the first conductive type semiconductor substrate. Four regions and the fourth region
A fifth region of a second conductivity type having a higher concentration than a fourth region formed on a surface layer of the region, and a first region formed on the first conductivity type semiconductor substrate including the first region and the fourth region. An insulating film,
In a method for manufacturing a semiconductor device comprising: a first electrode electrically in contact with the second region and the third region; and a second electrode in electrical contact with the fifth region, It is preferable that the manufacturing method includes a step of forming a high resistance thin film wiring connecting the second electrode on the first insulating film.

The step of forming the high-resistance thin-film wiring includes forming a polysilicon thin film by a low-pressure CVD method;
The method may include a step of patterning the polysilicon thin film by a photo-etching method and a step of etching the polysilicon thin film.

It is preferable that the step of forming the high-resistance thin film wiring includes a step of forming a non-doped polysilicon thin film. The step of forming the high-resistance thin-film wiring comprises a doped
It is preferable to include a step of forming with polysilicon.

It is preferable that the step of forming the high-resistance thin-film wiring includes a step of forming a non-doped polysilicon thin film and a step of adding an impurity to the polysilicon thin film by ion implantation.

Preferably, the step of forming the high resistance thin film wiring includes a step of forming a non-doped polysilicon film and a step of adding an impurity to the polysilicon thin film by a vapor phase diffusion method.

As described above, the polysilicon thin film formed by the low pressure CVD method on the field oxide film between the first electrode (source electrode) and the second electrode (drain electrode) is processed by photolithography to form a spiral. After forming a high-resistance thin film wiring in the form of a thin film or by processing a polysilicon thin film formed by a low pressure CVD method on a field oxide film between a source electrode and a drain electrode by photoetching, the second element (transistor) is formed. Area (source area)
Implantation of a p-type impurity and an n-type impurity for forming a third region (a drain region) and a third region (a high-concentration region), and a p-type impurity and an n for forming a pn diode in a polysilicon wiring. The manufacturing cost is reduced by using a method of forming a spiral pn diode in a plurality of stages by simultaneously performing ion implantation of the type impurity, thereby reducing the manufacturing cost. A substantially uniform potential gradient is obtained in the thin film layer due to the current flowing through the resistive thin film wiring and the saturation current of the pn diode, and the potential on the substrate side becomes substantially equal to the potential of the spiral thin film layer.
A stable breakdown voltage can be obtained.

Further, since the spiral thin film layer has a shielding effect against disturbances such as ions and charges in the plastic mold, even when a high voltage is applied at a high temperature, the fluctuation of the withstand voltage is extremely unlikely to occur. Make devices available.

That is, when a reverse bias is applied to the source and the drain, a reverse bias saturation current or a resistance current of the diode flows through this thin film layer, so that the thin film layer itself has a substantially uniform potential gradient. In an actual device, a thin film layer having a certain width and a certain interval is periodically arranged on the field oxide film, and acts as a field plate whose potential changes every one rotation. Because of the field plate effect, the substrate potential below the spiral thin film layer is forced to approach the potential of the thin film layer, and the potential gradient in the depletion layer inside the device becomes substantially uniform. Further, since the thin film layer itself has a shielding effect against disturbances such as ions and charges in the plastic mold, fluctuations in withstand voltage are extremely unlikely to occur even when a high voltage is applied at a high temperature.

On the other hand, since the field plate effect is obtained by forming the spiral-shaped polysilicon thin film layer, the concentration of the p-offset region which causes the increase of the on-resistance is determined by the optimum concentration condition without the polysilicon thin film layer ( The concentration can be made lower than that under the condition that the breakdown voltage can be secured.

By lowering the density of the p offset region,
Substantially lower n-offset resistance can be achieved, and the on-resistance of the device can be reduced. That is, since the n-offset resistance serving as a main current path at the time of turning on can be substantially reduced, the on-resistance of the element can be reduced. As a result, in the case of the same on-resistance, the chip area of the semiconductor device can be reduced, so that a significant cost reduction can be achieved.

Further, since the ion implantation for forming the spiral polysilicon thin film layer also serves as the ion implantation for forming the source region and the drain region of the device, the number of steps can be reduced. Cost reduction can be achieved.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. FIG.
FIG. 3 is a plan view of a principal part of the semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first embodiment of the present invention; Reference numeral 27 denotes a spiral thin film layer, which is a spiral polysilicon having a pn diode 28. 16 is p ⁺ Poly (p ⁺ polysilicon, which corresponds to the p layer of the pn diode), and 20 is n ⁺ P
poly (n ⁺ polysilicon, corresponding to the n layer of the pn diode). 24 is a source electrode and 25 is a drain electrode.

FIGS. 2 to 15 show a method of manufacturing a semiconductor device according to a first embodiment of the present invention.
It is principal part process sectional drawing cut | disconnected by the line. In the step shown in FIG. 2, boron is applied to the p-type substrate 1 under the conditions of an acceleration energy of 50 keV and a dose of 5 × 10 ¹⁵ cm ^{−2 to} 5 × 10 ¹⁶ cm ⁻² by using a resist mask. The p-offset region 2 is formed by selective ion implantation at the location,
Under a condition of 0 keV, 5 × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ⁻² , phosphorus is selectively ion-implanted into a desired place using a resist mask to form an n-offset region 3, and 50 keV , 5 × 10 ¹³ cm ^-2 to 1 × 10 ¹⁴ cm ^-2
Boron is selectively ion-implanted into a desired location by using a resist mask under the condition (1) to form a p base region 4.
Next, an SiO ₂ film 5 is formed by a thermal oxidation method, and Si ₃ N ₄
The film 6 is formed by low pressure CVD, laminated SiO ₂
By processing the film 5 and the Si ₃ N ₄ film 6 by a photo-etching method (a method of patterning and etching by photolithography), a mask for forming a field oxide film is formed.

In the step shown in FIG.
SiO ₂ film 5 and Si ₃ N ₄
A field oxide film 7 (LOCOS) for element isolation is formed to a thickness of about 1 μm on the silicon surface not covered with the film 6, and the SiO ₂ film 5 and Si ₃ N used as masks are formed.
_{4 The} film 6 is removed by a wet etching method.

In the step shown in FIG.
Gate oxide film 8 of transistor by dry oxidation
Of about 25 nm. In the step shown in FIG.
A doped polysilicon film is formed to a thickness of about 300 nm by a VD method (low-pressure CVD method), and a gate electrode 9 is formed by a photoetching method.

In the step shown in FIG. 6, a thermal oxide film 10 is formed on the gate electrode 9 by a dry oxidation method. In the step shown in FIG. 7, a non-doped polysilicon film is formed to a thickness of about 300 nm by LP-CVD, and a non-doped polysilicon wiring 11 is formed by photo-etching so as to have a width of 3 μm to 5 μm and an interval of 3 μm to 5 μm. I do.

In the steps shown in FIGS. 8 and 9, the photoresist 12 is used to apply 65 keV, 5 × 10 ¹⁴ cm to the p ⁺ contact portion 13 and the non-doped polysilicon wiring 11.
The B (boron) 14 under the condition of ^{-2 ~5} × 10 ¹⁶ cm ^-2 selectively ion-implanted, forming a p ⁺ POLY16 (p ⁺ polysilicon film) to become a p ⁺ region 15 and p-type diode simultaneously I do. At this time, the length of the non-doped (non-doped) polysilicon wiring 11 at the location where B (boron) 14 is implanted (corresponding to the location where p ⁺ Poly 16 is formed in FIG. 1) is set to 1 μm to It is 15 μm.
The reason why this length is necessary is to prevent p ⁺ Poly16 from being inverted to n-type even if arsenic of adjacent n ⁺ Poly20 diffuses laterally into p ⁺ Poly16 in the subsequent heat treatment.

In the steps shown in FIG. 10 and FIG.
N using gyst 17⁺Contact point 18 and contact
80 keV, 5 × 10¹⁴
cm ^-2~ 5 × 10¹⁶cm^-2Under the condition of As (arsenic) 29
Selective ion implantation and n⁺Region 19 (right of the figure)
The drain is on the side and the source is on the left) and n-type diode
Become n⁺Poly20 (n⁺Polysilicon film)
I do. At this time, As29 is injected as shown in FIG.
Location (n in FIG. 1)⁺At the place where Poly20 is formed
(Corresponding) length of non-doped polysilicon wiring 11
Is set to 1 μm to 15 μm. This length is necessary because
In the subsequent heat treatment, the adjacent p⁺Poly16 boron
Is n⁺Even if it diffuses laterally to Poly20, n⁺Poly
This is to prevent 20 from inverting to p-type. That
After that, in a nitrogen atmosphere, at 850 ° C. to 950 ° C. for about 10 minutes
Heat treatment is performed to activate the ion-implanted impurities.

In the steps shown in FIGS. 12 and 13, the normal pressure CV
Interlayer insulating film 21 composed of an oxide film and a BPSG film by D method
Is formed to a thickness of 500 nm, and a contact hole 23 is formed by photoetching using the photoresist 22 as a mask. In the step shown in FIG.
lSiCu is deposited to a thickness of about 1 μm, and a source electrode 24 and a drain electrode 25 are formed by a photoetching method.

In the step shown in FIG.
A nitride film is formed to a thickness of 1 μm by a plasma CVD method using SiH ₄ , N ₂ , and NH ₃ as source gases at a temperature of 400 ° C. to 400 ° C. to form a passivation film 26, and a photoetching method
Although not shown, a pad for taking out an electrode is opened.

Next, FIGS. 16 to 30 show the second embodiment of the present invention.
A method for manufacturing the semiconductor device according to the embodiment will be described. FIG.
FIG. 6 is a plan view of a main part of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the second embodiment of the present invention. 77 is a spiral high resistance thin film wiring, 24 is a source electrode, and 25 is a drain electrode.

FIGS. 17 to 30 show a method of manufacturing a semiconductor device according to a second embodiment of the present invention.
It is principal part process sectional drawing cut | disconnected by the A 'line. Reference numeral 47 denotes a spiral thin film layer, which is a high-resistance thin film wiring 31 described later.

In the step shown in FIG.
keV, 5 × 10^Fifteencm^-2~ 2 × 10¹⁶cm^-2Under the conditions
Selective boron at desired location using resist mask
To form a p-offset region 2, and then
50 keV, 5 × 10¹²cm ^-2~ 1 × 10¹³cm^-2Article
Selected phosphorus at desired location using resist mask
To form an n-offset region 3 by ion implantation.
50 keV, 5 × 10¹³cm^-2Cash register for boron
Selective ion implantation at desired locations using a strike mask
Thus, p base region 4 is formed. Next, SiO_Two Heat film 5
Formed by oxidation method, Si_ThreeN_Four Film 6 is reduced pressure CVD
Formed and laminated SiO_Two Film 5 and Si_ThreeN_Four 
By processing the film 6 by photo etching,
A mask for forming a gate oxide film is formed.

In the step shown in FIG.
SiO ₂ film 5 and Si ₃ N ₄ by selective oxidation at 000 ° C.
A field oxide film 7 (LOCOS) for element isolation is formed to a thickness of about 1 μm on the silicon surface not covered with the film 6, and the SiO ₂ film 5 and Si ₃ N used as masks are formed.
_{The four} films 6 are removed by a wet etching method.

In the step shown in FIG.
A gate oxide film 8 of the transistor is formed to a thickness of about 25 nm by a dry oxidation method at 0 ° C. In the step shown in FIG.
About 300 n of doped polysilicon by CVD method
Then, a gate electrode 10 is formed by a photoetching method.

In the step shown in FIG. 21, a thermal oxide film 10 is formed on gate electrode 9 by a dry oxidation method. The manufacturing steps so far are the same as the manufacturing steps of the first embodiment. In the step shown in FIG. 22, non-doped polysilicon is formed to a thickness of about 300 nm by LP-CVD, and the width is, for example, 3 μm to 5 μm and the interval is 3 μm to 5 μm by photoetching.
Then, a non-doped polysilicon wiring to be the high-resistance thin-film wiring 31 is formed. The high-resistance thin-film wiring 31
May be obtained by ion-implanting impurities into doped polysilicon or non-doped polysilicon.

In the steps shown in FIGS. 23 and 24, a photoresist 32 is used to form a p ⁺ contact portion 33 and a 6
B (boron) 14 under the condition of 5 keV, 5 × 10 ¹⁴ cm ^-2
Are selectively ion-implanted, and at the same time, p ⁺ region 15 and p ⁺
Poly 36 is formed.

In the steps shown in FIGS.
N using gyst 37⁺80k at contact point 38
eV, 5 × 10¹⁴cm^-2~ 5 × 10¹⁶cm^-2A under the condition
s29 is selectively ion-implanted into n⁺Form region 19
You. In the second embodiment, the high resistance thin film wiring 31
In the part that makes contact with Mi, p⁺Contact point 33
B (boron) 14 selectively at the same time as ion implantation into
Ion implantation, but n ⁺Ion to contact point 38
Simultaneously with implantation, As (arsenic) 29 is selectively ion-implanted.
Obviously, you can. Then, nitrogen atmosphere,
850 ℃ ～ 950 ℃, heat treatment for about 10 minutes, ion
Activate the implanted impurities.

In the steps shown in FIGS. 27 and 28, the normal pressure CV
Interlayer insulating film 21 composed of an oxide film and a BPSG film by D method
Is formed to a thickness of 500 nm, and then a contact hole 40 is formed by photoetching using the photoresist 39 as a mask. In the step shown in FIG. 29, AlSiCu is deposited to a thickness of about 1 μm by a sputtering method, and a source electrode 24 and a drain electrode 25 are formed by a photoetching method.

In the step shown in FIG.
A plasma CVD method using SiH ₄ , N ₂ , NH ₃ as a source gas at a temperature of 400 ° C. to 400 ° C. forms a nitride film to a thickness of 1 μm to form a passivation film 26. Open the pad.

The source electrode 24 and the drain electrode 2 are formed by using the method of manufacturing the semiconductor device of the first and second embodiments.
5, a spiral thin film layer 27 on the field oxide film 7
When a reverse bias is applied between the source and the drain, a substantially uniform potential gradient is obtained in the spiral thin film layers 27 and 47 by the saturation current of the pn diode and the current flowing through the resistor, and the potential on the substrate side is obtained. Is a spiral thin film layer 2
The potential becomes substantially equal to the potentials of 7 and 47, and a stable breakdown voltage can be obtained. Furthermore, since the spiral thin film layers 27 and 47 have a shielding effect against disturbances such as ions and electric charges in the plastic mold, fluctuations in withstand voltage are extremely unlikely to occur even when a high voltage is applied at a high temperature. A semiconductor device can be provided.

FIGS. 31 and 32 show the dependence of the breakdown voltage and the on-resistance on the p-offset concentration. This is experimental data. From FIG. 31, there is a condition that a desired breakdown voltage can be ensured even if the concentration of the p-offset is reduced and the surface concentration of the n-offset is slightly reduced (that is, diffusion is formed so as not to cause the p-rotation). Further, as shown in FIG. 32, in the case of a diffusion layer having a lower concentration and a lower n-offset, a desired breakdown voltage may be ensured even without a p-offset.

That is, by forming the spiral-shaped polysilicon thin film layer, it is possible to reduce the concentration of the p-offset layer, which has caused the increase of the on-resistance, and to lower the element by substantially reducing the n-offset resistance. ON resistance can be achieved. That is, since the n-offset resistance serving as a main current path at the time of turning on can be substantially reduced, the on-resistance of the element can be reduced.

As a result, in the case of the same on-resistance, the chip area of the semiconductor device (for example, power MOSFET) can be reduced by about 40%, so that the cost can be significantly reduced.

In the present invention, the ion implantation for forming the spiral polysilicon thin film layer also serves as the ion implantation for forming the source region and the drain region, so that the number of steps can be reduced. , A significant cost reduction is possible. Further, the present invention can be applied to a power IC in which the power MOS and the control circuit unit are monolithically integrated.

In the first and second embodiments, the case where the p base 4 is in contact with the n offset 3 has been described as an example. However, the case where the p base 4 is separated from the n offset 3 or the case where the p base 4 is It may be wrapped in n offset 3. In that case, the process does not change.

[0052]

According to the manufacturing method of the present invention, a spiral thin film layer is formed on a field oxide film between a first main electrode (source electrode) and a second main electrode (drain electrode).
By combining the ion implantation process for forming the thin film wiring of the n-diode group and the high resistance thin film wiring with the ion implantation of the source region and the drain region, the number of manufacturing steps can be significantly reduced, and the cost can be reduced. Can be.

By optimizing the impurity concentration of the p offset region and the impurity concentration of the n offset region,
The breakdown voltage of the semiconductor device can be stabilized while reducing the chip area, and the reliability of the breakdown voltage can be improved.

[Brief description of the drawings]

FIG. 1 is a main part plan view of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view of a main step of the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a sectional view of a main part process of the semiconductor device according to the first embodiment of the present invention, following FIG. 2;

FIG. 4 is a sectional view of a main part process of the semiconductor device according to the first embodiment of the present invention, following FIG. 3;

FIG. 5 is a cross-sectional view of a main part process of the semiconductor device of the first embodiment of the present invention, following FIG. 4;

FIG. 6 is a sectional view of a main part process of the semiconductor device of the first embodiment of the present invention, following FIG. 5;

FIG. 7 is a cross-sectional view of a main part process of the semiconductor device of the first embodiment of the present invention, following FIG. 6;

FIG. 8 is a sectional view of a main step of the semiconductor device according to the first embodiment of the present invention, following FIG. 7;

FIG. 9 is a sectional view of a main step of the semiconductor device of the first embodiment of the present invention, following FIG. 8;

FIG. 10 is a sectional view of the main part process of the semiconductor device of the first embodiment of the present invention, following FIG. 9;

FIG. 11 is a sectional view of the main part process of the semiconductor device of the first embodiment of the present invention, following FIG. 10;

FIG. 12 is a sectional view of a main part process of the semiconductor device of the first embodiment of the present invention, following FIG. 11;

FIG. 13 is a sectional view of the main part process of the semiconductor device of the first embodiment of the present invention, following FIG. 12;

FIG. 14 is a cross-sectional view of a main part process of the semiconductor device of the first embodiment of the present invention, following FIG. 13;

FIG. 15 is a sectional view of a main step of the semiconductor device of the first embodiment of the present invention, following FIG. 14;

FIG. 16 is a plan view of a main part of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to a second embodiment of the present invention;

FIG. 17 is a sectional view showing a main step of a semiconductor device according to a second embodiment of the present invention;

FIG. 18 is a sectional view of the main part process of the semiconductor device of the second embodiment of the present invention, following FIG. 17;

FIG. 19 is a sectional view of a main step of the semiconductor device of the second embodiment of the present invention, following FIG. 18;

FIG. 20 is a sectional view of the main part process of the semiconductor device of the second embodiment of the present invention, following FIG. 19;

FIG. 21 is a sectional view of the main part process of the semiconductor device of the second embodiment of the present invention, following FIG. 20;

FIG. 22 is a sectional view of a main step of the semiconductor device of the second embodiment of the present invention, following FIG. 21;

FIG. 23 is a sectional view of the main part process of the semiconductor device of the second embodiment of the present invention, following FIG. 22;

FIG. 24 is a sectional view of the main part process of the semiconductor device of the second embodiment of the present invention, following FIG. 23;

FIG. 25 is a sectional view of the main part process of the semiconductor device of the second embodiment of the present invention, following FIG. 24;

FIG. 26 is a sectional view of a main step of the semiconductor device of the second embodiment of the present invention, following FIG. 25;

FIG. 27 is a sectional view of the main part process of the semiconductor device of the second embodiment of the present invention, following FIG. 26;

FIG. 28 is a cross-sectional view of a main part process of the semiconductor device of the second embodiment of the present invention, following FIG. 27;

FIG. 29 is a sectional view of a main step of the semiconductor device of the second embodiment of the present invention, following FIG. 28;

FIG. 30 is a sectional view of the main part process of the semiconductor device of the second embodiment of the present invention, following FIG. 29;

FIG. 31 is a diagram showing the dependence of the breakdown voltage and the on-resistance on the p-offset concentration.

FIG. 32 is a diagram showing the dependence of the breakdown voltage and the on-resistance on the p-offset concentration.

FIG. 33 is a cross-sectional view of essential parts and an equipotential diagram of Conventional Example 1 (initial state).

FIG. 34 is a sectional view of a main part and an equipotential diagram of Conventional Example 1 (when the withstand voltage fluctuates).

FIG. 35 is a sectional view of an essential part and an equipotential diagram of the conventional example 2.

[Explanation of symbols]

Reference Signs List 1 p substrate 2 p offset region 3 n offset region 4 p base region 5 SiO ₂ film 6 Si ₃ N ₄ film 7 field oxide film 8 gate oxide film 9 gate electrode 10 thermal oxide film 11 polysilicon wiring 12, 17, 22, 32, 37, 39 Photoresist 13, 33 p ⁺ contact location 14 B (boron) 15 p ⁺ layer 16, 36 p ⁺ Poly 18, 38 n ⁺ contact location 19 n ⁺ layer 20 n ⁺ Poly 21 interlayer insulating film 23, DESCRIPTION OF SYMBOLS 40 Contact hole 24 Source electrode 25 Drain electrode 26 Passivation film 27, 47 Spiral thin film layer 28 pn diode 29 As (arsenic) 31 High resistance thin film wiring

Continuation of the front page (72) Inventor Gen Tada 1-1, Tanabe Nitta, Kawasaki-ku, Kawasaki, Kanagawa Prefecture Inside Fuji Electric Co., Ltd. (72) Inventor Akio Kitamura 1-1, Tanabe Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa Fuji F term (reference) in Denki Co., Ltd. 5F040 DA00 DA22 DB06 EB02 EC07 EF11 EF18 EK01 EL02 FC00 FC11 5F048 AA05 AB10 AC10 BA01 BB05 BC03 BC05 BG01 BG12 CC06

Claims (14)

[Claims] A first region of a first conductivity type having a higher concentration than the first conductivity type semiconductor substrate formed on a surface layer of the first conductivity type semiconductor substrate; and a first region formed on the surface layer of the first region. A second region of a second conductivity type having a higher concentration than the first region and a third region of a first conductivity type having a higher concentration than the first region formed on a surface layer of the first region in contact with the second region; A second conductivity type doped at a higher concentration than the first conductivity type semiconductor substrate, the second conductivity type being formed in contact with, separated from, or including the first region; And a fourth region of
A fifth region of a second conductivity type having a higher concentration than a fourth region formed on a surface layer of the region, and a first region formed on the first conductivity type semiconductor substrate including the first region and the fourth region. An insulating film,
In a method for manufacturing a semiconductor device comprising: a first electrode electrically in contact with the second region and the third region; and a second electrode in electrical contact with the fifth region, The polysilicon wiring connecting the second electrode is connected to the first electrode.
Forming on the insulating film, and forming a first
Forming a plurality of stages of pn diodes by alternately and selectively ion-implanting a conductivity type impurity and a second conductivity type impurity. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the polysilicon wiring includes the step of forming a polysilicon thin film by a low-pressure CVD method, and the step of forming the polysilicon thin film by a photo-etching method. A method of manufacturing a semiconductor device, comprising the steps of: 3. The method of manufacturing a semiconductor device according to claim 1, wherein ions of a first conductivity type impurity for forming the third region are implanted, and a first conductivity for forming a pn diode of the polysilicon wiring is formed. A method for manufacturing a semiconductor device, comprising the step of simultaneously performing ion implantation of type impurities under the same conditions. 4. A method of manufacturing a semiconductor device according to claim 1, wherein ions of a second conductivity type for forming said second region and said fifth region are implanted, and a pn diode for said polysilicon wiring is formed. And a step of simultaneously performing ion implantation of a second conductivity type impurity under the same conditions. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the dose of the first conductivity type impurity at the time of ion implantation is 5 × 10 ¹⁴ cm ^{−2 to} 5 × 10 ¹⁶ cm ^−2. A method for manufacturing a semiconductor device, comprising: 6. The method of manufacturing a semiconductor device according to claim 4, wherein the step of setting the dose at the time of ion implantation of the second conductivity type impurity to 5 × 10 ¹⁴ cm ^{−2 to} 5 × 10 ¹⁶ cm ^−2. A method for manufacturing a semiconductor device, comprising: 7. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of setting a length of the first portion where the first conductivity type impurity is ion-implanted into the polysilicon wiring to 1 μm to 15 μm. A method for manufacturing a semiconductor device. 8. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of setting a length of a second portion where the second conductivity type impurity is ion-implanted into the polysilicon wiring to 1 μm to 15 μm. A method for manufacturing a semiconductor device. 9. A first region of a first conductivity type having a higher concentration than the first conductivity type semiconductor substrate formed on a surface layer of the first conductivity type semiconductor substrate, and a first region formed on the surface layer of the first region. A second region of a second conductivity type having a higher concentration than the first region and a third region of a first conductivity type having a higher concentration than the first region formed on a surface layer of the first region in contact with the second region; A second conductivity type doped at a higher concentration than the first conductivity type semiconductor substrate, the second conductivity type being formed in contact with, separated from, or including the first region; And a fourth region of
A fifth region of a second conductivity type having a higher concentration than a fourth region formed on a surface layer of the region, and a first region formed on the first conductivity type semiconductor substrate including the first region and the fourth region. An insulating film,
In a method for manufacturing a semiconductor device comprising: a first electrode electrically in contact with the second region and the third region; and a second electrode in electrical contact with the fifth region, A method of manufacturing a semiconductor device, comprising: forming a high-resistance thin-film wiring connecting the second electrode on the first insulating film. 10. The method of manufacturing a semiconductor device according to claim 9, wherein said step of forming said high-resistance thin-film wiring includes forming a polysilicon thin film by a low-pressure CVD method and photo-etching said polysilicon thin film. A method of manufacturing a semiconductor device, comprising: a step of patterning by means of a semiconductor device; and a step of etching a polysilicon thin film. 11. The method of manufacturing a semiconductor device according to claim 9, wherein the step of forming a high-resistance thin film wiring includes a step of forming a non-doped polysilicon thin film. 12. The method of manufacturing a semiconductor device according to claim 9, wherein the step of forming the high-resistance thin-film wiring includes a step of forming doped polysilicon. 13. The method of manufacturing a semiconductor device according to claim 9, wherein said step of forming said high-resistance thin-film wiring comprises forming a non-doped polysilicon thin film and implanting impurities into said polysilicon thin film by ion implantation. And a step of adding. 14. The method of manufacturing a semiconductor device according to claim 9, wherein said step of forming said high-resistance thin-film wiring includes forming a non-doped polysilicon film and vapor-phase diffusing impurities into said polysilicon thin film. A method for manufacturing a semiconductor device, comprising a step of adding by a method.