JP2000516398A - 半導体ウェーハを分離する方法 - Google Patents
半導体ウェーハを分離する方法Info
- Publication number
- JP2000516398A JP2000516398A JP10509301A JP50930198A JP2000516398A JP 2000516398 A JP2000516398 A JP 2000516398A JP 10509301 A JP10509301 A JP 10509301A JP 50930198 A JP50930198 A JP 50930198A JP 2000516398 A JP2000516398 A JP 2000516398A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- cover layer
- semiconductor
- separating
- cutting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1. 多数の光電子的な半導体構造を備えた半導体ウェーハ(1)を分離研磨によ って所定の数の個別チップ(9,10)に分離する方法において、 (イ)光電子的な半導体構造を備えた半導体ウェーハ(1)の表面(4)に カバー層(7)を全面的に沈着し、 (ロ)切断軌跡(6)の領域でカバー層(7)が取り除かれるようにカバー 層(7)を構造化し、 (ハ)切断工具を用いて、切断工具と半導体ウェーハ(1)とを互いに相対 的に切断軌跡(6)に沿って案内して分離研磨することによって、半導体ウェー ハ(1)を所定の数の個別チップ(9,10)に分離し、 (ニ)半導体ウェーハ(1)の分離後にチップ側面(11)をエッチングし 、 (ホ)カバー層(7)を取り除く ことを特徴とする、半導体ウェーハを分離する方法。 2. カバー層をフォトレジスト材料から形成し、カバー層の構造化を、フオトマ スクによる写真技術的な露光プロセスと、続く現像プロセスとによって行なう、 請求項1記載の方法。 3. 全面的に沈着されたカバー層(7)の厚さを最小 でほぼ5μmにする、請求項1または2記載の方法。 4. 半導体ウェーハ(1)に基礎材料として、III−V−半導体、特にGaA lAsまたはInPを使用する、請求項1から3までのいずれか1項記載の方法 。 5. 半導体ウェーハ(1)に形成されるダイオード構造に特に発光ダイオードを 使用する、請求項1から4までのいずれか1項記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19632815.2 | 1996-08-14 | ||
DE19632815 | 1996-08-14 | ||
PCT/DE1997/001756 WO1998007190A1 (de) | 1996-08-14 | 1997-08-14 | Verfahren zum trennen einer halbleiterscheibe |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2000516398A true JP2000516398A (ja) | 2000-12-05 |
Family
ID=7802651
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10509301A Ceased JP2000516398A (ja) | 1996-08-14 | 1997-08-14 | 半導体ウェーハを分離する方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6281031B1 (ja) |
EP (1) | EP0944920B1 (ja) |
JP (1) | JP2000516398A (ja) |
DE (1) | DE59705221D1 (ja) |
WO (1) | WO1998007190A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6465353B1 (en) * | 2000-09-29 | 2002-10-15 | International Rectifier Corporation | Process of thinning and blunting semiconductor wafer edge and resulting wafer |
US20040245216A1 (en) * | 2003-06-06 | 2004-12-09 | Chien-Shing Pai | Devices and method of their manufacture |
CN113224005A (zh) * | 2021-04-08 | 2021-08-06 | 深圳市德明利光电有限公司 | 一种芯片切割道工艺方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4476620A (en) * | 1979-10-19 | 1984-10-16 | Matsushita Electric Industrial Co., Ltd. | Method of making a gallium nitride light-emitting diode |
DE3335395A1 (de) * | 1983-09-29 | 1985-04-18 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zur verarbeitung von halbleiterbauelementen |
JPS61180442A (ja) * | 1985-02-05 | 1986-08-13 | Toshiba Corp | 半導体装置の製造方法 |
GB2172141B (en) * | 1985-03-08 | 1988-11-16 | Stc Plc | Single heterostructure laser chip manufacture |
US5171716A (en) * | 1986-12-19 | 1992-12-15 | North American Philips Corp. | Method of manufacturing semiconductor device with reduced packaging stress |
DE4036578C2 (de) | 1990-11-16 | 1993-12-16 | Man Nutzfahrzeuge Ag | Verfahren zur Verzögerung eines Schiffsantriebes, insbesondere bei einem Not-Stop-Manöver, sowie Vorrichtung zur Durchführung des Verfahrens |
US5435876A (en) * | 1993-03-29 | 1995-07-25 | Texas Instruments Incorporated | Grid array masking tape process |
-
1997
- 1997-08-14 DE DE59705221T patent/DE59705221D1/de not_active Expired - Fee Related
- 1997-08-14 WO PCT/DE1997/001756 patent/WO1998007190A1/de active IP Right Grant
- 1997-08-14 JP JP10509301A patent/JP2000516398A/ja not_active Ceased
- 1997-08-14 EP EP97937458A patent/EP0944920B1/de not_active Expired - Lifetime
-
1999
- 1999-02-16 US US09/250,866 patent/US6281031B1/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0944920A1 (de) | 1999-09-29 |
EP0944920B1 (de) | 2001-10-31 |
US6281031B1 (en) | 2001-08-28 |
WO1998007190A1 (de) | 1998-02-19 |
DE59705221D1 (de) | 2001-12-06 |
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Legal Events
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A602 | Written permission of extension of time |
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A313 | Final decision of rejection without a dissenting response from the applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A313 Effective date: 20070420 |
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A02 | Decision of refusal |
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